JPH09331065A - Thin film transistor and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a thin film transistor suppressing an increase in an off current without largely decreasing an on current. SOLUTION: In the thin film transistor comprising a substrate 1 having an insulating surface, a channel layer disposed on a partial region on the substrate 1 and formed of a semiconductor material, a source region 2S and a drain region 2D respectively disposed on regions of both sides of the channel layer on the substrate 1 and electrically connected to the channel layer, a gate insulating film 3 formed on the channel layer and gate electrodes 4 formed on the film 3 and including a low resistance part 4b and a high resistance part 4a having higher resistivity than the part 4b, the part 4a has the electrodes 4 respectively disposed on a region between the part 4b and the region 2S and a region between the part 4b and the region 2D.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor and its manufacturing method.

[0002]

2. Description of the Related Art In an active matrix type liquid crystal display device using a thin film transistor (TFT), it is possible to electrically separate a pixel electrode and a signal line which are not being scanned, so that crosstalk can be easily eliminated. it can. Further, it is possible to dispose a driving circuit composed of TFTs around the display area. Therefore, it is possible to provide a high-resolution and high-definition liquid crystal display panel having a built-in drive circuit.

Since the carrier mobility of polysilicon is higher than that of amorphous silicon, a TFT using polysilicon is suitable for high speed operation. However, the current (off-current) during non-conduction is larger than that of the TFT using amorphous silicon.

When a negative bias is applied to the gate electrode of the n-channel TFT, a p-type inversion layer is formed in the channel region just below the gate electrode. A large electric field is generated at the pn junction between the p type inversion layer and the n ⁺ type source / drain region. Due to this electric field, a current flows through the defect in the pn junction, so that the off current increases.

Referring to FIG. 5, the structure and operation of a conventional TFT for suppressing an increase in off current will be described.

FIG. 5A is a cross-sectional view showing the vicinity of the boundary between the source region and the channel region of the conventional TFT. The polysilicon film 101 is formed on the surface of the glass substrate 100,
A gate insulating film 102 is formed on the surface of the polysilicon film 101 so as to cover a region of about 2/3 on the right side of the drawing. A gate electrode 103 is formed on the surface of the gate insulating film 102 so as to cover a region of about 1/3 on the right side of the drawing.

The polysilicon film 101 is the gate insulating film 1
02 is divided into a source region 105 not covered with 02, a boundary region 104 covered with the gate insulating film 102 and not covered with the gate electrode 103, and a controlled region 106 covered with the gate electrode 103. The controlled region 106 and the boundary region 104 form a channel region. Source area 105
Is an n ⁺ type, the boundary region 104 is undoped or n ⁻ type,
The controlled region 106 is non-doped.

FIGS. 5B and 5C show carrier concentration distributions when the boundary region 104 is n ⁻ type and non-doped, respectively. The horizontal axis represents the in-plane position of the polysilicon film 101, and the vertical axis represents the carrier concentration on an arbitrary scale. When a negative bias is applied to the gate electrode 103, the controlled region 10
6 becomes p-type. Controlled area 106 and source area 105
N ^- type or undoped boundary region 104 between
Is provided, the electric field strength generated in this portion is weakened. The weakening of the electric field strength can suppress an increase in off current.

[0009]

As shown in FIG. 5B, when the low concentration region 104 is formed between the source region 105 and the controlled region 106, the gate shown in FIG. Impurity ions such as phosphorus are implanted into the polysilicon film 101 through the insulating film 102. Therefore, the low concentration region 1
The impurity concentration of 04 depends on the thickness of the gate insulating film 102. If the thickness of the gate insulating film 102 deviates from a desired value, it becomes difficult to set the impurity concentration of the low concentration region 104 to a desired concentration.

As shown in FIG. 5C, the source region 10
5 and the controlled region 106 between the undoped region 104
Although the increase of the off-current can be suppressed by providing, the high-resistance region 104 is inserted in series between the source region 105 and the controlled region 106, so that the current at the time of conduction (on-current) is also increased. Will decrease.

An object of the present invention is to provide a thin film transistor capable of suppressing an increase in off-current without significantly decreasing the on-current and a method for manufacturing the same.

[0012]

According to one aspect of the present invention, a substrate having an insulative surface, a channel layer disposed in a partial region of the substrate and formed of a semiconductor material, and the substrate A source region and a drain region that are respectively disposed in regions on both sides of the channel layer and are electrically connected to the channel layer, a gate insulating film formed on the channel layer, and the gate insulating layer. A gate electrode formed on a film, the gate electrode including a low resistance portion and a high resistance portion having a resistivity higher than that of the low resistance portion, the high resistance portion being the low resistance portion. There is provided a thin film transistor having a region between the drain region and the source region and a region between the low resistance region and the drain region.

When a bias is applied to the gate electrode so that the channel becomes non-conductive, an inversion layer is formed in the region of the channel layer immediately below the low resistance portion. In addition, a leak current flows between the low resistance portion and the source region and the drain region through the high resistance portion and the gate insulating film. This leak current causes a voltage drop in the high resistance portion. For this reason,
In the channel layer immediately below the high resistance portion, the inversion strength becomes weaker as it approaches the source region and the drain region from the region directly below the low resistance portion. That is, the carrier concentration decreases.

Since a region having a low carrier concentration is inserted in series between the source region and the drain region and the channel, the electric field strength generated in this region is suppressed. The off current that increases when a strong electric field is generated can be suppressed.

According to another aspect of the present invention, a step of forming a semiconductor thin film on a partial region of the substrate having an insulating surface and a gate insulating film on the surface of the semiconductor thin film. And a step of forming a gate electrode made of metal on a surface of the gate insulating film and in a portion in a region above the semiconductor thin film, and at least on a side surface of the surface layer of the gate electrode. There is provided a method of manufacturing a thin film transistor, which includes the steps of anodizing the surface layer to form an anodized film, and adding an impurity to the anodized film to impart conductivity.

The anodic oxide film containing impurities formed on the surface of the gate electrode constitutes the above-mentioned high resistance portion.

According to another aspect of the present invention, a step of forming a semiconductor thin film on a part of the insulating surface of a substrate having an insulating surface, and a gate insulating film on the surface of the semiconductor thin film. A step of forming a high resistance layer on the gate insulating film, a step of depositing a metal layer on the high resistance layer, and a region of the surface of the metal layer above the semiconductor thin film. A step of covering a part of the inside with a resist pattern, and etching the metal layer and the high resistance layer using the resist pattern as an etching mask to form a laminated structure of the high resistance layer and the metal layer in the region covered with the resist pattern. Leaving the gate electrode having, a step of forming a anodic oxide film by anodizing the side surface of the metal layer with the upper surface of the gate electrode covered with the resist pattern, the resist pattern and the Manufacturing method of a thin film transistor and a step of removing the electrode oxide film is provided.

When the anodic oxide film formed on the side surface of the metal layer is removed, a structure in which the end portions of the high resistance layer project on both sides of the metal layer can be obtained. This protruding portion constitutes the above-mentioned high resistance portion.

[0019]

BEST MODE FOR CARRYING OUT THE INVENTION With reference to FIGS. 1 and 2, a method of manufacturing a thin film transistor according to a first embodiment of the present invention, its structure and operation will be described.

FIG. 1A shows a schematic plan view of a thin film transistor. A polysilicon film 2 extending in the horizontal direction in the drawing is arranged on a glass substrate. A gate electrode 4 that intersects with the polysilicon film 2 is arranged at a substantially central portion in the length direction of the polysilicon film 2. One end of the gate electrode 4 is continuous with a gate line extending in the horizontal direction in the figure.
The gate electrode 4 and the gate line are composed of a low resistance portion 4b made of Al and an anodic oxide film 4a surrounding the side surface thereof.

FIGS. 1B to 1G are process drawings in the cross section indicated by the one-dot chain line A1-A1 in FIG.

In FIG. 1B, after depositing an amorphous silicon film having a thickness of about 40 to 50 nm on the entire surface of the glass substrate 1, laser annealing is performed to form polysilicon, and the polysilicon film is patterned to form polysilicon. The film 2 is formed. The deposition of the amorphous silicon film is
For example, monosilane (SiH ₄ ) is used as a source gas, H ₂ is used as a reducing gas, and plasma-enhanced chemical vapor deposition (PE-CVD) is performed at a growth temperature of about 250 ° C.
Laser annealing is performed, for example, with an energy density of 250 mJ / c
It is performed by irradiating a XeCl laser of m ² . The patterning of the polysilicon film is performed by dry etching using Cl ₂ gas, for example.

A gate insulating film 3 of SiO _{2 having} a thickness of about 120 nm is deposited on the entire surface of the substrate 1 so as to cover the polysilicon film 2. The gate insulating film 3 is deposited by, for example, SiH
PE-CVD using ₄ and N ₂ O.

An Al film having a thickness of about 350 nm is deposited on the gate insulating film 3 by sputtering. A resist pattern 5 having the same pattern as the gate electrode 4 intersecting the polysilicon film 2 of FIG. 1A is formed on the Al film. Using the resist pattern 5 as an etching mask, Al is dry-etched using Cl ₂ gas.
The film is patterned to leave the gate electrode 4 in the region covered with the resist pattern 5.

As shown in FIG. 1C, the exposed surface of the gate electrode 4 is anodized using the resist pattern 5 as a mask. The low resistance portion 4b made of Al remains inside the gate electrode 4, and the anodic oxide film 4a having a thickness of about 1 to 2 μm is formed on the side surface thereof. The anodization is performed in an aqueous solution containing oxalic acid as a component. After the anodization, the resist pattern 5 is removed.

As shown in FIG. 1D, the gate insulating film 3 is etched by using the gate electrode 4 as a mask, and the gate insulating film 3a is left just under the gate electrode 4. The etching of the gate insulating film 3 is performed by dry etching using a fluorine-based gas, for example. Partial surfaces of the polysilicon film 2 are exposed on both sides of the gate insulating film 3a.

As shown in FIG. 1E, P ^{+ is formed on the} entire surface of the substrate.
Ions are implanted and activation annealing is performed by laser irradiation. The implantation amount is such that the sheet resistance of the ion implantation region of the polysilicon film 2 is about 1 kΩ / □ or less. An n ⁺ type source region 2S and a drain region 2D are formed in portions of the polysilicon film 2 exposed on both sides of the gate insulating film 3a. P ⁺ ions are also implanted in the anodic oxide film 4a.

The conductivity is imparted by implanting P ⁺ ions into the Al anodic oxide film 4a. Thus, the low resistance portion 4b made of Al and the source region 2S thereof are formed.
Side and the drain electrode 2D side, the gate electrode 4 composed of the high resistance portion 4a is formed.

The anodic oxide film 4a implanted with P ⁺ ions was analyzed by X-ray photoelectron spectroscopy (XPS) to find that Al and P
It was confirmed that it was combined with. Also, the acceleration energy is 10 ke
When P ⁺ ions are implanted under the conditions of V and a dose amount of 5 × 10 ¹⁵ cm ⁻² , the concentrations of Al, P, O, and C on the outermost surface of the film are 26 at%, 4 at%, 51 at%, respectively. And 19 atomic%, and the concentrations of Al, P, and O at a depth of 10 nm from the outermost surface were 42 atomic%, 9 atomic%, and 49 atomic%, respectively. C contained in the outermost surface of the film
Is likely from the atmosphere.

As shown in FIG. 1F, an interlayer insulating film 6 is deposited on the entire surface of the substrate in which a SiO ₂ film having a thickness of about 30 nm and a SiN film having a thickness of about 270 nm are laminated in this order. Si
The deposition of the O ₂ film is performed, for example, by using SiH ₄ and N ₂ as source gases.
PE-CVD is performed with O at a growth temperature of 300 ° C., and the SiN film is deposited by using, for example, Si as a source gas.
PE-using H ₄ and NH ₃ at a growth temperature of 300 ° C.
It is performed by CVD.

Contact holes 7S and 7D are formed in the interlayer insulating film 6 to expose the partial surfaces of the source region 2S and the drain region 2D. The SiN film is etched by, for example, dry etching using a fluorine-based gas, and the SiO ₂ film is etched by, for example, wet etching using buffered hydrofluoric acid in which NH ₄ F, HF, and H ₂ O are mixed. .

In FIG. 1G, a thickness of about 5 is formed on the entire surface of the substrate.
A Ti film having a thickness of 0 nm and an Al film having a thickness of about 300 nm are stacked in this order. This laminated structure is patterned to form a source leader line 8S connected to the source region 2S and a drain leader line 8D connected to the drain region 2D. Ti
The etching of the film and the Al film is performed by dry etching using a chlorine-based gas, for example.

Next, the operation of the thin film transistor according to the first embodiment will be described with reference to FIG.

FIG. 2A is a sectional view showing the vicinity of the boundary between the source region 2S and the gate electrode 4 of the thin film transistor according to the first embodiment. The same reference numerals as those of the corresponding components in FIG. 1G are given to the respective components. The polysilicon film 2 is divided into a controlled region 2C immediately below the low resistance portion 4b of the gate electrode 4, a boundary region 2B immediately below the high resistance portion 4a, and a source region 2S.

FIG. 2B shows a carrier concentration distribution in the polysilicon film 2 when a negative bias is applied to the gate electrode 4. The horizontal axis corresponds to the position of the polysilicon film 2 in the substrate surface, and the vertical axis represents the carrier concentration on an arbitrary scale.

The source region 2S is n ⁺ type and the controlled region 2C is p type. In FIG. 2A, a slight leak current flows from the source region 2S through the gate insulating film 3a and the high resistance portion 4a to the low resistance portion 4b. Due to the leakage current, a voltage drop occurs in the high resistance portion 4a from the end portion on the source region 2S side toward the end portion on the low resistance portion 4b side.

Due to the voltage drop, the hole concentration in the boundary region 2B gradually decreases from the controlled region 2C to the source region 2S. Since a region having a low carrier concentration is formed between the source region 2S and the controlled region 2C, the electric field strength generated at the pn junction can be weakened, and the increase in off current can be suppressed.

FIG. 2C shows a carrier concentration distribution in the polysilicon film 2 when a positive bias is applied to the gate electrode 4. Electrons are accumulated in the controlled region 2C and become n-type. As in the case of FIG. 2B, in the boundary region 2B, due to the voltage drop in the high resistance portion 4a, the controlled region 2C is formed.
The electron concentration gradually decreases as it approaches the source region 2S from the boundary with.

In the case of the conventional thin film transistor shown in FIG. 5C, since almost no carriers exist in the boundary region 104, the on-current decreases. On the other hand, in the case of FIG. 2C, the controlled area 2C in the boundary area 2B is
Carriers are present in the side portion, and the portion in which almost no carriers are present is limited to the short region on the source region 2S side. Therefore, it is possible to suppress the decrease of the on-current.

Further, it is not necessary to perform ion implantation into the boundary region 104 through the gate insulating film 102, which is necessary in the case of FIG. 5B. When ion implantation is performed through the gate insulating film, it is difficult to control the impurity addition amount with good reproducibility. The manufacturing yield of the thin film transistor according to the first embodiment can be increased.

Al or an Al alloy is used for the low resistance portion of the gate electrode, and an Al anodic oxide film (A
Although the case where l ₂ O ₃ ) is used has been described, other anodizable materials may be used as the gate electrode material. For example, Ta, Mo, or the like may be used as the gate electrode material. Conductivity can be imparted to these anodic oxide films by adding P.

In the first embodiment, the case where P is added to the anodic oxide film of Al to give conductivity is explained. However, other impurities capable of obtaining conductivity, such as As, are added. May be.

Next, a method of manufacturing a thin film transistor according to the second embodiment of the present invention will be described with reference to FIG.

As shown in FIG. 3A, the polysilicon film 2 and the gate insulating film 3 are formed on the glass substrate 1 by the same method as in the case of FIG. 1B. An amorphous silicon film 11a having a thickness of about 50 nm is deposited on the gate insulating film 3. Deposition of amorphous silicon film 11a is performed, for example SiH ₄ as source gases, by PE-CVD using and H ₂ as the reducing gas. A thickness of about 350 nm is formed on the amorphous silicon film 11a by sputtering.
Al film 11b is deposited.

As shown in FIG. 3B, the Al film 11b and the amorphous silicon film 11a are patterned,
An amorphous silicon film 4c is formed above the polysilicon film 2.
And the gate electrode 4 made of a laminate of the Al film 4d is left. The surface of the gate electrode 4 is anodized using an aqueous solution containing tartaric acid.

As shown in FIG. 3C, the gate insulating film 3 is etched using the gate electrode 4 as a mask in the same manner as in the case of FIG. Leave 3a.

As shown in FIG. 3D, P ⁺ ions are implanted into the polysilicon film 2 by the same method as in the case of FIG. 1E, and activation annealing is performed to form the source region 2S and the drain region. Form 2D. It should be noted that this activation annealing is preferably performed under the condition that the amorphous silicon is not crystallized.

In FIG. 3E, a positive resist film is applied on the entire surface of the substrate, and ultraviolet rays are irradiated from the back surface of the substrate.
The portion of the resist film immediately above the gate electrode 4 is not irradiated with ultraviolet light, and the other portion is irradiated with ultraviolet light. When the resist film is developed, the resist film 12 remains only on the gate electrode 4.

As shown in FIG. 3F, the resist film 12
Using the as a mask, the exposed side surface of the Al film 4d is anodized to form an anodized film 4e having a thickness of about 1 to 2 μm. This anodic oxidation is performed using, for example, an aqueous solution containing oxalic acid. When anodic oxidation is performed using oxalic acid, a film having a lower density is formed as compared with the anodic oxidation using tartaric acid performed in the step of FIG. 3B. After anodic oxidation, resist film 1
Remove 2.

The surface of the Al film 4d is previously covered with a thin anodic oxide film by anodic oxidation using tartaric acid performed in the step of FIG. 3B. According to the experiments conducted by the inventors of the present application, when anodization is not performed in the step of FIG. 3B, the depth of anodization from the side surface in the step of FIG. 3F can be stably controlled. It was difficult. FIG. 3 (B)
In the step, by anodizing the surface of the Al film 4d in advance, it becomes possible to uniformly form the anodized film on the side surface of the Al film 4d.

As shown in FIG. 3G, the anodic oxide film 4b is formed.
(FIG. 3F) is removed by etching. The surfaces near the edges of the amorphous silicon film 4c are exposed on both sides of the Al film 4d. The etching of the anodic oxide film is performed by wet etching using an aqueous solution containing chromic acid and phosphoric acid as main components.

As shown in FIG. 3H, as in the case of FIGS. 1F and 1G, the interlayer insulating film 6 and the source lead line 8 are formed.
The S and drain leader lines 8D are formed.

The amorphous silicon film 4c is an Al film 4d.
It has a higher resistivity than. Therefore, the Al film 4d acts in the same manner as the low resistance portion 4b of FIG. 1G, and the portions of the amorphous silicon film 4c that project to both sides of the Al film 4d have high resistance portions of FIG. It operates in the same manner as 4a. In the TFT shown in FIG. 3H, the amorphous silicon film 4 is formed between the Al film 4d and the gate insulating film 3a.
Although c is arranged, its thickness is sufficiently smaller than the projecting length of the part projecting on both sides of the Al film 4d, so there is no significant difference in operation as compared with the TFT of FIG.

In this way, by disposing the amorphous silicon film 4c protruding on both sides of the Al film 4d between the Al film 4d of the gate electrode 4 and the gate insulating film 3a,
The same effect as in the case of the first embodiment described with reference to FIG. 2 can be obtained.

FIG. 4 shows the T according to the first or second embodiment.
The top view of the 1 pixel part of the liquid crystal display panel using FT is shown. The plurality of signal lines 20 extending in the vertical direction and the plurality of control lines 21 extending in the horizontal direction in FIG. 4 form a lattice pattern. The signal line 20 and the control line 21 are insulated from each other by an interlayer insulating film at the intersection. Signal line 20
The TFT 22 according to the first or second embodiment is arranged at the intersection of the control line 21 and the control line 21.

The gate electrode 22G of the TFT 22 is continuous with the corresponding control line 21. The source region 22S is T
The transparent pixel electrode 23 formed on the interlayer insulating film covering the FT 22 is connected via a contact hole 24S. The drain region 22D is connected to the corresponding signal line 20 via a contact hole 24D formed in the interlayer insulating film.

T according to the first or second embodiment of the present invention
By using FT, off current can be reduced. Therefore, unselected pixels, that is, T
In the pixel electrode 23 of the pixel in which the FT is in the non-conduction state,
Leakage of the image signal applied to the corresponding signal line 20 can be suppressed.

The present invention has been described above with reference to the embodiments.
The present invention is not limited to these. For example, it will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.

[0059]

As described above, according to the present invention,
By disposing the high resistance body connected to the gate electrode on both sides of the gate electrode, it is possible to suppress an increase in the off current of the TFT.

[Brief description of drawings]

1A and 1B are a plan view of a TFT and a cross-sectional view of the TFT during a manufacturing process, for explaining a method of manufacturing a TFT according to a first embodiment of the present invention.

FIG. 2 is a partial sectional view of a TFT and a graph showing a carrier density distribution for explaining the operation of the TFT according to the first embodiment of the present invention.

FIG. 3 is a cross-sectional view of the TFT during a manufacturing process for explaining the method of manufacturing the TFT according to the second embodiment of the present invention.

FIG. 4 is a plan view of one pixel portion of a liquid crystal display panel.

FIG. 5 is a partial cross-sectional view of a TFT and a graph showing a carrier density distribution for explaining the operation of a conventional TFT.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Glass substrate 2 Polysilicon film 2S Source region 2D Drain region 2C Controlled region 2B Boundary region 3, 3a Gate insulating film 4 Gate electrode 4a Anodized film, high resistance part 4b Low resistance part 4c Amorphous silicon film 4d Al film 5 Resist Pattern 6 Interlayer insulating film 7S, 7D Contact hole 8S, 8D Lead line 12 Resist film 20 Signal line 21 Control line 22 TFT 22G Gate electrode 22S Source region 22D Drain region 23 Pixel electrode 24S, 24D Contact hole 100 Glass substrate 101 Polysilicon film 102 gate insulating film 103 gate electrode 104 boundary region 105 source region 106 controlled region

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Tomotaka Matsumoto 4-1-1 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Within Fujitsu Limited (72) Inventor Tsutomu Tanaka 4-chome, Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa No. 1 within Fujitsu Limited

Claims (5)

[Claims] 1. A substrate having an insulating surface, a channel layer formed of a semiconductor material, which is disposed in a partial region of the substrate, and in a region of the substrate on both sides of the channel layer. A source region and a drain region that are respectively arranged and electrically connected to the channel layer, a gate insulating film formed on the channel layer, and a gate electrode formed on the gate insulating film. The gate electrode is configured to include a low resistance portion and a high resistance portion having a resistivity higher than that of the low resistance portion, the high resistance portion being a region between the low resistance portion and the source region, and A thin film transistor having the gate electrode arranged in a region between the low resistance portion and the drain region. 2. The low resistance portion of the gate electrode is Al or Al alloy, and the high resistance portion is an anodic oxide film of Al or Al alloy to which conductivity is added by adding impurities. The thin film transistor described. 3. The gate electrode has another high resistance portion disposed between the low resistance portion and the gate insulating film,
The thin film transistor according to claim 1, wherein the high resistance portion and the other high resistance portion form one layer made of the same material. 4. A step of forming a semiconductor thin film on a partial region of the substrate having an insulating surface on the insulating surface; a step of forming a gate insulating film on the surface of the semiconductor thin film; Forming a gate electrode made of a metal on a part of the surface of the film and above the semiconductor thin film; and anodizing at least a side surface layer of the surface layer of the gate electrode. A method of manufacturing a thin film transistor, comprising: a step of forming an anodized film; and a step of adding impurities to the anodized film to impart conductivity. 5. A step of forming a semiconductor thin film on a partial region of the substrate having an insulating surface on the insulating surface; a step of forming a gate insulating film on the surface of the semiconductor thin film; A step of forming a high resistance layer on the film; a step of depositing a metal layer on the high resistance layer; and a part of the surface of the metal layer in a region above the semiconductor thin film as a resist pattern. And a step of covering the metal layer, the high resistance layer, and the gate insulating film using the resist pattern as an etching mask,
A step of leaving a gate electrode having a laminated structure of a high resistance layer and a metal layer in a region covered with a resist pattern, and leaving a gate insulating film directly under the gate electrode; A method of manufacturing a thin film transistor, comprising: a step of forming a anodic oxide film by anodizing the side surface of the metal layer in a state of being covered with a step of removing the resist pattern and the anodic oxide film.