JPH09330894A - Grinding of device surface of semiconductor wafer - Google Patents

Grinding of device surface of semiconductor wafer

Info

Publication number
JPH09330894A
JPH09330894A JP14586496A JP14586496A JPH09330894A JP H09330894 A JPH09330894 A JP H09330894A JP 14586496 A JP14586496 A JP 14586496A JP 14586496 A JP14586496 A JP 14586496A JP H09330894 A JPH09330894 A JP H09330894A
Authority
JP
Japan
Prior art keywords
polishing
semiconductor wafer
grinding
device surface
cloth
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14586496A
Other languages
Japanese (ja)
Inventor
Takao Inaba
高男 稲葉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tokyo Seimitsu Co Ltd
Original Assignee
Tokyo Seimitsu Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Seimitsu Co Ltd filed Critical Tokyo Seimitsu Co Ltd
Priority to JP14586496A priority Critical patent/JPH09330894A/en
Publication of JPH09330894A publication Critical patent/JPH09330894A/en
Pending legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To provide a grinding method for flattening a device surface of a semiconductor wafer with high accuracy. SOLUTION: A grinding liquid is supplied between a semiconductor wafer 20 and a grinding cloth 12 so as to press both of them on each other to allow them to perform relative movement for grinding the device surface 20A. Immediately before reaching a target grinding amount, the semiconductor wafer 20 and the grinding cloth 12 are separated so as to grind the device surface 20A only with this grinding liquid while stirring the grinding liquid by the relative movement between the semiconductor wafer 20 and the grinding cloth 12. By this grinding, scratches caused on the device surface 20 at the time of grinding by imposing grinding pressure can be erased. Since the grinding amount can be controlled with high accuracy, excessive grinding can be prevented.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、半導体ウェーハの
研磨方法に係わり、特に化学的機械研磨法 (CMP:Che
mical Mechanical Polishing) による半導体ウェーハの
デバイス面の研磨方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for polishing a semiconductor wafer, and more particularly to a chemical mechanical polishing method (CMP: Che).
The present invention relates to a method for polishing a device surface of a semiconductor wafer by means of mical mechanical polishing.

【0002】[0002]

【従来の技術】近年、半導体デバイスの高密度化、多層
化が進み、その製作過程において半導体ウェーハのデバ
イス面を高い精度で平坦化する技術が重要視されてい
る。従来、そのための方法の一つとしてCMP法が用い
られている。このCMP法は、半導体ウェーハと研磨布
との間に研磨液を供給し、半導体ウェーハと研磨布とを
押し付けながら相対運動させる研磨方法である。この方
法では、研磨液の作用で半導体ウェーハ表面に生成した
軟質の皮膜が、研磨液や研磨布によって拭い取られるよ
うにして研磨が進む。このCMP法によれば、加工変質
層のほとんど無い、高精度の研磨を行うことができる。
2. Description of the Related Art In recent years, semiconductor devices have been highly densified and multilayered, and a technique for flattening a device surface of a semiconductor wafer with high accuracy is emphasized in the manufacturing process thereof. Conventionally, a CMP method has been used as one of the methods for that. The CMP method is a polishing method in which a polishing liquid is supplied between a semiconductor wafer and a polishing cloth, and the semiconductor wafer and the polishing cloth are relatively moved while being pressed against each other. In this method, polishing progresses so that the soft film formed on the surface of the semiconductor wafer by the action of the polishing liquid is wiped off by the polishing liquid or the polishing cloth. According to this CMP method, highly accurate polishing can be performed with almost no work-affected layer.

【0003】[0003]

【発明が解決しようとする課題】しかしながら、従来の
CMP法では、半導体ウェーハと研磨布とを単に押し付
けながら研磨を行うので、研磨屑等が擦り付けられるこ
とによって半導体ウェーハの表面に傷が生じやすい。ま
た、過剰な研磨が起こりやすく、そのために半導体ウェ
ーハの平坦度が悪くなるという欠点がある。
However, in the conventional CMP method, since the semiconductor wafer and the polishing cloth are simply pressed against each other for polishing, the surface of the semiconductor wafer is apt to be scratched due to the rubbing of polishing dust or the like. In addition, there is a drawback that excessive polishing is likely to occur, which results in poor flatness of the semiconductor wafer.

【0004】本発明はこのような事情に鑑みてなされた
もので、半導体ウェーハのデバイス面を、表面に傷を残
すことなく、高い精度で平坦化するための研磨方法を提
供することを目的とする。
The present invention has been made in view of the above circumstances, and an object thereof is to provide a polishing method for flattening the device surface of a semiconductor wafer with high accuracy without leaving scratches on the surface. To do.

【0005】[0005]

【課題を解決する為の手段】前記目的を達成するため
に、本発明は、半導体ウェーハと研磨布との間に研磨液
を供給するとともに、半導体ウェーハと研磨布とを押し
付けながら相対運動させて、半導体ウェーハのデバイス
面を研磨する半導体ウェーハのデバイス面の研磨方法に
おいて、研磨終了の直前に、前記半導体ウェーハと前記
研磨布とを離間させ、半導体ウェーハと研磨布との相対
運動によって前記研磨液を攪拌させながら、この研磨液
のみで半導体ウェーハのデバイス面を研磨する工程を設
けたことを特徴とする。
In order to achieve the above-mentioned object, the present invention provides a polishing liquid between a semiconductor wafer and a polishing cloth, and relatively moves the semiconductor wafer and the polishing cloth while pressing them. In the method for polishing the device surface of a semiconductor wafer, which polishes the device surface of a semiconductor wafer, immediately before the end of polishing, the semiconductor wafer and the polishing cloth are separated from each other, and the polishing liquid is caused by relative motion between the semiconductor wafer and the polishing cloth. The method is characterized in that a step of polishing the device surface of the semiconductor wafer with only this polishing liquid is provided while stirring.

【0006】本発明によれば、まず、半導体ウェーハと
研磨布との間に研磨液を供給し、半導体ウェーハと研磨
布とを押し付けながら相対運動させて、半導体ウェーハ
のデバイス面を研磨する。次いで、研磨量が目標値に達
する直前に、前記半導体ウェーハと前記研磨布とを離間
させ、半導体ウェーハと研磨布との相対運動によって前
記研磨液を攪拌させながら、この研磨液のみで半導体ウ
ェーハのデバイス面を研磨する。
According to the present invention, first, a polishing liquid is supplied between the semiconductor wafer and the polishing cloth, and the semiconductor wafer and the polishing cloth are pressed against each other to move relatively to polish the device surface of the semiconductor wafer. Then, immediately before the polishing amount reaches a target value, the semiconductor wafer and the polishing cloth are separated from each other, and the polishing solution is agitated by the relative motion of the semiconductor wafer and the polishing cloth, while the semiconductor wafer is polished only by this polishing solution. Polish the device surface.

【0007】このようにすれば、半導体ウェーハと研磨
布とを押し付けながら研磨を行った際に半導体ウェーハ
のデバイス面に生じた傷を、消すことができる。また、
研磨量を高精度に制御できるので、過剰な研磨を防ぐこ
とができ、半導体ウェーハのデバイス面を高い精度で平
坦化できる。
By doing so, it is possible to eliminate the scratches that have occurred on the device surface of the semiconductor wafer when polishing is performed while pressing the semiconductor wafer and the polishing cloth against each other. Also,
Since the polishing amount can be controlled with high precision, excessive polishing can be prevented, and the device surface of the semiconductor wafer can be planarized with high precision.

【0008】[0008]

【発明の実施の形態】以下添付図面に従って、本発明に
係わる半導体ウェーハのデバイス面の研磨方法の好まし
い実施の形態について詳説する。本発明の実施の形態の
研磨方法を適用したCMP装置10の要部構造を、図1
に示す。このCMP装置10は、主として、研磨布回転
機構、ウェーハ支持機構及び制御機構から構成されてい
る。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A preferred embodiment of a method for polishing a device surface of a semiconductor wafer according to the present invention will be described below in detail with reference to the accompanying drawings. FIG. 1 shows a main structure of a CMP apparatus 10 to which the polishing method according to the embodiment of the present invention is applied.
Shown in The CMP apparatus 10 mainly includes a polishing cloth rotating mechanism, a wafer supporting mechanism, and a control mechanism.

【0009】まず、研磨布回転機構について述べる。こ
の機構は、研磨布12を支持、回転するためのもので、
定盤11及びこれを回転させるモータ14等から構成さ
れている。研磨布12は前記定盤11の上面に貼られて
いて、この定盤11の下部中央には前記モータ14の回
転軸16が固着されている。したがって、モータ14が
回転駆動されると、研磨布12は図中矢印で示す方向に
所定の速度で回転する。
First, the polishing cloth rotating mechanism will be described. This mechanism is for supporting and rotating the polishing cloth 12,
It is composed of a surface plate 11 and a motor 14 for rotating the surface plate. The polishing cloth 12 is attached to the upper surface of the surface plate 11, and the rotary shaft 16 of the motor 14 is fixed to the lower center of the surface plate 11. Therefore, when the motor 14 is rotationally driven, the polishing pad 12 rotates at a predetermined speed in the direction indicated by the arrow in the figure.

【0010】次に、ウェーハ支持機構について述べる。
この機構は、半導体ウェーハ20を保持、回転、移動、
加圧するためのもので、吸着パッド22とこれを回転さ
せるモータ24、さらにそれら全体を図中上下方向に移
動させるシリンダ26等から構成されている。前記吸着
パッド22の下面には、半導体ウェーハ20が研磨を受
けるデバイス面20Aを下に向けて吸着保持される。こ
の吸着パッド22は上部中央に回転軸28が固着されて
おり、この回転軸28はギヤ30、32を介して、ベー
ス34に取り付けられた前記モータ24のスピンドルに
連結されている。したがって、モータ24が回転駆動さ
れると、その動力が吸着パッド22に伝達されて、半導
体ウェーハ20は図中矢印で示す方向に所定の速度で回
転する。
Next, the wafer support mechanism will be described.
This mechanism holds, rotates, moves, and holds the semiconductor wafer 20.
It is for applying pressure, and is composed of a suction pad 22, a motor 24 for rotating the suction pad 22, and a cylinder 26 for moving the suction pad 22 in the vertical direction in the figure. The lower surface of the suction pad 22 is suction-held with the device surface 20A of the semiconductor wafer 20 to be polished facing downward. A rotary shaft 28 is fixed to the center of the upper part of the suction pad 22, and the rotary shaft 28 is connected to a spindle of the motor 24 mounted on a base 34 via gears 30 and 32. Therefore, when the motor 24 is rotationally driven, its power is transmitted to the suction pad 22, and the semiconductor wafer 20 rotates at a predetermined speed in the direction indicated by the arrow in the figure.

【0011】また、前記回転軸28はベース34に軸支
されており、このベース34は、コラム35に設置され
たガイド36によって、図示しない直動式ベアリングを
介して上下動自在に支持されている。さらに、回転軸2
8には、その上部に前記シリンダ26のロッド38が、
図示しないカップリングと後述するアクチュエイタ40
とロードセル42とを介して固着されている。そして、
シリンダ26は、アーム39を介してコラム35に取り
付けられている。したがって、シリンダ26によってロ
ッド38が伸縮すると、回転軸28が上下に移動し、半
導体ウェーハ20は上下に移動する。
The rotary shaft 28 is pivotally supported by a base 34, and the base 34 is supported by a guide 36 installed on a column 35 so as to be vertically movable via a direct acting bearing (not shown). There is. Furthermore, the rotating shaft 2
8, the rod 38 of the cylinder 26 is provided on the upper part thereof.
A coupling not shown and an actuator 40 described later
And the load cell 42. And
The cylinder 26 is attached to the column 35 via an arm 39. Therefore, when the rod 38 expands and contracts by the cylinder 26, the rotating shaft 28 moves up and down, and the semiconductor wafer 20 moves up and down.

【0012】さらに、半導体ウェーハ20を上下に微動
させるために、後述の制御部50によって制御される前
記アクチュエイタ40が設けられている。このアクチュ
エイタ40は、圧電素子が用いられていて、制御部50
から印加される電圧に応じてその長さを上下方向にわず
かに変化させる。したがって、その作用によって回転軸
28が上下に微動され、半導体ウェーハ20は上下に微
動される。
Further, in order to finely move the semiconductor wafer 20 up and down, the actuator 40 controlled by a controller 50 described later is provided. This actuator 40 uses a piezoelectric element and has a control unit 50.
The length is slightly changed in the vertical direction according to the voltage applied from the. Therefore, the rotation shaft 28 is finely moved vertically by the action, and the semiconductor wafer 20 is finely moved vertically.

【0013】なお、半導体ウェーハ20が移動する際に
は、半導体ウェーハ20、回転軸28及びベース34は
常に一体的に移動し、半導体ウェーハ20とベース34
との相対位置は変化しない。次に、制御機構について述
べる。この機構は、半導体ウェーハ20と研磨布12と
の押し付け力(研磨圧力)、及び半導体ウェーハ20と
研磨布12との間の距離を検出し、その情報に基づいて
研磨布回転機構及びウェーハ支持機構を制御するための
ものである。そして、この機構は前記ロードセル42、
容量センサ44及び制御部50等から構成されている。
ロードセル42は制御部50に接続されていて、制御部
50は、このロードセル42が受ける圧力に応じてロー
ドセル42の内部の圧電素子に生ずる起電力を測定する
ことで、研磨圧力を検出している。
When the semiconductor wafer 20 moves, the semiconductor wafer 20, the rotary shaft 28 and the base 34 always move integrally, and the semiconductor wafer 20 and the base 34 move.
The relative position with does not change. Next, the control mechanism will be described. This mechanism detects a pressing force (polishing pressure) between the semiconductor wafer 20 and the polishing cloth 12 and a distance between the semiconductor wafer 20 and the polishing cloth 12, and based on the information, a polishing cloth rotating mechanism and a wafer supporting mechanism. Is for controlling. And, this mechanism is the load cell 42,
It is composed of a capacitance sensor 44, a control unit 50, and the like.
The load cell 42 is connected to the control unit 50, and the control unit 50 detects the polishing pressure by measuring the electromotive force generated in the piezoelectric element inside the load cell 42 according to the pressure received by the load cell 42. .

【0014】また、前記容量センサ44は、半導体ウェ
ーハ20の位置を検出するために設けられている。前述
のように、半導体ウェーハ20とベース34との相対位
置は常に変化しないので、ベース34の位置を検知すれ
ば半導体ウェーハ20の位置を知ることができる。容量
センサ44は、このベース34の位置を検知するために
ベース34に対向する位置に取り付けられていて、制御
部50に接続されている。この容量センサ44は、その
上部に設けられた電極板46Aと、それに対向する位置
にベース34に設けられた電極板46Bとでコンデンサ
を形成している。制御部50は、このコンデンサの静電
容量を測定することで、容量センサ44とベース34と
の距離を検知し、半導体ウェーハ20の位置を検出して
いる。
The capacitance sensor 44 is provided to detect the position of the semiconductor wafer 20. As described above, the relative position between the semiconductor wafer 20 and the base 34 does not always change, so that the position of the semiconductor wafer 20 can be known by detecting the position of the base 34. The capacitance sensor 44 is attached to a position facing the base 34 in order to detect the position of the base 34, and is connected to the control unit 50. The capacitance sensor 44 has a capacitor formed by an electrode plate 46A provided on the upper part thereof and an electrode plate 46B provided on the base 34 at a position facing the electrode plate 46A. The control unit 50 detects the position of the semiconductor wafer 20 by detecting the distance between the capacitance sensor 44 and the base 34 by measuring the electrostatic capacitance of this capacitor.

【0015】そして、制御部50は、上記のようにして
得た、研磨圧力及び半導体ウェーハ20の位置の情報に
基づいて、シリンダ26とアクチュエイタ40とをフィ
ードバック制御して、研磨圧力や半導体ウェーハ20の
位置を制御している。さらに、制御部50は、モータ1
4及びモータ24の回転速度を制御することで、研磨時
の半導体ウェーハ20と研磨布12との相対運動の速度
を制御している。
Then, the control unit 50 feedback-controls the cylinder 26 and the actuator 40 based on the information on the polishing pressure and the position of the semiconductor wafer 20 obtained as described above, and the polishing pressure and the semiconductor wafer are controlled. It controls 20 positions. Further, the control unit 50 controls the motor 1
4 and the rotation speed of the motor 24 are controlled to control the speed of relative movement between the semiconductor wafer 20 and the polishing cloth 12 during polishing.

【0016】ここで、以上のように構成されたCMP装
置10による、半導体ウェーハ20のデバイス面20A
の研磨方法について説明する。本実施の形態の研磨方法
は、研磨終了まで研磨圧力をかけ続けて研磨を行うので
はなく、研磨終了直前に半導体ウェーハ20と研磨布1
2との間に隙間を開けて、半導体ウェーハ20と研磨布
12との相対運動によって研磨液を攪拌させながら、こ
の研磨液のみの作用でデバイス面20Aの研磨を行う工
程があることが特徴である。
Here, the device surface 20A of the semiconductor wafer 20 by the CMP apparatus 10 configured as described above.
Will be described. In the polishing method of the present embodiment, the semiconductor wafer 20 and the polishing cloth 1 are not immediately polished until the polishing is completed, instead of continuously applying the polishing pressure.
2 is characterized in that there is a step of opening a gap between the semiconductor wafer 20 and the polishing cloth 12 and stirring the polishing liquid by the relative movement of the semiconductor wafer 20 and the polishing pad 12, and polishing the device surface 20A only by the action of this polishing liquid. is there.

【0017】まず、半導体ウェーハ20を、研磨を受け
るデバイス面20Aを下にして吸着パッド22に取り付
ける。そして、シリンダ26を動作させて半導体ウェー
ハ20を研磨布12に押し付けながら、吸着パッド22
と研磨布12とを回転させて、デバイス面20Aを研磨
する。なお、このとき必要に応じて、研磨圧力を変化さ
せながら研磨を行ってもよい。その際には、シリンダ2
6だけでなくアクチュエイタ40も動作させれば、研磨
圧力を精密に制御できる。
First, the semiconductor wafer 20 is attached to the suction pad 22 with the device surface 20A to be polished facing down. Then, while the cylinder 26 is operated to press the semiconductor wafer 20 against the polishing cloth 12, the suction pad 22
The polishing pad 12 is rotated to polish the device surface 20A. At this time, polishing may be performed while changing the polishing pressure, if necessary. In that case, cylinder 2
By operating not only the actuator 6 but also the actuator 40, the polishing pressure can be precisely controlled.

【0018】また、研磨中には、半導体ウェーハ20と
研磨布12との間に、パイプ48から図示しない研磨液
を供給する。研磨液としては、通常、アルカリ性の溶液
に砥粒をコロイド状に分散させたものを用いるが、それ
に限定することなく、研磨の対象物に応じて適当な研磨
液を選べばよい。そして、研磨量が目標値に近くなった
ら、シリンダ26の動作を停止させて研磨圧力を0にす
る。次いで、アクチュエイタ40を動作させて、半導体
ウェーハ20の位置を適当な距離、例えば10μmだけ
上昇させ、半導体ウェーハ20と研磨布12との間に隙
間を開ける。この状態で吸着パッド22と研磨布12と
を回転させると、デバイス面20Aには攪拌された研磨
液のみが接触して、わずかずつの研磨が行われる。
During polishing, a polishing liquid (not shown) is supplied from the pipe 48 between the semiconductor wafer 20 and the polishing cloth 12. As the polishing liquid, generally, an alkaline solution in which abrasive grains are dispersed in a colloidal form is used, but the polishing liquid is not limited thereto, and an appropriate polishing liquid may be selected according to the object to be polished. Then, when the polishing amount approaches the target value, the operation of the cylinder 26 is stopped and the polishing pressure is set to zero. Next, the actuator 40 is operated to raise the position of the semiconductor wafer 20 by an appropriate distance, for example, 10 μm, and a gap is opened between the semiconductor wafer 20 and the polishing cloth 12. When the suction pad 22 and the polishing pad 12 are rotated in this state, only the agitated polishing liquid comes into contact with the device surface 20A, and polishing is performed little by little.

【0019】なお、研磨量を検出するには、研磨中の半
導体ウェーハ20の厚みの変化を、容量センサ44によ
って検知すればよい。また、研磨圧力及び研磨時間に対
する研磨量の依存性を実験によってあらかじめ求めてお
き、実際の研磨においては研磨圧力及び研磨時間を管理
することで研磨量を推定する方法でもよい。以上のよう
に、半導体ウェーハ20と研磨布12との間に隙間を開
けた状態で研磨を行えば、デバイス面20Aに研磨屑等
を擦り付けることがないので、研磨圧力をかけて研磨し
た際にデバイス面20Aに生じた傷を消すことができ
る。
To detect the polishing amount, the capacitance sensor 44 may detect a change in the thickness of the semiconductor wafer 20 during polishing. Alternatively, the dependency of the polishing amount on the polishing pressure and the polishing time may be obtained in advance by an experiment, and in the actual polishing, the polishing amount may be estimated by managing the polishing pressure and the polishing time. As described above, when polishing is performed with a gap between the semiconductor wafer 20 and the polishing cloth 12, polishing dust or the like is not rubbed against the device surface 20A. The scratch generated on the device surface 20A can be erased.

【0020】また、この状態での研磨は単位時間あたり
の研磨量が非常に少ないので、かえって高い精度で研磨
量を制御することができる。そのため、過剰な研磨を防
ぐことができ、デバイス面20Aを高度に平坦化するこ
とができる。その反面、研磨の始めからこの隙間を開け
た状態での研磨を行うのは、スループットを考えると得
策ではない。したがって、本実施の形態のように、従来
の研磨圧力をかけた研磨と組み合わせて実施するべきで
ある。
Further, since the polishing amount in this state is very small per unit time, the polishing amount can be controlled with high accuracy. Therefore, excessive polishing can be prevented, and the device surface 20A can be highly flattened. On the other hand, it is not a good idea to perform polishing with this gap left open from the beginning of polishing in view of throughput. Therefore, as in the present embodiment, it should be carried out in combination with the conventional polishing under a polishing pressure.

【0021】なお、これまで述べた研磨の途中で、半導
体ウェーハ20と研磨布12との相対運動の速度を変化
させてもよい。それによって、デバイス面20Aに接触
する研磨液の流速を変化させ、デバイス面20Aの研磨
量を制御することができる。さて、次に本実施の形態の
研磨方法について、図2の研磨圧力に対する研磨量及び
研磨時間の関係を示すグラフに基づいて説明する。この
グラフの縦軸は研磨圧力及び研磨量を示し、横軸は研磨
時間を示す。なお、研磨量を表したグラフの傾きは、単
位時間あたりの研磨量に相当する。
The speed of the relative movement between the semiconductor wafer 20 and the polishing pad 12 may be changed during the above-described polishing. Thereby, the flow rate of the polishing liquid contacting the device surface 20A can be changed and the polishing amount of the device surface 20A can be controlled. Now, the polishing method of the present embodiment will be described with reference to the graph of FIG. 2 showing the relationship between the polishing pressure and the polishing amount and the polishing time. The vertical axis of this graph shows the polishing pressure and the polishing amount, and the horizontal axis shows the polishing time. The slope of the graph showing the polishing amount corresponds to the polishing amount per unit time.

【0022】もし、従来の方法のように研磨圧力をかけ
たままで研磨を終了させようとすると、符号A’で示す
破線のグラフのように単位時間あたりの研磨量が多いま
まなので、研磨時間の管理によって研磨量を目標値に合
わせるのは困難である。符号Aで示すグラフは、研磨開
始時から時刻t1 までは一定の研磨圧力p1 で研磨を行
い、時刻t1 に研磨圧力を0にして半導体ウェーハ20
と研磨布12との間に隙間を開け、研磨量が目標値に達
する時刻tA まで研磨液のみの作用による研磨を行った
際のグラフである。グラフAを見ると、時刻0からt1
までに比べて、時刻t1 からtA まででは単位時間あた
りの研磨量が少なく、精密な研磨が行われていることが
分かる。このように単位時間あたりの研磨量が少なけれ
ば、研磨時間を管理することによる研磨量の制御が比較
的容易にできる。
If it is attempted to finish polishing with the polishing pressure applied as in the conventional method, the polishing amount per unit time remains large as indicated by the broken line graph A ', so that the polishing time It is difficult to adjust the polishing amount to the target value by management. The graph indicated by the sign A, from the polishing start to a time t 1 was ground with a constant polishing pressure p 1, the semiconductor wafer 20 by the polishing pressure at the time t 1 to 0
2 is a graph when a gap is opened between the polishing pad 12 and the polishing pad 12 and polishing is performed by the action of only the polishing liquid until time t A when the polishing amount reaches the target value. Looking at graph A, from time 0 to t 1
It can be seen that the amount of polishing per unit time is small and precise polishing is performed from time t 1 to time t A as compared with the above. As described above, if the polishing amount per unit time is small, the polishing amount can be controlled relatively easily by controlling the polishing time.

【0023】また、本実施の形態の研磨方法によれば、
研磨終了時の仕上げ精度が確保されているので、研磨の
前半での研磨圧力を従来よりも高く設定して、スループ
ットを向上させることが可能である。符号Bで示すグラ
フは、研磨開始時から時刻t2 までは前記p1 よりも高
い研磨圧力p2 をかけ、時刻t2 から研磨圧力を徐々に
小さくしていき、時刻t3 に研磨圧力を0にして半導体
ウェーハ20と研磨布12との間に隙間を開け、研磨液
のみの作用による研磨をするように制御した際のグラフ
である。この方法では時刻tB に研磨が終了しており、
グラフAの方法よりも研磨にかかる時間が短いことが分
かる。しかも、時刻tB 付近の研磨終了直前では、グラ
フの傾きはグラフAの場合と等しく、精密な研磨が行わ
れている。
Further, according to the polishing method of the present embodiment,
Since the finishing accuracy at the end of polishing is ensured, it is possible to set the polishing pressure in the first half of polishing higher than before and improve the throughput. The graph indicated by the symbol B is from the time of start of polishing to the time t 2 over a high polishing pressure p 2 than the p 1, gradually reducing the polishing pressure from the time t 2, the polishing pressure at time t 3 6 is a graph when a gap is opened between the semiconductor wafer 20 and the polishing cloth 12 by setting it to 0 and polishing is performed by the action of only the polishing liquid. In this method, polishing is completed at time t B ,
It can be seen that the time required for polishing is shorter than the method of graph A. Moreover, just before the end of polishing near time t B , the inclination of the graph is the same as in the case of graph A, and precise polishing is performed.

【0024】[0024]

【発明の効果】以上説明したように、本発明の半導体ウ
ェーハのデバイス面の研磨方法によれば、研磨終了直前
に半導体ウェーハと研磨布との間に隙間を開け、研磨液
のみの作用で研磨を行う工程を設けたので、半導体ウェ
ーハのデバイス面を、表面に傷を残すことなく、高い精
度で平坦化することができる。
As described above, according to the method for polishing the device surface of the semiconductor wafer of the present invention, a gap is opened between the semiconductor wafer and the polishing cloth immediately before the polishing is finished, and the polishing is performed only by the action of the polishing liquid. Since the step of carrying out is provided, the device surface of the semiconductor wafer can be planarized with high accuracy without leaving scratches on the surface.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の実施の形態の研磨方法を適用したCM
P装置の要部構造図。
FIG. 1 is a CM to which a polishing method according to an embodiment of the present invention is applied.
The principal part structural drawing of P apparatus.

【図2】研磨圧力に対する研磨量及び研磨時間の関係を
示す説明図。
FIG. 2 is an explanatory diagram showing a relationship between a polishing pressure and a polishing amount and a polishing time.

【符号の説明】[Explanation of symbols]

10…CMP装置 11…定盤 12…研磨布 20…半導体ウェーハ 22…吸着パッド 26…シリンダ 40…アクチュエイタ 42…ロードセル 44…容量センサ 50…制御部 10 ... CMP device 11 ... Surface plate 12 ... Polishing cloth 20 ... Semiconductor wafer 22 ... Adsorption pad 26 ... Cylinder 40 ... Actuator 42 ... Load cell 44 ... Capacity sensor 50 ... Control unit

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】半導体ウェーハと研磨布との間に研磨液を
供給するとともに、半導体ウェーハと研磨布とを押し付
けながら相対運動させて、半導体ウェーハのデバイス面
を研磨する半導体ウェーハのデバイス面の研磨方法にお
いて、 研磨終了の直前に、前記半導体ウェーハと前記研磨布と
を離間させ、半導体ウェーハと研磨布との相対運動によ
って前記研磨液を攪拌させながら、この研磨液のみで半
導体ウェーハのデバイス面を研磨する工程を設けたこと
を特徴とする半導体ウェーハのデバイス面の研磨方法。
1. Polishing a device surface of a semiconductor wafer, wherein a polishing liquid is supplied between the semiconductor wafer and the polishing cloth, and the semiconductor wafer and the polishing cloth are relatively moved while being pressed against each other to polish the device surface of the semiconductor wafer. In the method, immediately before the end of polishing, the semiconductor wafer and the polishing cloth are separated from each other, and while the polishing solution is stirred by the relative motion of the semiconductor wafer and the polishing cloth, the device surface of the semiconductor wafer is removed only by this polishing solution. A method for polishing a device surface of a semiconductor wafer, comprising a step of polishing.
JP14586496A 1996-06-07 1996-06-07 Grinding of device surface of semiconductor wafer Pending JPH09330894A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14586496A JPH09330894A (en) 1996-06-07 1996-06-07 Grinding of device surface of semiconductor wafer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14586496A JPH09330894A (en) 1996-06-07 1996-06-07 Grinding of device surface of semiconductor wafer

Publications (1)

Publication Number Publication Date
JPH09330894A true JPH09330894A (en) 1997-12-22

Family

ID=15394835

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14586496A Pending JPH09330894A (en) 1996-06-07 1996-06-07 Grinding of device surface of semiconductor wafer

Country Status (1)

Country Link
JP (1) JPH09330894A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004507098A (en) * 2000-08-22 2004-03-04 ラム リサーチ コーポレーション Polishing apparatus and method having high processing load for controlling polishing pressure provided by polishing head
JP2020011319A (en) * 2018-07-17 2020-01-23 秀和工業株式会社 Processing device and processing method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004507098A (en) * 2000-08-22 2004-03-04 ラム リサーチ コーポレーション Polishing apparatus and method having high processing load for controlling polishing pressure provided by polishing head
JP2020011319A (en) * 2018-07-17 2020-01-23 秀和工業株式会社 Processing device and processing method

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