JPH09283803A - Chip led and manufacture thereof - Google Patents
Chip led and manufacture thereofInfo
- Publication number
- JPH09283803A JPH09283803A JP8687396A JP8687396A JPH09283803A JP H09283803 A JPH09283803 A JP H09283803A JP 8687396 A JP8687396 A JP 8687396A JP 8687396 A JP8687396 A JP 8687396A JP H09283803 A JPH09283803 A JP H09283803A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- led
- support member
- ceramic
- led element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
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- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
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- H01L2924/01033—Arsenic [As]
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- H01L2924/01074—Tungsten [W]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
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- H—ELECTRICITY
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- H01L2924/01082—Lead [Pb]
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- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12041—LED
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明はＬＥＤ素子（ベアチッ
プ）をセラミックスパッケージに納めたチップタイプＬ
ＥＤに係り、特に、基板にフリップチップ実装したチッ
プタイプＬＥＤに関する。The present invention relates to a chip type L in which an LED element (bare chip) is housed in a ceramic package.
The present invention relates to EDs, and more particularly, to chip-type LEDs that are flip-chip mounted on a substrate.
【０００２】[0002]
【従来の技術】看板、広告塔等の平面型ディスプレイに
はＬＥＤが使用されている。現在量産化されているＬＥ
Ｄディスプレイに使用されているＬＥＤは、砲弾型リー
ドタイプＬＥＤと、基板に直接ＬＥＤ素子（ベアチッ
プ）を実装するダイレクトボンディングタイプの２種類
ある。砲弾型リードタイプＬＥＤを使用したものは、か
なりの高輝度化が実現できるため、屋外用途として主に
採用されている。しかし、ＬＥＤそのものが大きいた
め、小型サイズのディスプレイが作りにくい。一方、ダ
イレクトボンディングタイプは、ＬＥＤそのものが小さ
いため小型サイズのディスプレイは作りやすい。しか
し、基板に直接ＬＥＤ素子を実装するので、１つずつＬ
ＥＤの輝度を管理することが難しく、ディスプレイとし
ての明るさの均一性を保つのが困難とされている。2. Description of the Related Art LEDs are used in flat displays such as signboards and advertising towers. LE currently in mass production
There are two types of LEDs used in the D display: a cannonball lead type LED and a direct bonding type in which an LED element (bare chip) is directly mounted on a substrate. The one using the cannonball type lead type LED can realize a considerably high brightness, and is mainly used for outdoor use. However, since the LED itself is large, it is difficult to make a small size display. On the other hand, the direct bonding type is easy to make a small size display because the LED itself is small. However, LED elements are mounted directly on the board, so L
It is difficult to control the brightness of the ED, and it is difficult to maintain the uniformity of brightness as a display.
【０００３】これに対し、従来、図２に示すようなチッ
プタイプＬＥＤがあった。これは、導体層を形成した絶
縁性のセラミックス支持部材２１の上にＬＥＤ素子２３
を載置し、ＬＥＤ素子２３の電極２４と電極端子２２を
ワイヤーボンディングし、キャビティー内に封止樹脂２
６を満たして固化した構造である。このチップタイプＬ
ＥＤを１平面の上に表面実装することで高密度表示ＬＥ
Ｄディスプレイが実現できる。しかも、実装する前にＬ
ＥＤの輝度を確認できるので、ディスプレイとしての明
るさの均一性を損なう問題がない。On the other hand, conventionally, there is a chip type LED as shown in FIG. This is because the LED element 23 is formed on the insulating ceramics supporting member 21 on which a conductor layer is formed.
Is mounted, the electrode 24 of the LED element 23 and the electrode terminal 22 are wire-bonded, and the sealing resin 2 is placed in the cavity.
It is a structure that fills 6 and is solidified. This tip type L
High density display LE by surface mounting ED on one plane
D display can be realized. Moreover, before mounting
Since the brightness of the ED can be confirmed, there is no problem of impairing the uniformity of brightness as a display.
【０００４】ところが、このチップタイプＬＥＤは、Ｌ
ＥＤ素子２３からの発光をワイヤーが遮ることによる輝
度低下の問題がある。特に、ワイヤーに金線を使用した
場合、青色域に吸収があるため、輝度低下と発光色調変
化の問題があった。However, this chip type LED is
There is a problem in that the light emission from the ED element 23 is blocked by the wire and the brightness is reduced. In particular, when a gold wire is used as the wire, there is a problem of a decrease in luminance and a change in color tone of the emitted light because of absorption in the blue region.
【０００５】また、ワイヤーを保護するために、ＬＥＤ
素子２３とワイヤーを覆う隔壁でキャビティーを形成し
てやる必要がある。Also, in order to protect the wire, the LED
It is necessary to form a cavity with a partition wall that covers the element 23 and the wire.
【０００６】さらに、ＬＥＤ素子２３をキャビティー内
に固定するためには、キャビティー内に封止樹脂２６を
満たす構造をとることになり、これはＬＥＤ素子２３に
通電した時に発生する熱により封止樹脂が膨張し、ワイ
ヤー及びＬＥＤ素子２３の剥がれの原因になり、また、
ＬＥＤ素子からの発光の一部の紫外線により、封止樹脂
２６の劣化を引き起こし、樹脂の透過性が低下すること
によりチップタイプＬＥＤの輝度低下を引き起こす問題
がある。Further, in order to fix the LED element 23 in the cavity, a structure in which the sealing resin 26 is filled in the cavity is adopted, which is sealed by the heat generated when the LED element 23 is energized. The stop resin expands, causing the wire and the LED element 23 to peel off.
There is a problem that a part of ultraviolet rays emitted from the LED element causes deterioration of the encapsulating resin 26 and a decrease in transmissivity of the resin, which causes a decrease in brightness of the chip type LED.
【０００７】さらにまた、チップタイプＬＥＤの製法
上、基板の上にＬＥＤ素子を載置し、ワイヤーボンディ
ング、封止樹脂を注入した後に各セラミック支持部材
（パッケージ）単位に割り出すことで、チップタイプＬ
ＥＤを得ている。この割り出し時にセラミックス支持部
材２１に歪みが生じ、ＬＥＤ素子２３が脱落する不良が
生じる。Further, in the chip type LED manufacturing method, the LED element is mounted on the substrate, the wire bonding and the sealing resin are injected, and then indexed into each ceramic supporting member (package) unit to obtain the chip type L.
I'm getting an ED. At the time of this indexing, the ceramic support member 21 is distorted, and the LED element 23 falls off.
【０００８】[0008]
【発明が解決しようとする課題】従って、本発明はこの
ような事情に鑑みて成されたものであり、第一の目的
は、さらに高密度な表示が可能なＬＥＤディスプレイを
実現するチップタイプＬＥＤを提供すること。Therefore, the present invention has been made in view of such circumstances, and a first object thereof is a chip-type LED for realizing an LED display capable of higher density display. To provide.
【０００９】第２の目的は、ＬＥＤ素子からの発光をワ
イヤーにより遮断されない構造とすることで輝度を向上
することである。A second object is to improve brightness by adopting a structure in which light emitted from the LED element is not blocked by a wire.
【００１０】第３の目的は、ワイヤー保護のためのキャ
ビティーを必要としない構造とすることである。A third object is to provide a structure that does not require a cavity for wire protection.
【００１１】第４の目的はセラミックス支持部材単位に
割り出すときに歪みを生じることが原因で、ＬＥＤ素子
が脱落しない構造とすることである。A fourth object is to provide a structure in which the LED element does not fall off due to the occurrence of distortion when indexing to the ceramic support member unit.
【００１２】[0012]
【発明を解決するための手段】本発明者は上述した課題
に対し鋭意検討した結果、同一面側に一対の電極を有す
るＬＥＤ素子をセラミックスＬＥＤパッケージにフリッ
プチップ実装することで課題を解決することを見いだし
本発明を完成させるに至った。As a result of earnest studies on the above-mentioned problems, the present inventor has solved the problems by flip-chip mounting an LED element having a pair of electrodes on the same surface side in a ceramics LED package. They have found the present invention and completed the present invention.
【００１３】すなわち、本発明のチップタイプＬＥＤ
は、以下の各条件を備えることを特徴とする。 （ａ）同一面側に一対の電極を有するＬＥＤ素子と、Ｌ
ＥＤ素子を固定しているセラミックスの支持部材を備
え、（ｂ）セラミックス支持部材には互いに接近して固
定されている一対の電極端子を有し、（ｃ）ＬＥＤ素子
の電極は、セラミックスの支持部材の電極端子に導電性
ろう材を介してフリップチップ接続され、（ｄ）ＬＥＤ
素子が載置されている平面に対して垂直な方向にあるセ
ラミックス支持部材の外縁は、ＬＥＤ素子が実装されて
いるセラミックス基板を、ハーフカットラインに沿って
割り出すことにより形成されている。That is, the chip type LED of the present invention
Is characterized by having the following conditions. (A) An LED element having a pair of electrodes on the same side, and L
The ceramic support member fixing the ED element is provided, (b) the ceramic support member has a pair of electrode terminals fixed close to each other, and (c) the electrode of the LED element is a ceramic support member. Flip-chip connection to the electrode terminals of the member through a conductive brazing material, (d) LED
The outer edge of the ceramic support member in the direction perpendicular to the plane on which the element is placed is formed by indexing the ceramic substrate on which the LED element is mounted along the half cut line.
【００１４】特に、セラミックス基板上のハーフカット
ライン上に中心が位置するように補助孔が形成されてい
ることでさらに分割が容易になり、ハーフカットライン
の交差点に中心が位置するように補助孔が形成されてい
ることが最も好ましい。Particularly, since the auxiliary hole is formed so that the center is located on the half cut line on the ceramic substrate, the division is further facilitated, and the auxiliary hole is located so that the center is located at the intersection of the half cut lines. Is most preferably formed.
【００１５】また、本発明のチップタイプＬＥＤの製造
方法は、以下に示す各工程を備えることを特徴とする。 （ｐ）セラミックスグリーンシートに、チップタイプＬ
ＥＤとして割り出すことで形成される電極を作製するた
めの導体印刷を施す工程、（ｑ）導体印刷を施されたセ
ラミックスグリーンシートにチップタイプＬＥＤとして
割り出すためのハーフカットラインを作製する工程、
（ｒ）導体印刷とハーフカットラインを作製したグリー
ンシートを脱脂し、次に焼結する工程、（ｓ）焼結され
たセラミックス基板にＬＥＤ素子をフリップチップ接続
する工程、（ｔ）ＬＥＤ素子がフリップチップ接続され
たセラミックス基板をハーフカットラインに沿って割り
出す工程、The method of manufacturing a chip type LED according to the present invention is characterized by including the following steps. (P) Chip type L on the ceramic green sheet
A step of performing conductor printing for producing an electrode formed by indexing as ED, (q) a step of producing a half-cut line for indexing as a chip type LED on the ceramic green sheet on which the conductor is printed,
(R) The step of degreasing the green sheet on which the conductor printing and the half-cut line are produced and then sintering, (s) the step of flip-chip connecting the LED element to the sintered ceramics substrate, (t) the LED element The process of indexing the flip-chip connected ceramics substrate along the half-cut line,
【００１６】グリーンシートのハーフカットライン上に
中心が位置するように補助孔を形成することで、焼結さ
れたセラミックス基板の分割がさらに容易になり好まし
く、グリーンシートのハーフカットラインの交差点に中
心が位置するように補助孔を形成することが最も好まし
い。By forming the auxiliary hole so that the center is located on the half-cut line of the green sheet, it becomes easier to divide the sintered ceramics substrate, which is preferable. Most preferably, the auxiliary holes are formed so that
【００１７】[0017]
【発明の実施の形態】図１を参照して本発明のチップタ
イプＬＥＤを説明する。セラミックスの支持部材１１に
一対の電極端子１２が形成されており、ＬＥＤ素子１３
の表面の一対の電極１４は導電性のろう材１５によりフ
リップチップ接続されている。ＬＥＤ素子１３はセラミ
ックス支持部材と強固に接着させるためにＬＥＤ素子と
支持体の隙間に封止樹脂１６が注入されている。BEST MODE FOR CARRYING OUT THE INVENTION A chip type LED of the present invention will be described with reference to FIG. A pair of electrode terminals 12 is formed on a ceramic support member 11, and an LED element 13 is formed.
The pair of electrodes 14 on the surface of the is flip-chip connected by a conductive brazing material 15. The LED element 13 is filled with the sealing resin 16 in the gap between the LED element and the support in order to firmly bond the LED element 13 to the ceramic support member.
【００１８】請求項１の（ａ）に記載する、セラミック
スの支持部材とは、ＬＥＤ素子を載置して電気的に接続
できる構造であれば良く、セラミックスの材料にはアル
ミナ、窒化アルミニウム、ムライトが好ましく使用でき
る。支持部材としてセラミックスを選択することで絶縁
性があり、その上に印刷法等により導体配線を直接形成
することができる。The ceramic support member described in claim 1 (a) may be any structure that can mount and electrically connect the LED element, and the ceramic material is alumina, aluminum nitride, or mullite. Can be preferably used. By selecting ceramics as the supporting member, it has an insulating property, and the conductor wiring can be directly formed on it by a printing method or the like.
【００１９】請求項１の（ｂ）に記載する、接近して固
定されている一対の電極端子とは、図１に示すように、
ＬＥＤ素子１３を載置して導電性のろう剤１５で固定す
る場合に、電極端子１２が同一面側のＬＥＤ素子１３の
電極１４にショートすることなく給電できる程度接近し
ている状態である。The pair of electrode terminals that are closely fixed to each other as described in (b) of claim 1 are, as shown in FIG.
When the LED element 13 is placed and fixed with the conductive brazing agent 15, the electrode terminal 12 is close enough to the electrode 14 of the LED element 13 on the same surface side so that power can be supplied without short-circuiting.
【００２０】請求項１の（ｃ）に記載する、フリップチ
ップ接続とは、図１に示すようにセラミックス支持部材
１１の上に設けられた一対の電極端子にＬＥＤ素子１３
の一対の電極１４を向かい合わせて接続する方式であ
る。この方式により、ワイヤーボンディング接続により
発生していた諸問題を解消することができる。The flip-chip connection described in claim 1 (c) means that the LED element 13 is connected to a pair of electrode terminals provided on the ceramic support member 11 as shown in FIG.
This is a method in which the pair of electrodes 14 are connected to face each other. By this method, various problems caused by the wire bonding connection can be solved.
【００２１】請求項１の（ｄ）に記載する、ＬＥＤ素子
が載置されている平面に対して垂直な方向にあるセラミ
ックス支持部材の外縁とは、セラミックス支持部材を作
製する製造工程において、図３に示すセラミックス基板
３１に予めＬＥＤ素子３３を接続したものを図中の点線
のハーフカットライン３８に沿って割り出すことで得ら
れる。このハーフカットライン３８によりセラミックス
基板の割り出しは極めて容易に行うことができる。この
割り出しにより、図４に平面図を示すチップタイプＬＥ
Ｄを得る。この割り出し工程を経て作製された外縁４７
は、ハーフカットラインに沿って形成されているため割
れた跡が残るという特徴がある。The outer edge of the ceramic support member in the direction perpendicular to the plane on which the LED element is mounted is defined in the manufacturing process for manufacturing the ceramic support member. It is obtained by indexing the ceramic substrate 31 shown in FIG. 3 to which the LED element 33 is connected in advance along the dotted half-cut line 38 in the figure. The ceramic substrate can be extremely easily indexed by the half cut line 38. By this indexing, chip type LE whose plan view is shown in FIG.
Get D. The outer edge 47 produced through this indexing process
Is characterized in that it is formed along the half-cut line, so that cracks remain.
【００２２】請求項２に記載する、セラミックス基板の
ハーフカットライン上に中心が位置するように補助孔が
形成されていることで、割り出しは更に容易になる。Since the auxiliary hole is formed such that the center is located on the half-cut line of the ceramic substrate according to the second aspect, the indexing is further facilitated.
【００２３】請求項３に記載する、ハーフカットライン
の交差点に中心が位置するように補助孔が形成されてい
ることで、角の部分の不規則な割れを防止することがで
き、さらに容易にチップタイプＬＥＤに分割することが
できる。その結果、歪みがないため、ＬＥＤ素子の脱落
の不良が起こらない。図３はハーフカットラインの交差
点に補助孔の中心が位置するように正方形の補助孔３９
が形成された例である。Since the auxiliary hole is formed so that the center is located at the intersection of the half-cut lines described in claim 3, irregular cracks at corners can be prevented, and it is even easier. It can be divided into chip type LEDs. As a result, since there is no distortion, the LED element does not fall off. FIG. 3 shows a square auxiliary hole 39 so that the center of the auxiliary hole is located at the intersection of the half cut lines.
Is an example in which is formed.
【００２４】また、本発明のチップタイプＬＥＤの製造
方法について、以下に説明する。A method of manufacturing the chip type LED of the present invention will be described below.
【００２５】請求項４の（ｐ）に記載するセラミックス
グリーンシートとは、セラミックス基板を作製するのに
用いる、例えば、アルミナ等を主成分とし、これに有機
バインダー、溶剤、分散剤を加えてシート状にしたもの
である。これに、例えばタングステンを主成分とする導
体ペーストを印刷することで導体印刷ができる。The ceramic green sheet described in (p) of claim 4 is a sheet which is used for producing a ceramic substrate and contains, for example, alumina as a main component, to which an organic binder, a solvent and a dispersant are added. It is a shape. Conductor printing can be performed by printing a conductor paste containing tungsten as a main component, for example.
【００２６】請求項４の（ｑ）に記載するハーフカット
とは、図５の断面図を示すように、グリーンシートの厚
み方向に刃でプレスすることによりグリーンシートに割
溝を入れることである。すなわち完全に切り取るのでは
なく、一部を残してカットする。The half cut described in (q) of claim 4 is to form a split groove in the green sheet by pressing with a blade in the thickness direction of the green sheet as shown in the sectional view of FIG. . That is, instead of cutting it completely, a part of it is cut.
【００２７】請求項４の（ｒ）に記載したグリーンシー
トの脱脂は、グリーンシートのバインダー、溶剤を燃焼
分解して除去することであり、その後の焼結工程によ
り、セラミックスの粉は焼結してセラミックス基板を形
成する。又、導体印刷は導体配線を形成する。ここで、
セラミックス基板とは図３に示す導体配線を持ったＬＥ
Ｄを複数個実装できる基板のことを指し、セラミックス
支持部材とは、断面図を図１、平面図を図４に示すよう
に、セラミックス基板をこれをハーフカットラインに沿
って分割したことで得られる。また、図４のセラミック
ス支持部材１１の上にある電極端子は、セラミックス基
板の導体配線がこのハーフカットラインで分割すること
により形成される。The degreasing of the green sheet described in claim 4 (r) is to remove the binder and solvent of the green sheet by burning and decomposing, and the ceramic powder is sintered by the subsequent sintering step. To form a ceramic substrate. Also, conductor printing forms conductor wiring. here,
A ceramic substrate is an LE with conductor wiring shown in FIG.
A ceramic support member is obtained by dividing a ceramic substrate along a half-cut line as shown in a sectional view of FIG. 1 and a plan view of FIG. To be Further, the electrode terminals on the ceramics supporting member 11 of FIG. 4 are formed by dividing the conductor wiring of the ceramics substrate by the half cut lines.
【００２８】グリーンシートのハーフカットライン上に
中心が位置するように補助孔を形成することで、焼結さ
れたセラミックス基板の分割がさらに容易になり好まし
く、グリーンシートのハーフカットラインの交差点に中
心が位置するように補助孔を形成することが最も好まし
い。By forming the auxiliary hole so that the center is located on the half cut line of the green sheet, it becomes easier to divide the sintered ceramics substrate, which is preferable. Most preferably, the auxiliary holes are formed so that
【００２９】[0029]
【実施例】アルミナ粉末に溶剤、分散剤、バインダー、
および可塑剤を加えてスラリー状として、ドクターブレ
ード法により、該アルミナスラリーを流出させ、乾燥
し、グリーンシートを得た。[Example] Alumina powder with a solvent, a dispersant, a binder,
Then, a plasticizer was added to make a slurry, and the alumina slurry was flowed out by a doctor blade method and dried to obtain a green sheet.
【００３０】これに常法に従い、グリーンシートの両面
の導体印刷をつなぐ目的でスルーホールを開け、スクリ
ーン印刷法によりタングステンペーストを両面に印刷
し、図６に示す導体印刷６２を施したグリーンシートを
得た。In accordance with a conventional method, through holes are formed for the purpose of connecting conductor printing on both sides of the green sheet, and a tungsten paste is printed on both sides by screen printing to obtain a green sheet on which conductor printing 62 shown in FIG. 6 is applied. Obtained.
【００３１】次に、図７に示すように、プレス機を用い
て正方形の補助孔を貫通し、その後に補助孔に中心が位
置するように切断機を用い、ハーフカットラインを形成
した。Next, as shown in FIG. 7, a half cut line was formed by using a pressing machine to penetrate the square auxiliary hole and then using a cutting machine so that the center of the auxiliary hole was located.
【００３２】補助孔とハーフカット加工したグリーンシ
ートを常法に従い、乾燥、脱脂、焼結することで、タン
グステン導体配線が形成されたセラミックス基板を得
た。タングステン導体配線に貴金属メッキを施した。The auxiliary holes and the half-cut green sheet were dried, degreased and sintered according to a conventional method to obtain a ceramic substrate having a tungsten conductor wiring formed thereon. Noble metal plating was applied to the tungsten conductor wiring.
【００３３】図８に示すＬＥＤ素子１３は、下面に一対
の電極を有し、電極に通電すると上方に光を放射する構
造をしている。ＬＥＤ素子には、例えば、サファイアの
基板の上に窒化物半導体を成長させ、活性層が一般式Ｉ
ｎxＡｌyＧａ1-x-yＮで表現できる窒化物系のＬＥＤが
使用できる。この種のＬＥＤはｘの値に応じて発光ピー
ク波長が自在に変化できる。例えば、ｘ＝０．３に設定
すればピーク波長が４５０ｎｍの青色発光を得、ｘ＝
０．５３に設定すればピーク波長が５２０ｎｍの緑色発
光を得、ｘ＝０．９５に設定すればピーク波長は６３０
ｎｍの赤色発光を得ることができる。しかし、本発明に
利用できるＬＥＤは窒化物系に限らず、このようなフリ
ップチップ実装できる、同一面側に一対の電極がある構
造のＬＥＤならば全て使用することができる。The LED element 13 shown in FIG. 8 has a pair of electrodes on the lower surface and has a structure in which light is emitted upward when the electrodes are energized. In the LED device, for example, a nitride semiconductor is grown on a sapphire substrate, and the active layer has the general formula I
A nitride-based LED that can be expressed by nxAlyGa1-x-yN can be used. In this type of LED, the emission peak wavelength can be freely changed according to the value of x. For example, if x = 0.3 is set, blue light emission with a peak wavelength of 450 nm is obtained, and x =
If it is set to 0.53, green light emission with a peak wavelength of 520 nm is obtained, and if it is set to x = 0.95, the peak wavelength is 630.
A red emission of nm can be obtained. However, the LED applicable to the present invention is not limited to the nitride type, and any LED having a structure having a pair of electrodes on the same surface side which can be flip-chip mounted can be used.
【００３４】図８に示すように、セラミックス基板１１
の上に配線された導体配線１２に、導電性のろう材１５
を介してＬＥＤ素子の一対の電極１４を電気的に接続し
た。導電性ろう剤は、例えば半田などの低融点金属、導
電剤と接着剤とを混練りした金属ペーストが使用でき
る。ＬＥＤ素子１３をセラミックス基板の上に強固に固
定するために封止樹脂１６がＬＥＤ素子とセラミックス
基板の隙間に注入されている。As shown in FIG. 8, the ceramic substrate 11
Conductive brazing material 15 is attached to the conductor wiring 12 wired on the
The pair of electrodes 14 of the LED element were electrically connected via the. As the conductive brazing agent, for example, a low melting point metal such as solder, or a metal paste obtained by kneading a conductive agent and an adhesive can be used. A sealing resin 16 is injected into the gap between the LED element and the ceramic substrate in order to firmly fix the LED element 13 on the ceramic substrate.
【００３５】図３は、図８の平面図を表している。図３
のハーフカットライン３８に沿って割り出すことによ
り、図４に示すセラミックス支持部材１１の上に電極端
子１２を形成され、その上にＬＥＤ素子がフリップチッ
プ接続され、外縁１７がハーフカット加工されているチ
ップタイプＬＥＤを得た。FIG. 3 shows a plan view of FIG. FIG.
The electrode terminals 12 are formed on the ceramics supporting member 11 shown in FIG. 4 by indexing along the half-cut line 38, the LED element is flip-chip connected thereon, and the outer edge 17 is half-cut. A chip type LED was obtained.
【００３６】[0036]
【発明の効果】本発明は、以上説明したように構成され
ているので、以下に記載されるような効果を奏する。Since the present invention is configured as described above, it has the following effects.
【００３７】請求項１の構成とすることで、ＬＥＤ素子
に給電するためのワイヤーを使用しないフリップチップ
接続となり、ＬＥＤ素子からの発光をワイヤーが遮るこ
とがなくなり、そのことによる輝度低下の問題がなくな
った。According to the structure of claim 1, the flip chip connection does not use the wire for supplying power to the LED element, and the wire does not block the light emission from the LED element, which causes the problem of the decrease in brightness. lost.
【００３８】また、請求項１の構成とすることで、ワイ
ヤーを保護するキャビティーは必要としない。その結
果、チップタイプＬＥＤはコンパクトになり、高密度実
装が可能となり、そのことで例えば、高密度表示が可能
なＬＥＤディスプレイを実現できる。Further, with the structure of claim 1, the cavity for protecting the wire is not required. As a result, the chip-type LED becomes compact and high-density mounting becomes possible, and thus, for example, an LED display capable of high-density display can be realized.
【００３９】さらに、従来の構造ではＬＥＤ素子をキャ
ビティー内に固定するため、封止樹脂をキャビティー内
に満たす構造をとることを余儀なくされた。その結果、
ＬＥＤ素子に通電した時に発生する熱により封止樹脂が
膨張し、樹脂及びＬＥＤ素子の剥がれの原因になった
り、ＬＥＤ素子からの発光の一部の紫外線により、樹脂
の劣化を引き起こし、樹脂の透過性が低下することによ
りＬＥＤの輝度低下を引き起こした。これに対し、本発
明の構造では、キャビティーがないために膨張による剥
がれ問題はなく、しかも、ＬＥＤからの発光が封止樹脂
により遮られることもない。Further, in the conventional structure, since the LED element is fixed in the cavity, it is inevitable to adopt a structure in which the cavity is filled with the sealing resin. as a result,
The heat generated when the LED element is energized causes the encapsulating resin to expand, causing the resin and LED element to peel off, and causing some of the ultraviolet light emitted from the LED element to cause resin deterioration and resin penetration. As a result, the brightness of the LED is lowered. On the other hand, in the structure of the present invention, since there is no cavity, there is no problem of peeling due to expansion, and moreover, light emission from the LED is not blocked by the sealing resin.
【００４０】ＬＥＤ素子をセラミックスの支持部材の電
極端子とフリップチップ接続されて、しかも外縁がハー
フカットされていることで、セラミックス特有の脆さに
加え、精度良く分割でき、しかも、歪みを受けにくくな
り、そのためにＬＥＤ素子の剥がれの問題は最小限に抑
えられる。Since the LED element is flip-chip connected to the electrode terminal of the ceramic support member and the outer edge is half-cut, the LED element can be accurately divided in addition to the fragility peculiar to ceramics, and is less susceptible to distortion. Therefore, the problem of peeling of the LED element is minimized.
【００４１】請求項２の構成とすることにより、割り出
し時にＬＥＤ素子に歪みのかかりにくい、剥がれの歩留
まり低下の少ないチップタイプＬＥＤを得ることができ
る。With the structure of the second aspect, it is possible to obtain a chip-type LED in which the LED element is less likely to be distorted during indexing and the yield of peeling is less reduced.
【００４２】請求項３の構成とすることにより、割り出
し時にさらにＬＥＤ素子に歪みのかかりにくい、剥がれ
による歩留まり低下の少ないチップタイプＬＥＤを得る
ことができる。According to the structure of claim 3, it is possible to obtain a chip-type LED in which the LED element is less likely to be distorted during indexing and the yield due to peeling is small.
【００４３】[0043]
【図１】本発明のチップタイプＬＥＤの模式断面図FIG. 1 is a schematic sectional view of a chip-type LED of the present invention.
【図２】比較のためのチップタイプＬＥＤの模式断面図FIG. 2 is a schematic sectional view of a chip-type LED for comparison.
【図３】割り出し工程前のセラミックス基板の平面図FIG. 3 is a plan view of the ceramic substrate before the indexing process.
【図４】本発明のチップタイプＬＥＤの平面図FIG. 4 is a plan view of a chip type LED of the present invention.
【図５】グリーンシートのハーフカットを説明する模式
断面図FIG. 5 is a schematic cross-sectional view illustrating a half cut of a green sheet.
【図６】導体印刷を形成したグリーンシートの平面図FIG. 6 is a plan view of a green sheet on which conductor printing is formed.
【図７】補助孔を開けたグリーンシートの平面図FIG. 7 is a plan view of a green sheet with auxiliary holes.
【図８】割り出し工程前のセラミックス基板の断面図FIG. 8 is a sectional view of the ceramic substrate before the indexing step.
１１、２１・・・・・・セラミックス支持部材 １２、２２・・・・・・電極端子 １３、２３、３３・・・ＬＥＤ素子 １４、２４・・・・・・電極 １５・・・・・・・・・ろう剤 １６、２６・・・・・・封止樹脂 １７・・・・・・・・・外縁 ３１・・・・・・・・・セラミックス基板 ３２・・・・・・・・・導体配線 ３８・・・・・・・・・ハーフカットライン ３９・・・・・・・・・補助孔 ６１・・・・・・・・・グリーンシート ６２・・・・・・・・・導体印刷 11, 21 ... Ceramic support member 12, 22 ... Electrode terminal 13, 23, 33 ... LED element 14, 24 ... Electrode 15 ...・ ・ ・ Waxing agent 16, 26 ・ ・ ・ Sealant resin 17 ・ ・ ・ ・ ・ ・ Outer edge 31 ・ ・ ・ ・ ・ ・ ・ Ceramics substrate 32 ・ ・ ・ ・ ・ ・Conductor wiring 38 ・ ・ ・ ・ ・ ・ Half-cut line 39 ・ ・ ・ ・ ・ ・ ・ Auxiliary hole 61 ・ ・ ・ ・ ・ ・ ・ Green sheet 62 ・ ・ ・ ・ ・ ・printing
───────────────────────────────────────────────────── フロントページの続き (72)発明者 土内 彰 徳島県阿南市上中町岡491番地100 日亜化 学工業株式会社内 (72)発明者 為本 広昭 徳島県阿南市上中町岡491番地100 日亜化 学工業株式会社内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Akira Douchi 100 491 Oka, Kaminaka-cho, Anan City, Tokushima Prefecture 100 Nichia Chemical Industry Co., Ltd. 100 Nichia Chemical Industry Co., Ltd.
Claims (6)
ップタイプＬＥＤ。 （ａ）同一面側に一対の電極を有するＬＥＤ素子と、Ｌ
ＥＤ素子を固定しているセラミックスの支持部材を備
え、（ｂ）セラミックス支持部材には互いに接近して固
定されている一対の電極端子を有し、（ｃ）ＬＥＤ素子
の電極は、セラミックスの支持部材の電極端子に導電性
ろう材を介してフリップチップ接続され、（ｄ）ＬＥＤ
素子が載置されている平面に対して垂直な方向にあるセ
ラミックス支持部材の外縁は、ＬＥＤ素子が実装されて
いるセラミックス基板を、ハーフカットラインに沿って
割り出すことにより形成されている。1. A chip-type LED having the following conditions. (A) An LED element having a pair of electrodes on the same side, and L
The ceramic support member fixing the ED element is provided, (b) the ceramic support member has a pair of electrode terminals fixed close to each other, and (c) the electrode of the LED element is a ceramic support member. Flip-chip connection to the electrode terminals of the member through a conductive brazing material, (d) LED
The outer edge of the ceramic support member in the direction perpendicular to the plane on which the element is placed is formed by indexing the ceramic substrate on which the LED element is mounted along the half cut line.
ン上に中心が位置するように補助孔が形成されているこ
とを特徴とする請求項１に記載のチップタイプＬＥＤ。2. The chip-type LED according to claim 1, wherein an auxiliary hole is formed so that the center of the half-cut line is located on the ceramic substrate.
置するように補助孔が形成されていることを特徴とする
請求項１に記載のチップタイプＬＥＤ。3. The chip-type LED according to claim 1, wherein an auxiliary hole is formed so that a center thereof is located at an intersection of the half cut lines.
るチップタイプＬＥＤの製造方法。 （ｐ）セラミックスグリーンシートに、チップタイプＬ
ＥＤとして割り出すことで形成される電極を作製するた
めの導体印刷を施す工程、（ｑ）導体印刷を施されたセ
ラミックスグリーンシートにチップタイプＬＥＤとして
割り出すためのハーフカットラインを作製する工程、
（ｒ）導体印刷とハーフカットラインを作製したグリー
ンシートを脱脂し、次に焼結する工程、（ｓ）焼結され
たセラミックス基板に、同一面側に一対の電極を有する
ＬＥＤ素子をフリップチップ接続する工程、（ｔ）ＬＥ
Ｄ素子がフリップチップ接続されたセラミックス基板を
ハーフカットラインに沿って割り出す工程、4. A method of manufacturing a chip type LED, comprising the following steps. (P) Chip type L on the ceramic green sheet
A step of performing conductor printing for producing an electrode formed by indexing as ED, (q) a step of producing a half-cut line for indexing as a chip type LED on the ceramic green sheet on which the conductor is printed,
(R) A step of degreasing a green sheet on which conductor printing and half-cut lines are produced and then sintering, (s) a flip-chip LED element having a pair of electrodes on the same surface side on a sintered ceramics substrate Connecting step, (t) LE
A step of indexing the ceramic substrate to which the D element is flip-chip connected along the half-cut line,
に中心が位置するように補助孔を形成することを特徴と
する請求項４に記載のチップタイプＬＥＤの製造方法。5. The method of manufacturing a chip type LED according to claim 4, wherein the auxiliary hole is formed so that the center thereof is located on the half-cut line of the green sheet.
交差点に中心が位置するように補助孔を形成することを
特徴とする請求項４に記載のチップタイプＬＥＤの製造
方法。6. The method of manufacturing a chip-type LED according to claim 4, wherein the auxiliary hole is formed so that the center thereof is located at the intersection of the half-cut lines of the green sheet.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8687396A JP3656316B2 (en) | 1996-04-09 | 1996-04-09 | Chip-type LED and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8687396A JP3656316B2 (en) | 1996-04-09 | 1996-04-09 | Chip-type LED and manufacturing method thereof |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2004258208A Division JP4176067B2 (en) | 2004-09-06 | 2004-09-06 | Chip type LED |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH09283803A true JPH09283803A (en) | 1997-10-31 |
| JP3656316B2 JP3656316B2 (en) | 2005-06-08 |
Family
ID=13898954
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8687396A Expired - Fee Related JP3656316B2 (en) | 1996-04-09 | 1996-04-09 | Chip-type LED and manufacturing method thereof |
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| Country | Link |
|---|---|
| JP (1) | JP3656316B2 (en) |
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