JPH09259586A - Memory circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce consuming power even when a clock frequency becomes high, by providing a write circuit synchronous with clocks and a holding circuit for holding data and further providing the write circuit with a clock input circuit. SOLUTION: A threshold potential Vthck of a clock input inverter is set to be lower than a threshold potential Vth of a general inverter. Therefore, when an input signal of a clock input circuit 103 is input with a Vth signal amplitude, for instance, from a ground potential Vss, a write circuit 101 operates normally. A threshold potential of the clock input circuit 103 is easily realized by adjusting a gate length ratio of a Pch transistor and an Nch transistor, and an amplitude of clocks is made small without manufacturing costs increased. An increase of consuming power is restricted even when a clock frequency is raised.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory circuit device in a semiconductor integrated circuit.

[0002]

2. Description of the Related Art FIG. 6 shows the structure of a register circuit which is an example of a conventional CMOS memory circuit device. 6 in FIG.
Reference numeral 01 is a writing circuit synchronized with the clock, and 602 is a holding circuit for holding the input data.

A conventional CMOS memory circuit device will be described below with reference to the drawings. If the clock signal CK is High and the inverted signal CK * of CK is in the Low state, the writing circuit 601 is in the operating state and the inverted signal of the input signal IN is written in the holding circuit 602. Next, when the clock is inverted and CK becomes Low and CK * becomes High, the write circuit 6
01 becomes a non-operation state, and the holding circuit 602 holds the data written immediately before the clock is inverted.

[0004]

In such a memory circuit device, it is necessary to input a clock signal with a signal amplitude from the ground potential VSS to the power supply potential VDD in order to normally operate writing and holding of input data. There is.
Therefore, there is a drawback that the power consumption increases in proportion to the clock frequency.

In view of the above problems, it is an object of the present invention to provide a memory circuit device capable of suppressing power consumption even when the clock frequency becomes high.

[0006]

In order to solve this problem, the present invention comprises a write circuit synchronized with a clock and a holding circuit for holding data, and the write circuit is provided with a clock input circuit. It is a thing. Further, the threshold potential of the clock input circuit is set lower or higher than the threshold potential of a normal gate.

[0007]

BEST MODE FOR CARRYING OUT THE INVENTION

(Embodiment 1) Hereinafter, Embodiment 1 of the present invention will be described with reference to FIGS.

FIG. 1 is a circuit diagram of a memory circuit device of the present invention. In FIG. 1, 101 is a write circuit, 102 is a holding circuit, and 103 is a clock input circuit.

The operation of the memory circuit device configured as described above will be described below. 201 in FIG.
Is an input / output characteristic of an inverter forming the clock input circuit 103, and 202 is an input / output characteristic of a normal inverter, for example, an inverter forming the holding circuit 102.
As is apparent from FIG. 2, the threshold potential of the normal inverter is Vth, whereas the threshold potential of the clock input inverter is Vthck, which is set lower than the threshold potential Vth of the normal inverter. Therefore, the input signal of the clock input circuit 103 is
For example, when the signal amplitude of the normal threshold potential Vth is input from the ground potential VSS, the output signal is output with the signal amplitude of the power supply potential VDD from the ground potential VSS, so that the writing circuit 101 operates normally.

FIG. 3 is a diagram showing the signal amplitude in this embodiment. In FIG. 3, 301 is a clock signal, and 302 is a clock signal.
Is the signal amplitude of the normal signal.

The threshold potential of the clock input circuit 103 can be easily realized by adjusting the gate length ratio of the Pch transistor and the Nch transistor, and the clock amplitude can be reduced without increasing the manufacturing cost. Therefore, compared with the conventional memory device, the increase in power consumption can be suppressed even if the clock frequency increases.

(Embodiment 2) In FIG. 4, 401 is an input / output characteristic of an inverter forming the clock input circuit 103, and 402 is an input / output characteristic of an ordinary inverter, for example, an inverter forming the holding circuit 102. FIG.
As is clear from the above, the threshold potential of the normal inverter is Vth, whereas the threshold potential of the clock input inverter is Vthck, which is set higher than the threshold potential of the normal inverter. Therefore, when the input signal of the clock input circuit 103 is input with the signal amplitude of the power supply potential VDD from the normal threshold potential Vth, for example, the output signal changes from the ground potential VSS to the power supply potential Vth.
Since the signal amplitude of DD is output, the writing circuit 101 operates normally.

FIG. 5 is a diagram showing the signal amplitude in this embodiment. In FIG. 5, 501 is a clock signal and 502.
Is the signal amplitude of the normal signal.

In the above description, the write circuit 10 is used.
Although the example in which 1 is configured by the totem pole type three-state inverter has been described, other memory circuit devices such as configured by the transfer gate type inverter can be similarly implemented.

[0015]

As described above, according to the present invention, the signal amplitude of the clock can be made smaller than the other signal amplitudes, and the remarkable effect that the power consumption can be reduced even if the operating frequency increases. can get.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a memory circuit device according to a first embodiment of the present invention.

FIG. 2 is an input / output characteristic diagram of an inverter in the memory circuit device according to the same embodiment.

FIG. 3 is an explanatory diagram of signal amplitude in the memory circuit device according to the same embodiment.

FIG. 4 is an input / output characteristic diagram of an inverter in the memory circuit device according to the second embodiment of the present invention.

FIG. 5 is an explanatory diagram of signal amplitude in the memory circuit device according to the same embodiment.

FIG. 6 is a circuit diagram of a conventional memory circuit device.

[Explanation of symbols]

 101 write circuit 102 holding circuit 103 clock input circuit 201 input / output characteristic diagram of inverter for clock input circuit 202 input / output characteristic diagram of inverter for normal circuit 301 signal amplitude of clock 302 signal amplitude of normal signal 401 input of inverter for clock input circuit Output characteristic diagram 402 Input / output characteristic diagram of inverter for normal circuit 501 Signal amplitude of clock 502 Signal amplitude of normal signal 601 Write circuit 602 Holding circuit

Claims (2)

[Claims] 1. A writing circuit synchronized with a clock, and a holding circuit for holding data, the writing circuit having a clock input circuit, wherein a threshold potential of the clock input circuit is higher than a threshold potential of a normal gate. A memory circuit device characterized in that it is also set to be low or high. 2. The memory circuit device according to claim 1, wherein a threshold potential of the clock input circuit is set to be lower or higher than a threshold potential of a gate forming the holding circuit.