JPH09251439A - Distribution type data transfer system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a distribution type data transfer system which can transfer the data in a short time to plural PCI target devices and shortens the occupation time of the PCI local bus band. SOLUTION: A PCI master device 1 and the PCI target devices 2 and 3A are connected to a PCT local bus 4. The device 3A holds a multi-cast address equal to the base address of the device 2 in its multi-cast address table 35. Then the device 2 carries out the normal transfer of data via the bus 4, and the device 3A monitors the transfer of data between both devices 1 and 2 and fetches the data to the device 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a delivery-type data transfer system used in a system having a PCI local bus, and more particularly to a delivery type data transfer system for multicasting the same data on the PCI local bus.

[0002]

2. Description of the Related Art In recent years, a PCI local bus has been adopted and commercialized as a local bus for personal computers and workstations. The PCI local bus is a technology that enables high-speed data transfer and is standardized.

FIG. 6 is a block diagram showing the configuration of a conventional delivery type data transfer system using a PCI local bus. In FIG. 6, the delivery-type data transfer system is a PC.
I master device 100 and a plurality (two in the figure) of PCIs
Target devices 200 and 300, PCI master device 100, and PCI target devices 200 and 30
PCI local bus 4 that connects 0 to each other so that they can communicate with each other
00.

The PCI target device 200 is a PC
It includes an I-bus control circuit 210 and a memory 280. PC
The I-bus control circuit 210 includes a configuration register base address table 212, an address comparison circuit 213, and a data write circuit 214. PC
The I target device 300 includes the PCI bus control circuit 3
10 and a memory 380. PCI bus control circuit 31
0 is the configuration register table 312
Address comparison circuit 313 and data write circuit 3
14 and.

The master device 100 functions as a bus master for the PCI local bus 400 and has a function of transferring data to the PCI target devices 200 and 300.

The configuration register base address tables 212 and 312 are configuration registers conforming to the PCI standard. Individual address values assigned to the PCI target devices 200 and 300 are stored in the PCI local bus 400 in accordance with the PCI standard. Written and stored via.

The base address of the configuration register base address table 212 is, for example, "00".
10 × XXX × h (lower 16 bits x indicates an arbitrary value), and the base address of the configuration register base address table 312 is, for example, “00”.
20 × XXX ”.

When data is transferred to the PCI target device 200 and written to the memory 280, the PCI master device 100 firstly addresses the address "00" assigned to the PCI target device 200 in the address phase.
10 × XXX ”is output to the PCI local bus 400. The address comparison circuit 213 of the PCI target device 200 compares the address “0010 × xxx” on the PCI local bus 400 with the configuration register base address table 212, and if the address is to be written in the memory 280, the data is written. The writing circuit 214 is instructed to write data.

Next, the PCI master device 100
The data to be transferred to the PCI target device 200 in the data phase is output to the PCI local bus 400.
The data write circuit 214 uses the PCI local bus 40.
The data is loaded from 0 and the loaded data is stored in the memory 2
Write to 80. As a result, data is transferred from the master device 100 to the PCI target device 200, and the transferred data is written in the memory 280.

Further, the PCI target device 200
When the same data transferred to another PCI target device 300 is written to the memory 380,
The master device 100 first performs P in the address phase.
The address value “0020 × XXX” assigned to the CI target device 300 is output to the PCI local bus 400. The address comparison circuit 313 of the PCI target device 300 compares the address “0020xxxxx” on the PCI local bus 400 with the configuration register base address table 312, and if the address is to be written in the memory 380, the data is written. The writing circuit 314 is instructed to write data.

Next, the PCI master device 100
The data to be transferred to the PCI target device 300 in the data phase is output again to the PCI local bus 400. The data writing circuit 314 fetches data from the PCI local bus 400 and writes the fetched data in the memory 380. As a result, the master device 10
Data is transferred from 0 to the PCI target device 300, and the transferred data is written in the memory 380. By transferring the same data twice in this way,
Delivery type data transfer can be performed.

[0012]

However, in the conventional delivery type data transfer system, when performing delivery type data transfer, it is necessary to repeat the data transfer by the number of the transfer destination PCI target devices. As a result, there is a problem in that it takes a long time to transfer data and the bandwidth of the PCI local bus is occupied for a long time.

The present invention solves the above-mentioned technical problems and enables the same data to be transferred to a plurality of PCI target devices in a short time, and the distribution-type data transfer in which the time occupied by the PCI local bus band is shortened. The purpose is to provide a system.

[0014]

A distribution-type data transfer system in which the same data is distributed from a PCI master device to two or more PCI target devices via a PCI local bus, and each PCI target device comprises: A PC including a configuration register, an address comparison means, and a data acquisition means
The I master device first sends a unique base address for one PCI target device in each PCI target device to the PCI local bus, and then delivers the data to be delivered to the PCI local bus,
The PCI target device other than the I target device further includes a multicast address storage unit, and the configuration register holds the unique base address assigned to the PCI target device of the PCI master device by the PCI master device, and the multicast address storage unit. Holds the same multicast address as the base address assigned to one PCI target device by the PCI master device,
The address comparison circuit of another PCI target device is
Base address of the configuration register,
The address on the PCI local bus is compared, and if the result of the comparison indicates a match, the data fetching means is instructed to fetch the data on the PCI local bus. The multicast address is compared with the address corresponding to the data on the PCI local bus, and when the comparison results in a match, the data fetching means is instructed to fetch the data on the PCI local bus.

Each PCI target device further includes a data storage means, and the data capturing means can write the captured data in the data storage means.

One PCI target device further includes a data storage means, the data capturing means writes the captured data in the data storage means, and the other PCI target devices further correct the error in the data captured by the data capturing means. It is also possible to provide an error correction encoding means for performing the encoding for and the encoded data storage means for storing the encoded data encoded by the error correction encoding means.

[0017]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of a delivery type data transfer system using a PCI local bus according to the first embodiment of this invention. In FIG. 1, the PCI
Distribution type data transfer system by local bus is PC
The I master device 1 includes a plurality of PCI target devices 2 and 3A, a PCI master device 1, and a PCI local bus 4 that connects the PCI target devices 2 and 3A so that they can communicate with each other.

The PCI target device 2 includes a PCI bus control circuit 21 and a memory 28. The PCI bus control circuit 21 includes a configuration register base address table 22, an address comparison circuit 23, and a data writing circuit 24.

The PCI target device 3A is a PCI
It includes a bus control circuit 31A and a memory 38A. PCI
The bus control circuit 31A includes a configuration register base address table 32 and an address comparison circuit 3
3, a data writing circuit 34A, and a multicast address table 35.

The PCI master device 1 becomes a bus master on the PCI local bus 4 and has a function of transferring data to the PCI target devices 2 and 3A.

The configuration register base address tables 22 and 32 are configuration registers conforming to the PCI standard, and the individual address values assigned to the PCI target devices 2 and 3A conform to the PCI standard according to the PCI local bus 4. To store the base address.

FIG. 2 is a diagram showing an example of the configuration of base addresses assigned to the configuration register base address tables 22 and 32 of FIG. In particular, FIG. 2A shows a general structure of the base address,
FIG. 2B shows a specific structure of the base address.

In FIG. 2, the configuration register base address tables 22 and 32 respectively hold a plurality of base addresses BA (1), BA (2), ... As unique base addresses BA (y). . When there are multiple base addresses,
Each base address is stored as a table.
The unique base address BA (y) of the configuration register base address table 22 is, for example, "0010xxxxxx" h (lower 16 bits x indicates an arbitrary value). Unique base address BA of the configuration register base address table 32
(Y) is, for example, "0020xxxx" h. In the lower 16 bits “×××” h, the memories 28 and 38A are stored.
The address to be stored in is described. The upper 16 bits of the address on the PCI local bus 4 and the base address B
If the upper 16 bits “0010” h of A (y) match, it means that the PCI target device 2 is selected.

The address comparison circuit 23 compares the address on the PCI local bus 4 with the base address of the configuration register base address table 22, and if the address is to be written in the memory 28, the address is written to the data writing circuit 24. Instruct to write.

The multicast address table 35 is
The same multicast address as the base address assigned to the PCI target device 2 is written by the PCI master device 1 via the PCI local bus 4 to store the multicast address.

FIG. 3 is a diagram showing an example of the structure of the multicast address assigned to the multicast address table 35 of FIG. Particularly, FIG. 3A shows a general structure of the multicast address, and FIG. 3B shows a specific structure of the multicast address.

In FIG. 3, the multicast address number x represents the number of the stored multicast address. The PCI address PA (x) represents the start address of the block that takes in the data. The size S (x) is the size of a block that captures data. For example, PCI address PA
When (x) is “00100100” h and the size S (x) is “10” h, the PCI address PA (x) is “00”.
In the range of 100100 "h to" 0010010F "h, data is captured. The target memory address TA (x) represents the start address of the block of the memory 38A inside the PCI target device 3A to be written. When there are a plurality of multicast addresses, each multicast address is stored as a table.

Similar to the address comparison circuit 23, the address comparison circuit 33 compares the address on the PCI local bus 4 with the base address of the configuration register base address table 32, and if it is the address to be written in the memory 38A, Data writing circuit 34
Instruct A to write.

When the address on the PCI local bus 4 and the base address of the configuration register base address table 32 are different, the address comparison circuit 33 further addresses the data on the PCI local bus 4 and the multicast address. The address is compared with the multicast address in the address table 35, and if the address is to be written in the memory 38A, the data writing circuit 34A is instructed to write.

The data write circuit 24 performs an instruction from the address comparison circuit 23 and controls the PCI local bus 4, fetches data according to the state of the PCI local bus 4, and writes the fetched data in the memory 28.

The data write circuit 34A controls the PCI local bus 4 by instructing from the address comparison circuit 33, fetches data according to the state of the PCI local bus 4, and writes the fetched data in the memory 38A.

The operation of the distribution type data transfer system configured as above will be described. First, PCI
The PCI master device 1 writes the base address to the configuration register base address tables 22 and 32 of the PCI target devices 2 and 3A according to the standard procedure of writing to the configuration register. Next, the PCI master device 1 sets the block for which the multicast address and data are to be fetched in the multicast address table 35 of the PCI target device 3A.

The multicast address table 3
When 5 is provided in the PCI configuration space, the PCI master device 1 writes by configuration access. If the PCI master device 1 is provided in the memory space, the PCI master device 1 performs writing by memory access.

Here, the PCI master device 1 is the PCI
For the target device 2, the address "00100
When the memory write is performed to 100 "h, the data transfer between the PCI master device 1 and the PCI target device 2 is performed by the normal transfer on the PCI local bus 4.

The address comparison circuit 23 compares the value of the configuration base address table 22. Now, the address on the PCI local bus 4 and the configuration address base register table 2
When the values of 2 match, the address comparison circuit 23 instructs the data writing circuit 24 to write data. The data write circuit 24 uses the PCI local bus 4
Control is performed and writing to the memory 28 is performed.

On the other hand, in the PCI target device 3A, the address comparison circuit 33 further differs from the address on the PCI local bus 4 by the value of the configuration address base register table 32.
The address on the CI local bus 4 is compared with the multicast address in the multicast address table 35. Now, since the address on the PCI local bus 4 and the multicast address in the multicast address table 35 match, the address comparison circuit 33
The data write circuit 34A is instructed to write data. The data write circuit 34A is in a state on the PCI local bus 4, that is, the IRDY # signal and TRDY.
The state of the # signal is monitored, this data is fetched at the timing when the data is transferred to the PCI target device 2, and the fetched data is written in the memory 38A.

As described above, according to the present embodiment, P
The CI target device 3A is provided with the multicast address table 35, and the base address of the configuration base address table 32 and the address on the PCI local bus 4 are compared. If it is instructed to take in the data on the bus 4 and the result of comparison is that they do not match, the multicast address table 3
5 is compared with the address on the PCI local bus 4, and when the comparison results in a match, the data write circuit 34A is instructed to fetch the data on the PCI local bus 4. As a result, other PC
The data transferred to the I target device 2 can be taken in, and it is not necessary to transfer the data a plurality of times. Therefore, the same data can be transferred to a plurality of PCI target devices 2 and 3A at one time, the data transfer time is shortened, and the occupation time of the PCI local bus 4 is shortened.

Further, according to the present invention, each PCI target device 2, 3A further includes memories 28, 38A, and the data write circuits 24, 34A write the fetched data in the memories 28, 38A. Therefore, data duplication is ensured.

FIG. 4 shows the PCI of the second embodiment of the present invention.
It is a block diagram which shows the structure of the delivery type data transfer system by a local bus. The parts corresponding to those in the first embodiment are designated by the same reference numerals, and detailed description thereof will be omitted.

It should be noted that in the distribution type data transfer system of FIG. 4, a parity arithmetic circuit 34B is provided in the PCI bus control circuit 31B instead of the data write circuit 34A of the PCI bus control circuit 31A of the embodiment of FIG. In addition, a parity operation result storage unit 38B is provided instead of the memory 38A.

The parity operation circuit 34B performs almost the same operation as the data write circuit 34A, that is,
The instruction from the address comparison circuit 23 and the control of the PCI local bus 4 are performed, and data is taken in according to the state of the PCI local bus 4. However, the parity arithmetic circuit 34B
Is different in that instead of writing to the memory, a parity operation is performed as encoding for error correction of the fetched data and the writing of the result is controlled.

The parity calculation result storage section 38B stores the result of the parity calculation.

FIG. 5 is a diagram showing an example of the structure of the multicast address assigned to the multicast address table 35 of FIG. In particular, FIG. 5A shows the general structure of the multicast address, and FIG. 5B shows the specific structure of the multicast address.

In FIG. 5, the multicast address number x, PCI address PA (x) and size S (x) are
The configuration is similar to that of the first embodiment (see FIG. 3). The parity write block PB (x) is a block in which the parity calculation result is written. For example, PCI address P
The parity calculation result for the data located in the space of size A (1) to size S (1) is stored in the area indicated by the parity write block PB (1).

The operation of the delivery type data transfer system using the PCI local bus configured as described above will be described.

First, the multicast address table 3
The operations up to 5 and writing to the configuration register base address tables 22 and 32 are the same as those in the first embodiment.

Here, the PCI master device 1 is the PCI
For the target device 2, the address "00100
When a memory write is performed on 100 "h, the PCI target device 2 operates in the same manner as in the first embodiment.

In the PCI target device 3B, the address comparison circuit 33 compares it with the contents of the multicast address table 35. Now, since the address on the PCI local bus 4 and the multicast address table 35 match, the multicast address table 35 performs the parity operation on the parity operation circuit 34B.
To instruct. The parity operation circuit 34B monitors data transfer on the PCI local bus 4, fetches data, performs a parity operation, and writes the parity operation result storage unit 38B.

As described above, according to this embodiment, the same data can be transferred to a plurality of PCI target devices 2 and 3B at one time, the data transfer time can be shortened, and the PCI
The occupation time of the local bus 4 is shortened.

Further, according to the present embodiment, the PCI target device 2 further includes the memory 28, the data write circuit 24 writes the fetched data in the memory 28, and the PCI target device 3B further includes the parity operation circuit. Since the data captured by 34B is encoded for error correction and the encoded data encoded by the parity arithmetic circuit 34B is stored in the parity arithmetic result storage unit 38B, the data stored in the memory 28 is stored. The error can be corrected with the encoded data.

In the first embodiment, there is one target device having the multicast address table 35 like the PCI target device 3A.
PCI target device 3A is PCI local bus 4
Since we are only monitoring the above data transfer, the PCI
A plurality of devices having the same function as the target device 3A may exist on the PCI master device 1. In this case, one-to-many multicast transfer can be performed.

Further, in the second embodiment, one target device such as the PCI target device 2 which does not have the multicast address table 35 is used.
PCI target device 3B is PCI local bus 4
Since we are only monitoring the above data transfer, the PCI
Select a device that has the same function as target device 2.
A plurality of PCI target devices 2 can be present on the CI master device 1, and data transfer to each PCI target device 2 can be performed by one PCI target device 3B for parity calculation.

The target device on the PCI master device 1 is replaced by a plurality of PCI target devices 3A.
Alternatively, it may be configured by only a plurality of PCI target devices 3B.
The I target device 3B may be mixed.

Further, the target device may be configured to have a plurality of functions in one device instead of individual devices.

[0055]

According to the present invention, the base address of the configuration register is compared with the address on the PCI local bus, and if the comparison results in a match, the data on the PCI local bus is loaded into the data loading means. , And if the comparison does not match,
The multicast address in the multicast address storage means is compared with the address on the PCI local bus, and when the comparison results in a match, the data fetching means is instructed to fetch the data on the PCI local bus, so that another PCI device is used. The data to be transferred can be taken in and the data need not be transferred multiple times. Therefore, the same data can be transferred to a plurality of PCI target devices at one time, the data transfer time is shortened, and the PCI local bus occupation time is shortened.

Further, according to the present invention, since each PCI target device is further provided with the data storage means, and the data fetching means writes the fetched data in the data storage means, duplication of data is prevented. Reserved.

According to the present invention, one PCI target device further includes a data storage means, the data fetching means writes the fetched data in the data storage means, and the other PCI target devices further fetch the data. Since the data taken in by the means is coded for error correction and the coded data coded by the error correction coding means is stored, the error in the data stored in the data storage means is coded. Can be repaired with data.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a distribution type data transfer system using a PCI local bus according to a first embodiment of this invention.

2 is a diagram showing an example of a configuration of base addresses assigned to configuration register base address tables 22 and 32 of FIG.

3 is a diagram showing an example of a configuration of a multicast address assigned to a multicast address table 35 of FIG.

FIG. 4 is a block diagram showing a configuration of a distribution type data transfer system using a PCI local bus according to a second embodiment of this invention.

5 is a diagram showing an example of a configuration of a multicast address assigned to a multicast address table 35 of FIG.

FIG. 6 is a block diagram showing the configuration of a conventional delivery type data transfer system using a PCI local bus.

[Explanation of symbols]

1 ... PCI master device 2, 3A, 3B ... PCI target device 4 ... PCI local bus 21, 31A, 31B ... PCI control circuit 22, 32 ... Configuration register base address table 23, 33 ... Address comparison circuit 24, 34A ... Data Write circuit 28, 38A ... Memory 34B ... Parity calculation circuit 35 ... Multicast address table 38B ... Parity calculation result storage unit

Claims (3)

[Claims] 1. A distribution-type data transfer system in which the same data is distributed from a PCI master device to two or more PCI target devices via a PCI local bus, wherein each PCI target device is a configuration register. The PCI master device first transmits a unique base address for one PCI target device among the PCI target devices to the PCI local bus and then distributes it. Data to be delivered to the PCI local bus, the PCI target devices other than the one PCI target device further include: a multicast address storage unit, the configuration register, the PCI Holds a unique base address assigned to its own PCI target device by the mobile device, and the multicast address storage means holds the same multicast address as the base address assigned to the one PCI target device by the PCI master device. Then, the address comparison circuit of the other PCI target device compares the base address of the configuration register with an address on the PCI local bus, and if the comparison results in a match, the PCI local device stores the PCI local data. When it is instructed to take in the data on the bus and the result of the comparison is that they do not match, the multicast address of the multicast address storage means and the P
A delivery-type data transfer system, characterized in that an address on a CI local bus is compared, and when the comparison results in a match, the data capturing means is instructed to capture data on the PCI local bus. 2. The delivery-type data transfer according to claim 1, wherein each of the PCI target devices further includes a data storage unit, and the data acquisition unit writes the acquired data in the data storage unit. system. 3. The one PCI target device is
Furthermore, the data storage means is provided, the data capture means writes the captured data in the data storage means, and the other PCI target device further performs encoding for error correction of the data captured by the data capture means. The delivery-type data transfer system according to claim 1, further comprising: an error correction coding unit that performs the coding, and a coded data storage unit that stores the coded data coded by the error correction coding unit.