JPH09245689A - Image display device using field-emission cold cathode - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent point and line defects on a screen that result from electric short circuits, leakage, and dielectric breakdown. SOLUTION: This image display device has a plurality of picture elements arranged in a matrix within an active region 11. Each of the picture elements has a field-emission cold cathode constructed of a cathode line 12, an emitter 14, a gate line 16, and the like. The cathode line 12 comprises a number of horizontally extending parallel line elements 12a. The gate line 16 comprises a number of vertically extending parallel line elements 16a. Plural cathode line elements 12a and gate line elements 16a are allotted to each one picture element and are connected to feeding electrodes 12b, 16b. A fuse 17 is placed outside the active region 11 so that each gate line element 16a is connected to the feeding electrode 16b.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image display device using a field emission cold cathode, and more particularly to a flat panel image display device.

[0002]

2. Description of the Related Art In recent years, development of a method for forming a field emission cold cathode by using a fine processing technique developed mainly for semiconductor integrated circuits has been actively pursued. Until now, application research of micro cold cathodes to ultra-high-speed microwave devices, power devices, electron beam devices, flat panel image display devices, etc. has been conducted. A typical example of this is CA Spindt.
(Jounal of Applied Phys
ics, Vol. 47, 5248 (1976)), transfer molding method (Japanese Patent Application No. 4-186753), and the like. Further, an electronic device using a cold cathode, for example, a flat panel image display device has been tried.

In an electronic device using such a cold cathode, for example, a flat panel image display device, a large number of cold cathodes formed on the substrate by the Spindt method and a glass face plate having a transparent electrode and a phosphor layer are provided. Are arranged to face each other with a predetermined interval. The image is displayed by using the light emission of the electron beam from the cold cathode as a light source. Therefore, this display device does not require a backlight and is a self-luminous type, unlike a display device using liquid crystal. Therefore, this display device has a possibility of low power consumption, and has attracted attention from this point.

[0004]

However, in the above-mentioned flat panel image display device, electrical shorts and leaks easily occur between the gate line electrode and the cathode line electrode, and line defects, point defects, and Further, there is a problem that dielectric breakdown occurs frequently.

In order to avoid such a problem, the emitter is divided into a number of sections, and a resistive ballast layer is interposed between the cathode line electrode and the emitter (IEEE T.
RANSACTIONS ON ELECTRON DEVICES, Vol. 38, No. 10,
October, 1991), and a method using a fuse (Autumn 1993 Autumn Applied Physics Society Proceedings 27p-Y-9).
However, the resistance ballast layer alone cannot completely interrupt the current, and thus it is incomplete as a countermeasure against electrical leakage. Further, if the fuse structure is adopted, it is difficult to increase the formation density of the emitters, which causes a problem such as a decrease in emission current and a decrease in brightness.

The present invention has been made in view of the above problems, and in an image display device using a field emission type cold cathode, a screen point defect and a line defect caused by electrical short circuit, leak, and dielectric breakdown. The purpose is to obtain a high-brightness image display function by preventing this.

[0007]

SUMMARY OF THE INVENTION A first aspect of the present invention is as follows.
In an image display device using a field emission cold cathode, a plurality of emitters arranged so that at least one corresponds to each of a plurality of pixels arranged in a matrix in an active region, and each of the pixels. A cathode line connected to the emitter to which the pixel belongs, and a gate line that is disposed on the cathode line through an insulating film and has a portion facing the emitter that belongs to each of the pixels in order to emit electrons from the emitter. And the gate line corresponding to each pixel is composed of a plurality of line elements, and each line element is connected to a power supply electrode through an individual fuse arranged outside the active region. And

A second aspect of the present invention is to arrange an image display device using a field emission cold cathode so that at least one pixel corresponds to each of a plurality of pixels arranged in a matrix in the active region. Multiple emitters,
The cathode line is connected to the emitter belonging to each of the pixels, and is disposed on the cathode line via an insulating film, and opposes the emitter belonging to each of the pixels for emitting electrons from the emitter. A gate line having a portion, and the cathode line corresponding to each pixel includes a plurality of line elements, and each line element is connected to a power supply electrode through an individual fuse.

A third aspect of the present invention is the image display device using the field emission cold cathode according to the second aspect, characterized in that the fuse is disposed outside the active region.

A fourth aspect of the present invention is an image display device using the field emission cold cathode according to any one of the first to third aspects, wherein the cathode line is connected to the emitter through a resistive ballast layer. And that the fuse is an immediate blow fuse having a melting time of 0.1 msec or less.

[0011]

1 is a plan view showing an array substrate of a flat panel type image display device using a field emission type cold cathode according to an embodiment of the present invention, and FIG. 2 is a line II-II of FIG. FIG. 3 is a cross-sectional view of the flat panel image display device taken along the line.

The image display device has a plurality of pixels arranged in a matrix in the active region 11. Each pixel is an emitter or gate line (electrode) of the form described later.
And a field emission cold cathode composed of

The image display device has a glass substrate 10 as a support. A cathode line (electrode) 12 made of a patterned conductive layer is provided on the glass substrate 10. The cathode line (electrode) 12 is composed of a large number of line elements 12a extending parallel to the lateral direction.

A resistive ballast layer 1 is formed on the cathode line 12.
3 is arranged, and a plurality of gate lines (electrodes) 16 are further arranged thereon via the insulating layer 15. The gate line (electrode) 16 is composed of a large number of line elements 16a extending in parallel in the vertical direction.

That is, the cathode line 12 and the gate line 16 are orthogonal to each other, and pixels are formed at the intersections thereof. The line element 12a of the cathode line 12 corresponding to one pixel is composed of a desired number, for example, 4 to 5
The plurality of line elements 12a for pixels are connected to the common power supply electrode 12b outside the active region 11. On the other hand, 1
The line elements 16a of the gate line 16 corresponding to the pixels are formed in a desired number, for example, nine, and a plurality of line elements 16a for one pixel are connected to the common power supply electrode 16b outside the active region 11. It should be noted that, in FIG. 1, for convenience of drawing, the cathode line element 12a and the gate line element 16a for one pixel are each shown as three pieces.

A plurality of field emission type emitters 14 are arranged on the resistive ballast layer 13. The emitter 14 is, for example,
It is manufactured by the spindt method or the transfer molding method. The emitter 14 corresponding to one pixel constitutes an emitter array including a plurality of emitters 14. Openings are formed in the insulating film 15 and the gate line element 16 a so as to correspond to the respective emitters 14. Therefore, the gate line element 16a functions as an electrode surrounding each emitter 14 with a slight gap.

A fuse 17 is arranged so as to connect each line element 16a of the gate line 16 and the power supply electrode 16b. The fuse 17 is made of a conductive layer made of a material different from that of the gate line element 16 a, and is arranged outside the active region 11.

A glass face plate 20 is arranged with a predetermined gap so as to face the glass substrate 10.
A seal member 1 that surrounds the periphery of the active region 11 between the glass substrate 10 and the glass face plate 20.
8 forms an airtight vacuum space 19. On the inner surface of the glass substrate 10 facing the emitter 14, a transparent electrode (anode electrode) 21 made of ITO and a phosphor layer 22 are sequentially stacked.

FIG. 3 is a cross-sectional view showing, in the order of steps, an embodiment of a method of manufacturing the array substrate of the flat panel image display device shown in FIGS. First, a cathode metal film was deposited on the glass substrate 10 and the resistance layer 13 was formed. ITO was used as the cathode metal, and the resistance layer 13 was formed of an amorphous Si layer having a thickness of about 5 μm. Next, the resistance layer 13 and the cathode metal film were patterned by stepper exposure and etching to form a cathode line element 12a having the resistance layer 13 on the upper surface (FIG. 3A).

The cathode line element 12a has a length of 14 m.
m, width 18 μm, line element interval 2 μm. Cathode line element 12a corresponding to one pixel (100 μm square)
The number of the power supply electrodes is 12
b (width 90 μm).

Next, an insulating layer 15 was formed on the resistance layer 13 by using, for example, a deposition oxide film by using a CVD apparatus. Further, a MoSi film was deposited as a gate metal film on the insulating layer 15 and patterned to form a gate line element 16a and a power supply electrode 16b. Further, Ag having a rapid temperature rise was vapor-deposited and patterned to form the fuse 17 (FIG. 3B).

The gate line element 16a has a length of 14 m.
m, width 9 μm, line element interval 1 μm. The number of gate line elements 16a corresponding to one pixel (100 μm square) is set to nine, and the gate line elements 16a are grouped together to form a common power supply electrode 16b.
(Width 90 μm). The fuse 17 has a length of 50
The ultrafast fuse has a width of 2 μm and a melting time of 0.1 msec or less.

Next, an opening 15a having a diameter of about 1 μm was formed in the gate line 16 and the insulating layer 15 by etching as a window for forming an emitter by etching. Next, a sacrificial layer is applied to the surfaces of the gate line element 16a, the power supply electrode 16b, the fuse 17, and the like, and the emitter metal is deposited while rotating the sample while tilting the sample with respect to the target. 14 was formed (FIG. 3 (c)). The emitter 14 had a conical shape with a height of about 1.2 μm, and Mo was used as the emitter metal. After forming the emitter 14, excess emitter metal was removed along with the sacrificial layer.

Next, a glass face plate 20 provided with a transparent electrode (anode electrode) 21 and a phosphor layer 22.
Were made to face the glass substrate 10 at intervals of 500 μm and bonded (FIG. 2). Next, a drive circuit was attached to the cathode line power supply electrode 12b and the gate line power supply electrode 16b. In this way, a flat image display device in which one pixel is 100 μm square and the active region 11 is 13.5 mm square is completed.

In the flat panel image display device formed under such conditions, a voltage of 120 V is applied between the gate and the cathode and a voltage of 400 V is applied between the anode and the cathode in accordance with the pixel signal.
It was driven by applying the voltage of. As a result, it was possible to obtain a good image in which the luminance of the pixels was excellent and there was little variation in each luminance. Moreover, the occurrence of point defects and line defects on the screen was small, and the device life was greatly improved compared to conventional devices. It was also found that the quick-break fuse 17 blows before the current in the short-circuited portion is suppressed by the effect of the resistance ballast layer 13, that is, the fuse 17 operates reliably.

FIG. 4 is a plan view showing an array substrate of a flat panel image display device using a field emission type cold cathode according to another embodiment of the present invention, and FIG. 5 is a line V-V of FIG. FIG. 3 is a sectional view of the flat panel image display device along the line.

In this flat panel image display device, each line element 12a of the cathode line 12 and the power supply electrode 12b.
A fuse 17 is arranged so as to connect with. The fuse 17 is made of a conductive layer made of a material different from that of the cathode line element 12 a, and is arranged outside the active region 11. On the other hand, the gate line element 16a is directly connected to the power supply electrode 12 without the fuse 17 outside the active region 11.
b. In other respects, the flat panel image display device illustrated in FIGS. 4 and 5 is substantially the same as the flat panel image display device illustrated in FIGS. 1 and 2, and therefore, corresponding portions are denoted by common reference numerals. Detailed description is omitted. The fuse 17 of the cathode line 12 is connected to the active area 1
Since it can be formed so as not to reduce the density of the emitters 14 in the active region 1, it may be disposed in the active region 11.

FIG. 6 is a sectional view showing an embodiment of a method of manufacturing the array substrate of the flat panel image display device shown in FIGS. 4 and 5 in the order of steps. First, a cathode metal film was deposited on the glass substrate 10 and the resistance layer 13 was formed. ITO was used as the cathode metal, and the resistance layer 13 was formed of a poly-Si layer having a thickness of about 5 μm. Next, the resistor layer 13 and the cathode metal film were patterned by stepper exposure and etching to form the cathode line element 12a having the resistor layer 13 on the upper surface. Further, Ag having a rapid temperature rise was vapor-deposited and patterned to form the fuse 17 (FIG. 6A).

The cathode line element 12a has a length of 14 m.
m, width 18 μm, line element interval 2 μm. Cathode line element 12a corresponding to one pixel (100 μm square)
The number of the power supply electrodes is 12
b (width 90 μm). The fuse 17 has a length of 5
The ultrafast fuse has a width of 0 μm, a width of 2 μm, and a melting time of 0.1 msec or less.

Then, an SOG film (glass) is spin-coated on the resistance layer 13, for example.
The insulating layer 15 having a thickness of 1.8 μm was formed. Further, a Cr film as a gate metal film is vapor-deposited on the insulating layer 15 and patterned to form the gate line element 16a and the power supply electrode 1.
6b was formed (FIG. 6 (b)).

The gate line element 16a has a length of 14 m.
m, width 9 μm, line element interval 1 μm. The number of gate line elements 16a corresponding to one pixel (100 μm square) is set to nine, and the gate line elements 16a are grouped together to form a common power supply electrode 16b.
(Width 90 μm).

Next, an opening 15a having a diameter of about 1.6 μm was formed in the gate line 16 and the insulating layer 15 by etching as a window for forming an emitter by etching.
Next, a sacrificial layer is applied to the surface of the gate line element 16 and the like, and the emitter metal is deposited while rotating the sample while tilting the sample with respect to the target to form the emitter 14 inside the opening 15a (FIG. 6). (C)). Emitter 1
No. 4 had a conical shape with a height of about 1.8 μm, and Mo was used as the emitter metal. After forming the emitter 14, excess emitter metal was removed along with the sacrificial layer.

Next, a glass face plate 20 provided with a transparent electrode (anode electrode) 21 and a phosphor layer 22.
Were opposed to the glass substrate 10 at intervals of 500 μm and bonded (FIG. 5). Next, a drive circuit was attached to the cathode line power supply electrode 12b and the gate line power supply electrode 16b. In this way, one pixel is 100 μm square,
A flat image display device having an active area 11 of 13.5 mm square was completed.

In the flat panel image display device formed under such conditions, a voltage of 120V is applied between the gate and the cathode and a voltage of 350V is applied between the anode and the cathode in accordance with the pixel signal.
It was driven by applying the voltage of. As a result, it was possible to obtain a good image in which the luminance of the pixels was excellent and there was little variation in each luminance. Moreover, the occurrence of point defects and line defects on the screen was small, and the device life was greatly improved compared to conventional devices. It was also found that the quick-break fuse 17 blows before the current in the short-circuited portion is suppressed by the effect of the resistance ballast layer 13, that is, the fuse 17 operates reliably.

FIG. 7 shows the number of fuses in one pixel and the number of fuses in one pixel in a comparative example in which a fuse is arranged in the active region (in the pixel) according to the prior art and in an embodiment installed outside the active region according to the present invention. It is a graph which shows the relationship with the number of emitters which can be arranged in a pixel. In FIG. 7, lines L1 and L2 indicate the example according to the present invention and the comparative example according to the prior art, respectively.

In the case of the comparative example, emitters of 1 μm size were arranged in 1 pixel (100 μm square) at a pitch of 1 μm, and the fuse length was 10 μm to divide the emitter array into a number of sections. As shown by the line L2, when fuses are arranged in the active region (pixels), the number of emitters that can be arranged in one pixel is greatly reduced as the number of fuses is increased. The relationship is approximately α = 2500−500, where α is the number of emitters in one pixel and m is the number of fuses.
It is represented by the formula (m) ^1/2 .

On the other hand, in the case of this embodiment, one pixel (100 μ
The gate line 16 corresponding to (m square) is divided into a large number of line elements 16a at intervals of 1 μm, and the fuse 17 is arranged outside the active region 11. As shown by the line L1, in the present invention, the decrease in the number of emitters that can be arranged in one pixel is small with the increase in the number of fuses. The relationship is
When the number of emitters in one pixel is α and the number of fuses is m, it is represented by an equation of approximately α = 2500-25m.

FIG. 8 is a graph showing how the current flowing when the anode-gate is short-circuited is increased or decreased with time. This graph shows about 0.8 μA per chip
About 10 below the emitter where the emission current of
An element with a resistance ballast layer of E + 9Ω (approx. 0.1μ
A / tip) is assumed. In FIG. 8, the time when the short circuit occurs is the origin of the graph.

As shown in FIG. 8, the current flowing through the emitter rapidly increases in the initial stage, the applied voltage is absorbed by the resistance layer due to the resistance ballast effect, the current reaches a peak at 0.1 msec, and then disappears. When a conventional fuse whose fusing time is longer than the above current peak time (0.1 msec or more) is used, the fuse may not blow. In this case, the emitter in the short-circuit peripheral region may be destroyed by an overcurrent due to a temporary and rapid increase in current. From the above, it can be seen that in order for the fuse to operate reliably, the ultrafast fuse having a low operating overvoltage that is blown in about 0.1 msec which is less than the current peak time is effective.

As described above, in the planar image display device described with reference to FIGS. 1 to 8, the gate line or the cathode line corresponding to one pixel is divided into a plurality of line elements, and for each line element. , The fuse is connected outside the active area. Therefore, the density of emitters formed in the active region increases, and as the number of emitters increases,
The emission current can be increased, and higher brightness of the image can be realized.

Further, since the fuse is not blown in the active region, the secondary insulation breakdown or short circuit between the gate and the emitter due to the fragments of the fuse scattered by the blow is suppressed. Furthermore, the number of emitters formed per section increases, and a high current can be obtained. Further, the value of the current flowing through each fuse also becomes large, and the fuse is easily blown. Therefore, it becomes easy to adopt even a fuse structure that has been difficult to blow with a minute current.
Also, by using a super-fast acting fuse that operates in 0.1 msec or less for the fuse, it can be used together with the resistance ballast layer, and a uniform image without screen unevenness, line defects and point defects, and screen dielectric breakdown can be obtained. It is possible to provide a highly reliable image display device that suppresses the occurrence of noise.

FIG. 9 is a cross-sectional view showing, in the order of steps, a method of manufacturing a modification of the field emission cold cathode. The method shown in FIG.
It uses the dt method. First, a silicon dioxide (SiO ₂ ) film 52 or the like is deposited as an insulating film on the silicon substrate 51 to a thickness of about 1 μm by thermal oxidation or a CVD method. Next, a silicon (Si) film 53 and an aluminum (Al) film 54, which will be gate electrodes, are formed by sputtering, for example, 300 and 1, respectively.
It is formed to a thickness of 00 nm (FIG. 9A).

Next, the Al film 54, Si film 53 and SiO
_{2 The} film 52 is selectively etched using a resist as a mask to form a hole 55 having a diameter of about 1.5 μm (FIG. 9B).

Next, a metal such as molybdenum Mo to be the emitter 56 is vacuum-deposited. At this time, the silicon substrate 51
Is rotated, and Mo is evaporated from the vertical direction,
By utilizing the fact that the diameter of the hole 55 is closed along with the deposition of Mo, Mo is deposited in a conical shape in the hole 55 (FIG. 9C).

Then, the Al film 54 is removed by etching, and the evaporated Mo film 56a is removed to remove the conical M shape.
A field emission cold cathode having the o layer as the cold cathode emitter 56 (FE emitter) is manufactured (FIG. 9D).

Next, anodic oxidation is performed. Here, the area other than about 1 μm around the emitter is covered with a resist 57 or the like. As an electrolyte, for example, 5 in 0.01N potassium hydroxide solution
8 is used to apply a voltage only to the Si film 53 to be the gate electrode (FIG. 9E).

The thickness of the anodic oxide film 59 is determined only by the applied voltage, and a film thickness of about 50 nm can be obtained at 30V. Next, the anode electrode 60 for trapping electrons, which is insulated from the gate electrode 53 and the FE emitter 56, is separately provided (FIG. 9F).

FIG. 10 is a cross-sectional view showing a method of manufacturing another modification of the field emission cold cathode in the order of steps. FIG. 10 uses the transfer molding method. First, SiO ₂ is used as an anisotropic etching protection film 72 on a silicon (100) substrate 71 having a thickness of about 0.5 mm by a thermal oxidation method to give a thickness of about 100.
nm. Next, using the resist or the like as a mask, Si
The O ₂ film 72 is selectively etched with ammonium fluoride or the like. Then, using the remaining SiO ₂ film 72 as a mask, anisotropic etching of Si is performed by using an aqueous solution of potassium hydroxide.
A micron-sized V-shaped groove 73 is formed (FIG. 10).
(A)).

After removing the SiO ₂ film 72, thermal oxidation is performed again to form a SiO ₂ film 74 having a thickness of 0.5 μm (FIG. 10).
(B)). The tip of the V-shaped anisotropic etching groove is sharpened by the thermal oxidation. The SiO ₂ film 74 also serves as an insulating film between the emitter and the gate.

Next, molybdenum (Mo) to be the FE emitter 75 is formed to a thickness of about 3 μm by sputtering, and an Al film is formed to 0.3 μm as the adhesive layer 76 (FIG. 10C). Next, a glass substrate 77 having a thickness of 0.5 mm is attached by electrostatic adhesion, and the silicon (100) substrate 71 is removed by etching. On the contrary, the V-shaped groove is transferred to the pyramid shape by etching (FIG. 10D).

Next, an Al film to be the gate electrode 78 is formed to a thickness of 300 nm by, for example, the sputtering method (FIG. 10).
(E)). Next, a resist 79 is applied to the entire surface, and the resist is etched by CDE (Chemical-Dry-Etching) until the tip 80 of the gate metal Al film is exposed (FIG. 1).
0 (f)).

Next, using the remaining resist 79 as a mask, only the tip of the Al film is opened by etching, and SiO 2 is removed.
With respect to the _two films, only the tip 81 is opened by etching. As a result, molybdenum is exposed and becomes the FE emitter 75.
Then, the resist 79 is removed (FIG. 10G).

Next, only the Al gate electrode 78 of 3 μm around the FE emitter is selectively anodized to about 100.
Coating with a thickness of nm (FIG. 10 (h)). Anodizing is
A voltage of 50 V is applied as an electrolytic solution 83 in a 10% sulfuric acid aqueous solution, and an unnecessary region is covered with a resist 84 to selectively perform the process. Then wash with warm water.

Next, the gate electrode 78 and the FE emitter 75
Anode electrode 8 for capturing electrons, which is insulated from
5 and the like are separately arranged (FIG. 10 (i)). 9 and 10
In the illustrated field emission cold cathode, the gate electrode is covered with an anodized film which is a protective film. As a result, the nonuniformity of the electric field distribution is reduced, and the electric field applied to the gate electrode is reduced in inverse proportion to the relative dielectric constant of the anodic oxide film. Therefore, there is no discharge breakdown between the gate electrode and the FE emitter, and a highly uniform and high quality field emission type cold cathode can be provided.

That is, the electric field applied to the gate electrode is about 1/4 for the Si gate electrode and 1/8 for the Al gate electrode. For this reason, the discharge breakdown rate of the FE emitter at a gate electrode applied voltage of 100 V was as large as about 60% in the past, but according to the present invention, it is significantly reduced to 0.1%. Also,
The field emission current is also 1 pA to 1 n per cold cathode in the past.
While the distribution was large with A, according to the present invention, it was 0.
Uniform characteristics of 5 to 1 nA can be obtained. Even when the gate electrode is made of another metal such as titanium or tantalum other than Si or Al, an anodic oxide film having the same effect can be formed.

[0056]

According to the present invention, a field emission type cold cathode having a high-brightness image display function in which the occurrence of screen defects and line defects caused by electrical shorts, leaks, and dielectric breakdown is prevented. It is possible to provide a flat panel image display device using the.

[Brief description of drawings]

FIG. 1 is a plan view showing an array substrate of a flat panel image display device using a field emission cold cathode according to an embodiment of the present invention.

FIG. 2 is a sectional view of the flat panel image display device taken along line II-II in FIG.

3A to 3C are cross-sectional views showing an embodiment of a method of manufacturing an array substrate of the flat panel image display device shown in FIGS.

FIG. 4 is a plan view showing an array substrate of a flat panel image display device using a field emission cold cathode according to another embodiment of the present invention.

5 is a cross-sectional view of the flat panel image display device taken along line VV of FIG.

6A to 6C are cross-sectional views showing an embodiment of a method of manufacturing an array substrate of the flat panel image display device shown in FIGS.

FIG. 7 is a graph showing the relationship between the number of fuses in one pixel and the number of emitters that can be arranged in one pixel in the example and the comparative example.

FIG. 8 is a graph showing how the current flowing when the anode-gate is short-circuited increases or decreases with time.

FIG. 9 is a cross-sectional view showing the method of manufacturing the modified example of the field emission cold cathode in the order of steps.

FIG. 10 is a cross-sectional view showing a method of manufacturing another modification of the field emission cold cathode in the order of steps.

[Explanation of symbols]

10 ... Glass substrate, 11 ... Active area, 12 ... Cathode line, 12a ... Line element, 12b ... Feed electrode,
13 ... Resistive ballast layer, 14 ... Emitter, 15 ... Insulating layer, 16 ... Gate line, 16a ... Line element, 16b
... power feeding electrode, 17 ... fuse, 18 ... sealing member, 19
... airtight space, 20 ... glass face plate, 22 ... transparent electrode (anode electrode), 22 ... phosphor layer.

Claims (4)

[Claims] 1. A plurality of emitters arranged so that at least one corresponds to each of a plurality of pixels arranged in a matrix in an active region, and a cathode connected to the emitters belonging to each of the pixels. A line and a gate line disposed on the cathode line via an insulating film, the gate line having a portion facing the emitter belonging to each of the pixels for emitting electrons from the emitter. The field emission type cold cathode characterized in that the gate line corresponding to is composed of a plurality of line elements, and each line element is connected to a power supply electrode through an individual fuse arranged outside the active region. Image display device used. 2. A plurality of emitters arranged so that at least one corresponds to each of a plurality of pixels arranged in a matrix in an active region, and a cathode connected to the emitters belonging to each of the pixels. A line and a gate line disposed on the cathode line via an insulating film, the gate line having a portion facing the emitter belonging to each of the pixels for emitting electrons from the emitter. An image display device using a field emission type cold cathode, wherein the cathode line corresponding to is composed of a plurality of line elements, and each line element is connected to a power feeding electrode through an individual fuse. 3. The image display device using a field emission type cold cathode according to claim 2, wherein the fuse is arranged outside the active region. 4. The cathode line is connected to the emitter through a resistive ballast layer, and the fuse is a quick-acting fuse with a melting time of 0.1 msec or less. An image display device using the field emission cold cathode according to any one of 3 above.