JPH09237164A - Semiconductor disk device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten the test time of a non-volatile semiconductor memory. SOLUTION: When a test command is received by a microcontroller 12, a data generating circuit 15 is controlled to generate test data and generated data is written in a buffer memory 13. When the buffer memory 13 becomes full, a sequencer 14 is controlled to write test data in a non-voltaile semiconductor memory 19. After writing test data in the whole area of the non-voltatile semiconductor memory 19 is completed, test data is read from the non-volatile semiconductor memory 19 by the sequencer 14 and written in the buffer memory 13. When the buffer memory 13 becomes full, a reading pulse is generated by a reading circuit 17 and data is read out from the buffer memory 13. The data generating circuit 15 generates test data. A data comparing circuit executes comparison and outputs a status to the microcontroller 12.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor disk device, and more particularly to a circuit for automatically performing a test on a semiconductor disk device such as a nonvolatile semiconductor mounted therein.

[0002]

2. Description of the Related Art Conventionally, a non-volatile semiconductor disk device (P
A CMIA-ATA flash memory card or the like) is used by being connected to a host computer. Generally, when writing data to or reading data from a non-volatile disk device, the host issues a command to the non-volatile semiconductor disk device to read / write data in sector (512 byte) units. FIG. 2 is a configuration diagram of a conventional nonvolatile semiconductor disk device. As shown in FIG. 2, when the host writes data to the nonvolatile semiconductor disk device, the host first issues a command to the nonvolatile semiconductor disk device to write the data. When the non-volatile semiconductor disk device receives a command via the host interface 1, the micro-controller 2 is notified, and the micro-controller 2 sets the sequencer 4 and the buffer memory 3 in the non-volatile semiconductor disk device according to the flow of the data writing operation. Control. First, the data written from the host is temporarily stored in the buffer memory 3 through the host interface and
When the data of the sector (512 bytes) is accumulated, a signal indicating that the data is accumulated in the buffer memory is sent from the buffer memory 3 to the microcontroller 2.

The microcontroller 2 is a sequencer 4
The sequencer 4 sequentially reads the data from the buffer memory 3, converts the format according to the interface of the non-volatile semiconductor array 5, and writes the data in the non-volatile semiconductor array 5. This operation is performed in the buffer memory 3
Execute the number of times specified by the sector counter. When the host reads data from the non-volatile semiconductor disk device, the host first issues a command to the non-volatile semiconductor disk device to read the data. When the nonvolatile semiconductor disk device receives a command via the host interface 1, it is notified to the microcontroller 2, and the microcontroller 2 buffers the sequencer 4 and the sequencer in the nonvolatile semiconductor disk device according to the flow of the data read operation. The memory 3 is controlled. First, the microcontroller 2 controls the sequencer 4, and the sequencer 4 reads data of one sector from the nonvolatile semiconductor array 5 and stores it in the buffer memory 3. When one sector of data is accumulated in the buffer memory 3, the host is notified via the microcontroller 2. The host reads from the buffer memory 3 via the host interface 1. This operation is executed the number of times designated by the sector counter.

[0004]

However, the conventional nonvolatile semiconductor disk device has the following problems.
Writing to the non-volatile semiconductor 5 is 1 by one command.
Only track units or a maximum of 256 sectors (usually, the number of sectors to be transferred is specified by the value of the sector counter) can be continuously used. However, when trying to test the non-volatile semiconductor array 5 in the non-volatile semiconductor disk device, it is necessary to write and read to all storage areas, and therefore the host must issue commands many times. I have to. Therefore, it takes time to check whether all the storage areas of the non-volatile semiconductor in the non-volatile semiconductor disk device are normal in a test or the like. Also,
In order to check one non-volatile semiconductor disk, it is necessary to repeatedly send and receive commands and data, and during that time it becomes a host, so one host is required and one semiconductor disk is required. In order to compensate for the time-consuming device test, a plurality of hosts are required to test a plurality of devices in parallel, which causes a problem of cost increase.

[0005]

In order to solve the above-mentioned problems, the first invention is used by being connected to a host computer, and according to a command from the host computer,
A semiconductor disk device for writing data to a semiconductor memory device and reading data from the semiconductor memory device includes the following means. A control unit that receives a command instructing a test from the host computer and controls writing of data to the semiconductor memory device and reading of data from the semiconductor memory device; and data writing based on a write signal, a read signal A buffer memory for reading the data written based on the above, a data generating means for controlling the operation by the control means, and a data generating means for generating the test data and the collating data, and the operation for controlling the operation by the control means. Data write means for generating the write signal for writing the test data generated by the means into the buffer memory.

The operation is controlled by the control means, the read signal is generated, the test data written in the buffer memory is read, written in the semiconductor memory device, and written in the semiconductor memory device. A sequencer for reading the test data, generating the write signal and writing the write signal in the buffer memory, and the read signal for reading the data written in the buffer memory, the operation of which is controlled by the control means. Data comparison for generating data and comparing the data output by the reading unit and the data for collation output by the data generation unit, the operation of which is controlled by the control unit, and outputs the collation result. And means.

Since the semiconductor disk device is constructed as described above, when a test command is input by the control means,
By controlling the data writing means and the data writing means, test data is created and written in the buffer memory. Then, by controlling the sequencer, the data written in the buffer memory is read out and written in the semiconductor memory means. Further, the sequencer is controlled to read the data written in the semiconductor memory means and write the data in the buffer memory. The data written in the buffer memory is controlled and read by the data reading means, and the data generating means is controlled to generate the collation data. The collation data and the data read from the buffer memory are compared by the data comparison means. Compare. As a result, the semiconductor memory device can be tested in the semiconductor disk device.

[0008]

BEST MODE FOR CARRYING OUT THE INVENTION First Embodiment FIG. 1 is a configuration diagram of a non-volatile semiconductor disk device showing a first embodiment of the present invention. The non-volatile semiconductor disk device of the first embodiment is different from the conventional non-volatile semiconductor disk device in that a data generation circuit 15, a data writing circuit 16, and a data reading circuit 1 for creating data are used.
7. The data comparison circuit 18 is provided to test whether the storage area of the nonvolatile semiconductor memory 19 is normal in the nonvolatile semiconductor disk device. FIG.
As shown in FIG. 1, the nonvolatile semiconductor disk device of the first embodiment includes a host interface 11, a microcontroller 12, a buffer memory 13, a sequencer 14,
Data generating circuit (data generating means) 15, data writing circuit (data writing means) 16, data reading circuit (data reading means) 17, data comparing circuit 18
(Data comparison means), a non-volatile semiconductor memory 19, and selectors 20 and 21 are provided.

The data generation circuit 15 includes an 8-bit data register 15-1, an 8-bit counter 15-2, an 8-bit memory address register 15-3, and a selector 15.
It has -4 and 15-5. Data writing circuit 16
The 512 counter 16-1 and the write pulse generation circuit 1
6-2 and 6-2. The data read circuit 17 has 5
12 counter 17-1 and read pulse generation circuit 17-2
And The input / output of the host interface 11 includes a microcontroller 12, a buffer memory 13,
And the host is connected. The buffer memory 13 is connected to the data generation circuit 15 by a data bus DBA. The buffer memory 13 and the data comparison circuit 18 are connected by a data bus DBB. The buffer memory 13 is connected to the sequencer 14 by a data bus DBC. The input / output of the buffer memory 13 is connected to the microcontroller 12. The initial value address signal s12a from the microcontroller 12 is connected to the input of the buffer memory 13. Read / write address signal s12b from the microcontroller 12 to the nonvolatile semiconductor memory 19 and operation control signal s12b of the sequencer 14.
Are connected to the inputs of the sequencer 14.

The data value s12c from the microcontroller 12, the initial count value (0) s12d, and the memory address 12e are stored in the data register 1 of the data generation circuit 15.
5-1, counter 15-2, memory address register 1
5-3 is connected to each input. The clock selection signal s12f of the counter 15-2 from the microcontroller 12 is connected to the selection signal input of the selector 15-4. The data output selection signal s12g of the data generation circuit 15 from the microcontroller 12 is connected to the selection signal input of the selector 15-5. The count start signal s12h from the microcontroller 12 is connected to the input of the 512 counter 16-1 of the data write circuit 16. The count start signal s12i from the microcontroller 12 is connected to the input of the 512 counter 17-1 of the data read circuit 17.

The write signal selection signal s12j from the microcontroller 12 is connected to the selection signal input of the selector 20. The read pulse selection signal s12k from the microcontroller 12 is connected to the selection signal input of the selector 21. The data comparison timing signal s12l from the microcontroller 12 is connected to the input of the data comparison circuit 18. The write signal s14R from the sequencer 14 is connected to one input of the selector 20. Read signal s14 from the sequencer 14
W is connected to the other input of the selector 21. The sequencer 14 and the non-volatile semiconductor memory 19 are connected by a data signal line. Data generation circuit 1
The output of the data register 15-1 of No. 5 is the selector 15-
5 inputs. The output of the counter 15-2 is connected to the input of the selector 15-5. The output of the memory address register 15-3 is the selector 15-5.
Connected to the input. The output of the selector 15-4 is
It is connected to the clock terminal of the counter 15-2.

Counter 16 of data write circuit 16
The clock signal CLK is connected to the first clock terminal. The output of the counter 16-1 is connected to one input of the write pulse generation circuit 16-2. The other input of the write pulse generation circuit 16-2 receives the clock signal CLK.
Is connected. The write signal s16 of the write pulse generation circuit 16-2 is the same as the selector 20 and the data generation circuit 1
5 selector 15-4. The clock signal CLK is connected to the clock terminal of the counter 17-1 of the data reading circuit 17. Counter 17-
The output of 1 is connected to one input of the read pulse generation circuit 17-2. The clock signal CLK is connected to the other input of the read pulse generation circuit 17-2.
The write signal s17 of the read pulse generation circuit 17-2 is
The selector 21 and the selector 15 of the data generation circuit 15-
4 inputs.

Status of the data comparison circuit 18 stat
us is connected to the input of the microcontroller 12. The output of the selector 20 is connected to the write signal input of the buffer memory 13. The output of the selector 21 is connected to the read signal input of the buffer memory 13. The host interface 11 is, for example, an ATA interface circuit. Microcontroller 12
Is for controlling the operations of the sequencer 14, the data generating circuit 15, the data writing circuit 16, the data reading circuit 17, the data comparing circuit 18, and the selectors 20 and 21. The buffer memory 13 is, for example, 512 bytes of S
This is a RAM, in which an address is generated by an address counter according to a write signal or a read signal, data is loaded into an address indicated by the address counter according to the write signal or a read signal, and data is read from the address indicated by the address counter.

The sequencer 14 generates a read signal s14R, reads data from the buffer memory 13,
A circuit that performs format conversion (for example, parallel / serial conversion) of the data and writes the data in the nonvolatile semiconductor memory 19, and data is read from the nonvolatile semiconductor memory 19 and subjected to format conversion (for example, serial / parallel conversion). , The write signal s14W and writes it in the buffer memory 13, and is a logic circuit whose operation is controlled by the microcontroller 12. The data generation circuit 15 is a circuit that generates test data, and the microcontroller 12
The timing for generating data and the type of data to be generated are controlled. For example, test data of any one of three types of fixed value, counter value, and memory address is generated.

The data write circuit 16 writes test data in the buffer memory 13 and the data generation circuit 1
5 is a circuit for generating the clock of the counter 15-2. The data read circuit 17 includes the buffer memory 1
3 is a circuit for reading data from 3 and generating a clock for the counter 15-2 of the data generation circuit 15. The data comparison circuit 18 compares the data read from the buffer memory 13 and the output from the data generation circuit 15 with each other.
Comparison timing signal s from the microcontroller 12
A circuit for comparing and outputting the status status according to 12l.

FIG. 3 is a time chart of FIG. Hereinafter, the operation of FIG. 1 will be described with reference to FIG. (A) When testing the non-volatile semiconductor memory 19 When the host tests the non-volatile semiconductor in the non-volatile semiconductor disk device, the host first commands the non-volatile semiconductor disk device to test the non-volatile semiconductor. Give out. The nonvolatile semiconductor disk device includes a microcontroller 12 via a host interface 11.
Will be notified. When the microcontroller 12 analyzes the command and recognizes that it is a non-volatile semiconductor test, the fixed value data s12 is stored in the data register 15-1.
c, the count initial value (0) s12d is output to the counter 22, or the address s12e for writing the test data generated here into the nonvolatile semiconductor memory 19 is output to the memory address register 15-3. Further, the microcontroller 12 outputs the initial value (0) s12a of the address to the address counter of the buffer memory 13 at the same time as outputting the initial value (0) s12d of the count.

Then, the microcontroller 12 inputs the data write circuit 1 to the selection signal input of the selector 15-4.
6 outputs the clock selection signal s12f so as to select the output s16, and outputs the data register 15-1 and the counter 15-2 to the selection input of the sector 15-5.
A selection signal s12g that selects one of the outputs of the memory address register 15-3 is output. Further, the microcontroller 12 outputs the count start instruction signal s12h to the 512 counter 16-1, and outputs the selection signal s12j to the selection signal input of the selector 20 so as to select the output s16 of the data writing circuit 16. The 512 counter 16-1 is instructed to the count start signal s12h,
Start counting the clock signal CLK, and
Until "1" is counted, after that,
Output "0". The write pulse generation circuit 16-2 is
While the output of the counter 16-1 is "1", the clock signal CLK is output as the write signal s16.

The write signal s16 is supplied to the data generation circuit 15
It is output to the inputs of the selector 15-4 and the selector 20. The selector 15-4 outputs the write signal s16 to the clock terminal of the counter 15-2 in response to the clock selection signal s12f. The counter 15-2 has a write signal s1.
The counter initial value (0) from the microcontroller 12 is loaded using 6 as a clock signal, and 0, 1, 2,
,, 255, 0, ... are sequentially counted and the selector 15-
5 is output. The sector 15-5 is a data register 1
The output of 5-1 and the output of the counter 15-2 and the output of the memory address register 15-3 are selected according to the selection signal s12g and output to the data bus DBA. On the other hand, the selector 20 selects the output s16 of the data writing circuit 16 by the selection signal s12j and outputs it. The address counter of the buffer memory 13 is the microcontroller 1
Load the address initial value (0) s12a from 2,
An address is generated using the write signal as a clock. Then, the buffer 13 inputs and writes the output of the data generation circuit 15 from the data bus DBA in accordance with the write signal at the address indicated by the address counter.

For example, assuming that the output from the data generating circuit 15 is the output of the counter 15-2, the counter 15-2 and the address counter use the same write pulse as the clock, and therefore the output of the counter 15-2. (0, 1, ..., 255, 0, ...) Are written at the addresses (0, 1, ..., 255, 256, ...) In the buffer memory. When one sector (512 bytes) of data is accumulated in the buffer memory 13,
The address counter notifies the microcontroller 12. The microcontroller 12 has a buffer memory 13
Upon receiving the notification from the non-volatile semiconductor memory 19, the read circuit for the buffer memory 13 and the write circuit for the non-volatile semiconductor memory 19 of the sequencer 14 are activated.
Set the write address to the address register.

The sequencer 14 reads the read signal s14R.
Are sequentially generated, data is sequentially read from the buffer memory 13, and format conversion (for example, parallel / serial conversion) is performed according to an interface with the nonvolatile semiconductor memory 19 to generate the nonvolatile semiconductor memory 19
I will write it in. When one sector of data is written in the nonvolatile semiconductor memory 19, the sequencer 19
Informs the microcontroller 12. The microcontroller 12 controls the next sector of test data to be written in the nonvolatile memory 19 in the same manner as described above. The above operation is performed in the entire storage area of the non-volatile semiconductor memory 19 or in the semiconductor area in the range designated by the host.

When the above write operation is completed, the microcontroller 12 causes the sequencer 14 to read the nonvolatile semiconductor memory 19 and the buffer memory 13.
Write instruction s12b and read address s1
2b is set in the address register, and the buffer memory 13
An initial value (0) s12a is output to the address counter and a selection signal s12k is output to the selector 21 so as to select the write signal s14W from the sequencer 14. Sequencer 1
4 is 1 sector (512 bytes) from the nonvolatile semiconductor memory 19.
(Byte) data is read, write signal s14W is sequentially generated, the data is output to data bus DBC, and write signal s14W is output to selector 21. Selector 2
1 selects the write signal s14W from the sequencer 14 by the selection signal s12k and outputs it to the write signal input of the buffer memory 13. The address counter of the buffer memory 13 loads the initial value (0) from the microcontroller 12 and generates an address by using the write signal s14W as a clock signal.
According to the write signal s14W, the output of the sequencer 14 is input from the data bus DBC and writing is performed at the address indicated by the address counter.

When one sector (512 bytes) of data is accumulated in the buffer memory 13, the address counter notifies the microcontroller 12 of it. Upon receiving the notification, the microcontroller 12 receives the data generation circuit 1
5, the fixed value data s12c when the test data is generated in the data register 15-1 of 5, the initial value (0) s12d of the counter in the counter 15-2, or the memory address s16e in the memory address register 15-3.
Further, the microcontroller 12 outputs the initial value (0) of the address to the address counter of the buffer memory 13 simultaneously with the output of the initial value (0) s12d of the counter,
The selection signal s12f is inputted to the selection signal input of the selector 15-4 so that the output s17 of the data reading circuit 17 is selected.
To output 512 counter 1 of the data read circuit 17
The count start signal s12i is output to 7-1, and the selection signal s12k is output to the selector 21 so as to select the output s17 of the data read circuit 17.

The counter 17-1 has a count start signal s.
According to 12i, the count operation of the clock signal CLK is started, and “1” is output during 1 to 512 which is the read period of one sector, and “0” is output thereafter. The read pulse generation circuit 17-2 uses the counter 1
While the output of 7-1 is "1", the clock CLK is output as the read signal s17. The read signal s17 is output to the selector 15-4 and the selector 21. Selector 1
5-4 receives the read signal s17 according to the selection signal s12f.
Is output to the clock terminal of the counter 15-2. The counter 15-2 loads the initial value (0) s12d from the microcontroller 12 to read the read signal s.
When 17 is used as a clock signal, counting operation is performed, and 0,
1, 2, ..., 255, 0 ,. The selector 15-4 includes a data register 15-1 and a counter 15-.
2. Either of the memory address registers 15-3 is selected according to the selection signal s12g and output to the data bus DBA.

On the other hand, the selector 21 selects the selection signal s12k.
Thus, the write signal s17 is selected and output to the read signal input of the buffer memory 13. Buffer memory 13
The address counter loads the initial value (0) s12a, generates an address using the read signal s17 as a clock signal, and the buffer memory 13 extracts the data from the address indicated by the address counter according to the read signal s17, Output to bus DBB. If the nonvolatile semiconductor memory 19 is normal and the output of the counter 15-2 is stored as test data, 0, 1, 2, ..., 255, 0, ... Are stored in the buffer memory 13. This is output according to the read signal s17. Microcontroller 12
Outputs to the data comparison circuit 18 a signal s12l instructing the timing of data comparison. Data comparison circuit 18
Is output from the data generation circuit 15 and the buffer memory 13 according to the signal s12l from the microcontroller 12.
And outputs the status signal "status" to the microcontroller 12.

For example, if the output of the counter 15-2 is selected, the input from the data generation circuit 15 of the data comparison circuit 18 is synchronized with the read signal s17.
0, 1, 2, 3, ..., 255, 0, and if the nonvolatile semiconductor memory 19 is normal, the input from the buffer memory 13 is 0, 1, in synchronization with the read signal s17.
2, ..., 255, 0, ..
By comparing the above data with a signal synchronized to
It is possible to determine whether the nonvolatile semiconductor memory 19 is normal or abnormal.
Also, when another data register 15-1 and memory address register 15-2 are selected, during one sector,
Since the values set by the microcontroller 12 are the same, it is possible to determine whether the nonvolatile semiconductor memory 19 is normal or abnormal. If there is an abnormality, the microcontroller 12
Notifies the host via the host interface 11. When the verification of the test data of one sector is completed, the microcontroller 12 controls as described above in order to verify the test data of the next one sector. The above operation is executed the number of times writing has been performed to all the non-volatile semiconductor memories 19 or the semiconductor memories 19 in the designated range.

(B) Normal Operation In normal operation, the microcontroller 12 inputs the write signal s1 from the sequencer 14 to the selection input of the selector 20.
The selection signal s12j is output so as to select 4W, and the read signal s from the sequencer 14 is input to the selection input of the selector 21.
The selection signal s12k is output so as to select 14R.
When the command is received via the host interface 11, the microcontroller 12 is notified, and the microcontroller 12 controls the sequencer 14 and the buffer memory 13 in the nonvolatile semiconductor disk device according to the flow of the data writing operation. First, the data written from the host is temporarily stored in the buffer memory 13 through the host interface 11, and when one sector (512 bytes) of data is accumulated, the data is written from the buffer memory 13 to the microcontroller 12 to the buffer memory 13. A signal is sent indicating that has accumulated.

The microcontroller 12 controls the sequencer 14, and the sequencer 14 reads the read signal s14.
The R is output to the buffer memory 13 through the selector 20, the write data is sequentially read from the buffer memory 13, the format is converted according to the interface of the nonvolatile semiconductor memory 19, and the nonvolatile semiconductor memory 19 is converted.
Write to. This operation is executed the number of times designated by the sector counter of the buffer memory 13. When the host reads data from the non-volatile semiconductor disk device, the host first issues a command to the non-volatile semiconductor disk device to read the data. When the nonvolatile semiconductor disk device receives a command via the host interface 11, it is notified to the microcontroller 12, and the microcontroller 12 buffers the sequencer 14 and the sequencer in the nonvolatile semiconductor disk device according to the flow of the data read operation. The memory 13 is controlled. First, the microcontroller 12 controls the sequencer 14, and the sequencer 14 reads the data of one sector from the non-volatile semiconductor memory 5, generates the write signal s14R, outputs it to the buffer memory 13 through the selector 21, and outputs it to the buffer memory 13. Write the data to 13. When one sector of data is accumulated in the buffer memory 13, the host is notified via the microcontroller 12. The host reads from the buffer memory 13 via the host interface 11. This operation is executed the number of times designated by the sector counter.

As described above, according to the first embodiment, the data generating circuit 15 and the data writing circuit 16 are provided.
Since it is provided, it is not necessary to transfer the data to be written to the nonvolatile semiconductor memory 19 from the host, and the data read circuit 17 and the data comparison circuit 18 are provided, so that it is not necessary to transfer the read data to the host. The advantage is that the transfer time with the host is shortened, there is no fear of data corruption due to noise during transfer, and the nonvolatile semiconductor memory 19 can be tested quickly and accurately. Further, it becomes possible to test all the non-volatile semiconductor memories 19 in the non-volatile semiconductor disk with one command, the number of times the command is issued is reduced, and the test can be further speeded up.

Second Embodiment FIG. 4 is a configuration diagram of a non-volatile semiconductor disk device showing a second embodiment of the present invention. Elements common to those in FIG. 1 are designated by common reference numerals. There is. The non-volatile semiconductor disk device of the second embodiment is different from the non-volatile semiconductor disk device of the first embodiment in that the output of the data generation circuit 15 for writing to the non-volatile semiconductor memory 19 is stored in the buffer memory 13. Directly output to the sequencer 44 without outputting, and from the nonvolatile semiconductor memory 19 to the sequencer 1
This means that the data read in step 4 is output directly to the data comparison circuit 18 instead of being written to the buffer memory 13. As shown in FIG. 4, the nonvolatile semiconductor disk device according to the second embodiment includes a host interface 11, a microcontroller 22, a buffer memory 13, a sequencer 14, a data generation circuit 15, a data comparison circuit 18, and a nonvolatile semiconductor memory. 19, a bus selector 25, and selectors 26 and 27. The input / output of the host interface 11 is the microcontroller 22,
The buffer memory 13 and the host are connected. The buffer memory 13 and the bus selector 25 are connected by a data bus DBC. Bus selector 25
And the sequencer and data comparison circuit 18 are connected by a data bus DBB. Bus selector 25
Between the data generation circuit 15 and the data comparison circuit 18,
It is connected by a data bus DBC. The input / output of the buffer memory 13 is connected to the microcontroller 22.

The initial value address signal s22a from the microcontroller 22 is connected to the input of the buffer memory 13. Read / write address signal s22b from the microcontroller 22 to the nonvolatile semiconductor memory 19 and operation control signal s22b of the sequencer 14.
Are connected to the inputs of the sequencer 14. The data value s22c, the initial count value (0) s22d, and the memory address 22e from the microcontroller 22 are stored in the data register 15-1 and the counter 15 of the data generation circuit 15.
-2, and are connected to the inputs of the memory address register 15-3, respectively. The clock selection signal s22f of the counter 15-2 from the microcontroller 22 is connected to the selection signal input of the selector 15-4. The data output selection signal s22g of the data generation circuit 15 from the microcontroller 12 is connected to the selection signal input of the selector 15-5.

The bus selection signal s22h from the microcontroller 22 and the selection signal input of the bus selector 25 are connected. The selection signal s22i of the output destination of the read signal s14R from the microcontroller 22 is the selector 2
6 selection signal inputs. The selection signal s22i at the output destination of the write signal s14W from the microcontroller 22 is connected to the selection signal input of the selector 27. The read signal s14R of the sequencer 14 is connected to the input of the selector 26. The write signal s14W of the sequencer 14 is connected to the input of the selector 27. One output of the selector 26 is the buffer memory 13
Of the selector 15-4, and the other output is connected to the input of the selector 15-4. One output of the selector 27 is connected to the write signal input of the buffer memory 13, and the other output is connected to the input of the selector 15-4. The data comparison timing signal of the sequencer 14 is connected to the input of the data comparison circuit 18.

FIG. 5 is a time chart of FIG. The operation of FIG. 4 will be described below with reference to FIG. (A) When testing a non-volatile semiconductor When the host tests the non-volatile semiconductor in the non-volatile semiconductor disk device, the host first issues a command to the non-volatile semiconductor disk device to instruct the non-volatile semiconductor test. . The nonvolatile semiconductor disk device includes a microcontroller 22 via the host interface 11.
Will be notified. When the microcontroller 22 analyzes the command and recognizes that the test is a nonvolatile semiconductor test, the microcontroller 22 initializes the buffer memory address to be written in the buffer memory for the buffer memory 13. The microcontroller 22 outputs to the data generation circuit 15 any one of the data value s22c, the initial value (0) s22d of the counter, and the memory address value s22e. The microcontroller 22 sets an instruction 22b for reading data and a memory address 22b to the sequencer 14, and the read signal s14 is input to the selection input of the selector 15-4.
A selection signal s22f is output to select R.

The data register 15-is provided in the selector 15-5.
1, counter 15-2, memory address register 15-
The selection signal s22g is output so as to select any one of the outputs of 3 and 3. The sequencer 14 is the microcontroller 2
When the data reading is instructed from 2, the read signal 1
4R is sequentially generated and output (the sequencer 14 does not distinguish between reading from the buffer memory 13 and reading from the data generating circuit 15). The selector 26 selects the output destination of the read signal s14R and outputs the read signal s14R to the selector 15-4. The selector 15-4 is
The read signal s14R is selected by the selection signal s22f and output to the clock terminal of the counter 14 as a clock signal. The counter 14 loads the initial value (0) s22d, counts the read signal s14R as a clock signal, and sequentially outputs 0, 1, 2, ..., 255, 0, 1 ... The selector 15-5 is the data register 1
5-1, counter 15-2, memory address register 1
One of the outputs of 5-3 is selected by the selection signal s22g and output to the data bus DBA. The bus selector 25 selects the data bus DBA by the selection signal s22h and outputs it to the data of the sequencer 14.

As a result, if the output of the counter 15-2 is selected and designated, the read signal s14R is sequentially selected.
Just like reading from the buffer memory 13, 0, 1,
2, ..., 255, 0, ..., 255 are input to the sequencer 14. When the sequencer 14 receives the data, the sequencer converts the format and sequentially writes the data to the nonvolatile semiconductor memory 19 in the memory address area designated by the microcontroller 22. When the writing of the test data of one sector to the nonvolatile semiconductor memory 19 is completed, the sequencer 14 notifies the microcontroller 22. The microcontroller 22 controls to write the next test data of one sector into the nonvolatile semiconductor memory 19 in the same manner as described above. The above operation is written to the entire storage area of the non-volatile semiconductor memory 19 or the semiconductor area of the specified range.

When the write operation is completed, the microcontroller 22 instructs the sequencer 14 to read the nonvolatile semiconductor memory 19 and the data comparison circuit 18.
Set the output and read address to the address register. The sequencer 14 reads out the data from the nonvolatile semiconductor memory 19 according to the address set in the address register, and outputs the data to the data bus DBC.
The write signal s14W is generated and output in exactly the same manner as when the write signal s14W is written in the buffer memory 13. The microcontroller 22 uses the data generation circuit 1
5, the fixed value data s22c when the test data is generated in the data register 15-1 of 5, the initial value (0) s22d of the counter in the counter 15-2, or the memory address s22e in the memory address register 15-3. In addition, the microcontroller 22 includes the selector 15
-4, a selection signal s22f for selecting the write signal s14W is output to the selection signal input, and the data register 15-1, when the test data is created in the selector 15-5,
The selection signal s22g is output to select either the output of the counter 15-2 or the memory address register 15-3, and the selection signal s22j is output to the selector 27 so that the output destination is the selector 15-4.

The selector 27 selects the selector 15-4 as the output destination by the selection signal s22j, and the selector 15-
Then, the write signal s14W is output to No. 4. Selector 15-4
Selects the write signal s14W by the selection signal s22f and outputs it to the clock terminal of the counter 15-2. The counter 15-2 loads the initial value (0) s22d and outputs the write signal s14 output from the selector 15-4.
Counting is started using W as a clock signal. The selector 15-5 selects one of the outputs of the data register 15-1, the counter 15-2, and the memory address register 15-3 by the selection signal s22g and outputs it to the bus selector 25. The bus selector 25 selects the output of the data generation circuit 15 by the selection signal s22h and outputs it to the data comparison circuit 18 through the data bus DBA. The data comparison circuit 18 collates the data output from the sequencer 14 with the data output from the data generation circuit 15 in accordance with the comparison timing signal from the sequencer 14 and sets the status to the microcontroller 2
Output to 2.

For example, if the output of the counter 14-2 is selected, the input from the data generation circuit 15 of the data comparison circuit 18 is synchronized with the write signal s14W,
0, 1, 2, 3, ..., 255, 0, and if the nonvolatile semiconductor memory 19 is normal, the input from the sequencer 14 is 0, 1, 2 ,, in synchronization with the write signal s14W.
, 255, 0, and so on, the normality / abnormality of the non-volatile semiconductor memory 19 can be determined by controlling the timing of comparison by the sequencer and comparing the above data with a signal synchronized with the write signal s14W. In addition, other data register 12-1, memory address register 1
Even when 2-2 is selected, since the value set by the microcontroller 12 is held during one sector, it is possible to determine whether the nonvolatile semiconductor memory 19 is normal or abnormal. If there is an abnormality, the microcontroller 12
Notifies the host via the host interface 11. When the write signal for the test data of one sector is output, the sequencer 14 notifies the microcontroller 22. The microcontroller 22 controls in the same manner as described above in order to collate the test data of the next one sector. This operation is executed the number of times writing is performed to all the nonvolatile semiconductor memories 19 or semiconductor memories in the designated range.

(B) In case of normal operation In the case of normal operation, the microcontroller 22 instructs the selection signal s22h of the bus selector 25 to select the data bus DBC, and the output destination of the selector 26 is the buffer memory 13. And outputs a selection signal s22i for instructing to output the selector 27 to the buffer memory 13. After that, the same operation as in the normal operation of the first embodiment is performed.
As described above, according to the second embodiment, the configuration is such that the data generation circuit 15 that generates test data and the output of the data generation circuit 15 are directly written to the non-volatile semiconductor memory 19. It is not necessary to transfer data to be written to the semiconductor memory 19 from the host, and it is not necessary to store data in the buffer memory 13. Further, since the data comparison circuit 18 for comparing the data during reading from the non-volatile semiconductor memory 19 is provided, it is not necessary to transfer the data read from the non-volatile semiconductor memory 19 to the host, and the data is further transferred to the buffer memory 13. Need not be stored. Therefore, the transfer time with the host is shortened, there is no fear of data conversion due to noise at the time of transfer, and the time for storing data in the buffer memory 13 is shortened, so that the nonvolatile semiconductor memory 19 can be tested. It has the advantage of being fast and accurate.

The present invention is not limited to the above embodiment, and various modifications can be made. For example, there are the following modifications. (1) In the first embodiment, the data generation circuit 15, the write circuit 16, the read circuit 17, and the data comparison circuit 18
The data generating circuit 15 and the writing circuit 16 are provided.
Alternatively, it is possible to add only either the read circuit 17 or the data comparison circuit 18. In this case, the buffer memory 13 is read from the nonvolatile semiconductor memory 19.
The micro controller 12 executes the generation of the test data and the data stored in the test data, the comparison between the test data and the test data, and the test data generation and the storage in the buffer memory 13. Although the execution speed is inferior to the case where a dedicated circuit for comparison is provided as in the first embodiment, the hardware scale of the nonvolatile semiconductor disk device can be reduced by the amount corresponding to the read circuit 17 and the data comparison circuit 18. it can. (2) It is also possible to combine the first and second embodiments. That is, the configuration until the test data generated by the data generation circuit 15 is written in the nonvolatile semiconductor 19 is
The same configuration as that of the first or second embodiment, the configuration of reading from the non-volatile semiconductor memory 19 and comparing by the data comparing means 19 is the same as that of the second or first embodiment.

(3) In the present embodiment, the configuration in which one non-volatile semiconductor disk device is connected to the host has been described, but unlike the prior art, one non-volatile semiconductor disk device is connected to one host. Therefore, it is possible to test at the same time. At this time, the host may issue a test command to the nonvolatile semiconductor disk device. In this case, each non-volatile semiconductor disk device independently tests the non-volatile semiconductor memory. (4) The data generation circuit 15 has a fixed value, a counter value,
Although the case of generating three types of address value data has been described, other data (eg, PN code) may be generated.

[0041]

As described in detail above, the first to eighth embodiments
According to the invention, since the semiconductor memory device can be tested in the semiconductor disk device, the semiconductor memory device test can be completed early. Further, there is a possibility that an error may occur in the test due to noise during data transfer to the host, but this is eliminated, and the reliability of the test is improved.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a nonvolatile semiconductor disk device according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram of a conventional nonvolatile semiconductor disk device.

FIG. 3 is a time chart of FIG. 1;

FIG. 4 is a configuration diagram of a nonvolatile semiconductor disk device according to a second embodiment of the present invention.

FIG. 5 is a time chart of FIG. 4;

[Explanation of symbols]

11 Host Interface 12, 22 Microcontroller 13 Buffer Memory 14 Sequencer 15 Data Generation Circuit 16 Data Writing Circuit 17 Data Reading Circuit 18 Data Comparison Circuit 19 Nonvolatile Semiconductor Memory 21, 22, 26, 27 Selector 25 Bus Selector

Claims (8)

[Claims] 1. A semiconductor disk device which is used by being connected to a host computer and which writes data to a semiconductor memory device and reads data from the semiconductor memory device according to a command from the host computer. Control means for receiving a command instructing a test and controlling writing of data to the semiconductor memory device and reading of data from the semiconductor memory device, and data writing based on a write signal and writing based on a read signal And a buffer memory for reading the data, an operation of which is controlled by the control unit, and a collation for collating the test data written to the semiconductor memory device with the test data written to the semiconductor memory device. Data generating means for generating data, and Operation is controlled by the control means, the data writing means for generating the write signal for writing the test data generated by the data generating means in the buffer memory, and the operation is controlled by the control means, the read signal To read the test data written in the buffer memory and write it in the semiconductor memory device,
A sequencer that reads the test data written in the semiconductor memory device, generates the write signal, and outputs the read data to the buffer memory based on the write signal, and an operation performed by the control unit. Data read means for generating the read signal for controlling and reading the data written in the buffer memory; data output from the buffer memory and output by the data generation means, the operation of which is controlled by the control means And a data comparison means for outputting a result of the collation. 2. The selection means for selecting either the write signal generated by the data writing means or the read signal generated by the data reading means under the control of the control means. 2. The semiconductor disk device according to claim 1, further comprising a counter that operates based on an output signal of the selecting means. 3. A semiconductor disk device which is used by being connected to a host computer and which writes data to a semiconductor memory device and reads data from the semiconductor memory device according to a command from the host computer. A control unit that receives a command instructing a test and controls writing of data to the semiconductor memory device and reading of data from the semiconductor memory device, and operation of the control unit to control and write to the semiconductor memory device Data for generating a collation data for collating the test data and the test data written in the semiconductor memory device, and the operation is controlled by the control unit to generate a read signal. And generated by the data generating means based on the read signal Input test data, write it in the semiconductor memory device, read the test data written in the semiconductor memory device, generate a write signal, and output the read data based on the write signal And a data comparison unit that controls the operation by the control unit or the sequencer, collates data output by the sequencer with collation data output by the data generation unit, and outputs a collation result. A semiconductor disk device comprising: 4. The data generation means includes a selection means for selecting either the read signal or the write signal under the control of the control means, and a counter which operates based on an output signal of the selection means. The semiconductor disk device according to claim 3, further comprising: 5. A semiconductor disk device which is used by being connected to a host computer and which writes data to a semiconductor memory device and reads data from the semiconductor memory device according to a command from the host computer. Control means for receiving a command instructing a test and controlling writing of data to the semiconductor memory device and reading of data from the semiconductor memory device, and data writing based on a write signal and writing based on a read signal A buffer memory for reading the data, and a collation for collating the test data written in the semiconductor memory device with the test data whose operation is controlled by the control means and the semiconductor memory device. Data generation means for generating the data of An operation is controlled by the control means, a data writing means for generating the write signal for writing the test data generated by the data generating means into the buffer memory; and an operation controlled by the control means, the read signal To read the test data written in the buffer memory and write it in the semiconductor memory device,
A sequencer that reads the test data written in the semiconductor memory device, generates a write signal, and outputs the read data based on the write signal, and the operation is controlled by the control unit or the sequencer, A semiconductor disk device comprising: a data comparison unit that collates the data output by the sequencer with the collation data output by the data generation unit and outputs a collation result. 6. A semiconductor disk device which is used by being connected to a host computer and which writes data to a semiconductor memory device and reads data from the semiconductor memory device according to a command from the host computer. Control means for receiving a command instructing a test and controlling writing of data to the semiconductor memory device and reading of data from the semiconductor memory device, and data writing based on a write signal and writing based on a read signal A buffer memory for reading the data, and a collation for collating the test data written in the semiconductor memory device with the test data whose operation is controlled by the control means and the semiconductor memory device. Data generation means for generating the data of The operation is controlled by the control means, the input control signal is generated, the test data generated by the data generation means is input based on the input control signal, and the test data is written into the semiconductor memory device and written in the semiconductor memory device. A sequencer for reading the written test data, generating the write signal and writing the write signal in the buffer memory, and the read for reading the data written in the buffer memory, the operation of which is controlled by the control means. A data reading unit that generates a signal and an operation of which is controlled by the control unit, collates the data output from the buffer memory with the collation data output by the data generation unit, and outputs a collation result. A semiconductor disk device comprising: a data comparison unit. 7. The semiconductor disk device according to claim 1, wherein the control means and the data generation means are constituted by a microcontroller. 8. The control means and the comparison means are constituted by a microcontroller.
The semiconductor disk device described in 2, 3, 4, 5 or 6.