JPH09229823A - Peak detector for detecting knocking, knock detecting circuit and resetting circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a peak detector using an A-D converter by reducing the gain of an input signal when the output value of the converter exceeds a predetermined value in a dynamic range. SOLUTION: A 8-bit A-D converter 4 converts an input analog signal into a digital signal. When the output signal value is the value F0 or less which is slightly lower than the dynamic range upper limit value of the converter 4, a switch 3 is controlled in response to the output of a comparator 5, and the signals amplified by amplifiers 1, 2 from the analog signal are supplied to the converter 4. When the output signal value becomes the value F0 or more, the comparator 5 outputs a gain switching signal, the switch 3 is changed over, and only the analog signal amplified by the amplifier 1 is input to the converter 4. Thus, when the output value of the converter 4 tends to exceed the dynamic range, the gain of the input signal is reduced to always input the signal of the dynamic range to the converter 4. Accordingly, the converter 4 always normally operates, and a peak detector using it is obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a knock detection peak detection circuit, a knock determination circuit and a reset circuit in a knock control circuit for detecting knocking of an internal combustion engine such as a vehicle.

[0002]

2. Description of the Related Art FIG. 11 is a block diagram showing a knock control device described in "Electronic Controlled Gasoline Injection" (written by Hideya Fujisawa and Hisanori Kobayashi, published by Sankaido Co., Ltd. on July 5, 1987). . In the figure, a knock sensor 111 attached to a cylinder block or the like of an internal combustion engine detects a vibration of the internal combustion engine and outputs a vibration waveform signal thereof to an electronic control unit (EC
U) 112 is applied to the filter circuit 113. The filter circuit 113 extracts a signal of, for example, 5 kHz to 10 kHz from the vibration waveform signal, and gives a bias voltage as the center voltage of the extracted signal. The peak detection circuit 114 includes a sample hold circuit that detects and holds the peak value from the output signal of the filter circuit 113. The comparison reference level calculation circuit 115 calculates a comparison reference level serving as a threshold for knock determination based on the output signal of the filter circuit 113. The knock determination circuit 116 outputs a knock signal to the microcomputer 1 when the peak value from the peak value detection circuit 114 is higher than the comparison reference level.
Give 17 The microcomputer 117 performs feedback control that retards the ignition timing when the knock signal is input while the knock determination section signal is on, and gradually advances the ignition timing when there is no knocking.

FIG. 12 is a circuit diagram showing a conventional peak detection circuit. In the figure, the knock sensor 111 and the filter circuit 113 are the same as those shown in FIG. The output of the filter circuit 113 is input to the peak detection circuit 121. As shown, the conventional peak detection circuit 121 is an analog peak hold circuit, and includes an operational amplifier 122, a transistor 123, and a capacitor 124. The peak value is obtained by accumulating charge in the capacitor 124.

[0004]

The conventional peak value detection circuit requires the capacitor 124 as shown in FIG. However, in order to hold the peak value with accuracy even after several milliseconds, a large capacity capacitor is required. For this reason, the capacitor becomes large in size, and there is a problem that it is difficult to increase the density of the electronic control unit 112 and make it into an IC.

Further, in order to improve the frequency response to a signal having an oscillation frequency of several kilohertz of the internal combustion engine and reduce the leakage current, it is necessary to use a film capacitor, but the film capacitor is not suitable for a high temperature environment. Since it is suitable and has a large size, the electronic control unit 11 is also required.
2 has a problem that it is difficult to achieve high density and IC.

In view of the above problems in the prior art, it is an object of the present invention to utilize that a knock signal is a signal close to a sine wave at a substantially constant frequency, and each part thereof is a signal close to a linear signal that smoothly changes. By realizing a peak detection circuit using an A / D converter, it is possible to increase the density and IC of an electronic control device including a peak detection circuit for knocking detection.

[0007]

In order to achieve the above object, according to the first aspect of the present invention, the output value of the A / D converter is a predetermined value within the dynamic range of the A / D converter. A peak detection circuit for knocking detection is provided in which the gain of the signal input to the A / D converter is reduced when the value exceeds the limit and the output of the A / D converter is input to the microcomputer.

According to the second aspect of the present invention, when the input level of the A / D converter exceeds a predetermined value within the dynamic range of the A / D converter, it is input to the A / D converter. A peak detection circuit for knocking detection is provided in which the gain of a signal is reduced and the output of an A / D converter is input to a microcomputer. According to a third aspect of the present invention, in addition to the first aspect, when it is determined that the output value of the A / D converter exceeds a predetermined value within the dynamic range of the A / D converter, A / D A peak detection circuit for knocking detection is further provided, which further comprises a bit shift circuit for shifting the output of the D converter by n bits and inputs the output of the bit shift circuit to a microcomputer.

According to a fourth aspect of the present invention, in addition to the second aspect, when it is determined that the input level of the A / D converter exceeds a predetermined value within the dynamic range of the A / D converter. , A peak detection circuit for knocking detection further comprising a bit shift circuit for shifting the output of the A / D converter by n bits and inputting the output of the bit shift circuit to a microcomputer.

According to the fifth aspect of the present invention, when the knock determination section signal is off, the offset A / D conversion value obtained by A / D converting the bias voltage which is the center voltage of the output signal from the knock sensor is obtained. Knocking is detected as a digital signal that indicates the peak value by subtracting the offset correction value from the digital data obtained by A / D conversion of the output signal from the knock sensor, which is latched as the offset correction value and the knock determination section signal is turned on. A peak detection circuit for knocking detection provided to a microcomputer is provided.

According to the sixth aspect of the present invention, the offset correction values in the fifth aspect are averaged to obtain a new offset correction value, and the output signal from the knock sensor is A / D converted when the knock determination section signal is on. A peak detection circuit for knocking detection is provided in which a new offset correction value is subtracted from the obtained digital data and a digital signal indicating a peak value is given to a microcomputer for detecting knocking.

According to the seventh aspect of the present invention, when the offset correction value or the new offset correction value in the fifth or sixth aspect is out of the predetermined range, the standard value is set to the second new offset correction value. And a microcomputer for detecting knocking, which is a digital signal indicating a peak value by subtracting the second new offset correction value from digital data obtained by A / D converting the output signal from the knock sensor when the knock determination section signal is on. A peak detection circuit for knocking detection is provided.

According to the eighth aspect of the present invention, when the offset correction value or the new offset correction value in the fifth or sixth aspect is out of the predetermined range, the upper limit value or the lower limit value is set to the second new offset. As a correction value, when the knock determination section signal is on, the second new offset correction value is subtracted from the digital data obtained by A / D conversion of the output signal from the knock sensor, and the digital signal indicating the peak value is detected as knocking. A peak detection circuit for knocking detection provided to a microcomputer is provided.

According to a ninth aspect of the present invention, when the offset correction value or the new offset correction value in the fifth aspect or the sixth aspect is out of a preset limit range, the previous offset correction value Is used as a second offset correction signal, and when the knock determination section signal is turned on, the second offset correction value is subtracted from the digital data obtained by A / D conversion of the output signal from the knock sensor, and the digital signal indicating the peak value is knocked. There is provided a peak detection circuit for knocking detection, which is provided to a microcomputer for detecting.

According to the tenth aspect of the present invention, the offset correction value or the new offset correction value is preset in the knock detection peak detection circuit of the seventh, eighth or ninth aspect. Provided is a knock determination circuit that lowers the level of knock determination and compares it with the output of the A / D converter when the value is out of the limit range.

According to the eleventh aspect of the present invention, in the knock detection peak detection circuit according to the seventh aspect, the eighth aspect or the ninth aspect, an offset correction value or a new offset correction value is preset. A reset circuit is provided for resetting the peak detection circuit for knocking detection when it is out of the limit range.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings. The same reference numerals denote the same parts throughout the drawings. FIG. 1 is a block diagram showing a peak detection circuit for knocking detection according to a first embodiment of the present invention. In the figure, an analog signal from a knock sensor attached to an internal combustion engine is input to an input terminal IN via a bandpass filter. Since the knock sensor and the bandpass filter are the same as the conventional ones, their illustration is omitted. The input terminal IN is connected to the input of the first amplifier 1,
The output of the first amplifier is connected to the input of the second amplifier 2 and to one terminal of the switch 3. The output of the second amplifier is connected to the other terminal of the switch 3. The other contact of the switch 3 is connected to the 8-bit A / D converter 4. The output of the 8-bit A / D converter 4 is connected to a microcomputer (not shown) and is also connected to one input of the comparator 5. A value F _{0 which} is slightly smaller than the upper limit value of the dynamic range of the 8-bit A / D converter 4 is input to the other input of the comparator 5.
Is entered. The value of F ₀ is determined according to the output of the comparator 5. That is, if the dynamic range of the 8-bit A / D converter 4 is, for example, 5 V, F ₀ is B3 (h) when the first amplifier 1 is selected by the switch 3 and when the second amplifier 2 is selected, for example. Is E6 (h). The output of the comparator 5 is also input to the microcomputer.

Next, the operation of the circuit shown in FIG. 1 will be described. For example, the 8-bit A / D converter 4 converts the input analog signal into a digital signal in response to the A / D start signal every 2 μsec. When the value of the output digital signal of the 8-bit A / D converter 4 is smaller than F ₀ , the switch 3 is controlled according to the output of the comparator 5 so that the output of the second amplifier 2 is 8-bit A.
It is connected to the input of the / D converter 4. In this state,
The 8-bit A / D converter 4 is supplied with a signal obtained by amplifying an input analog signal by the first amplifier and the second amplifier. When the value of the output digital signal of the 8-bit A / D converter 4 becomes F ₀ or more, the comparator 5 outputs a gain switching signal, which switches the switch 3 and
The output of the amplifier 1 is connected to the input of the 8-bit A / D converter 4. As a result, the analog signal amplified only by the output of the first amplifier is input to the 8-bit A / D converter 4. Thus, when the output value of the 8-bit A / D converter 4 is about to exceed the dynamic range of the 8-bit A / D converter 4, the gain of the input signal is reduced to
A signal within the dynamic range is always input to the bit A / D converter 4, and the 8-bit A / D converter 4 can always operate normally. This switching is possible because the analog signal applied to the input terminal is a signal close to a sine wave with a substantially constant frequency, and each part thereof is a signal close to a linear signal that smoothly changes.

Output of 8-bit A / D converter 4 and comparator 5
Is output to the microcomputer and used for knock determination. As a result, since a digital A / D converter is used instead of the conventional analog peak hold circuit, no capacitor is required, and the knock detection peak detection circuit can be optimally configured for high density and IC implementation. it can.

FIG. 2 is a block diagram showing a peak detection circuit for knocking detection according to the second embodiment of the present invention. 1 is different from FIG. 1 in that it includes a comparator 21, a flip-flop 22 and a DC power supply 23 in FIG. 2 in place of the comparator 5 in FIG. 1, and other configurations are the same as in FIG. Is. The output of the first amplifier 1 is connected to one input end of the comparator 21, and the other input end of the comparator 21 is connected to a DC power supply 23 of, for example, 3.5V.

Next, the operation of the circuit shown in FIG. 2 will be described. A / D output from the microcomputer, for example, every 2 μs
In response to the start signal, the 8-bit A / D converter 4 converts the input analog signal into a digital signal. Second amplifier 1
When the output voltage of the DC power supply 23 becomes higher than the output voltage of the DC power supply 23, which is 3.5V, the comparator 21 outputs a signal "1", and the flip-flop 22 outputs the signal in response to the rising edge of the next A / D start signal. To latch. Then, the flip-flop 22 gives its output to the switch 3 as a gain switching signal, the switch 3 is switched according to the gain switching signal, and the output of the amplifier 1 is input to the 8-bit A / D converter 4. Become. Thus, the switch 3 is not switched during the A / D conversion of the output of the second amplifier 2 and is switched according to the next A / D start signal, so that the A / D conversion operation is interrupted. There is nothing to do. When the input value of the 8-bit A / D converter 4 is about to exceed the dynamic range of the 8-bit A / D converter 4, the gain of the input signal is reduced to keep the dynamic range of the 8-bit A / D converter 4 constant. Since the signal within the range is input, the 8-bit A / D converter 4 can always operate normally. This switching is possible because the analog signal applied to the input terminal is a signal close to a sine wave having a substantially constant frequency and each part thereof is a signal close to a linear signal that smoothly changes, as in the first embodiment. is there.

The output of the 8-bit A / D converter 4 and the output of the flip-flop 22 are input to a microcomputer and used for knock determination. FIG. 3 is a block diagram showing a peak detection circuit for knocking detection according to a third embodiment of the present invention. In the figure, in addition to the configuration shown in FIG. 1, the bit shift circuit 31 includes an 8-bit A / D converter 4
Connected to the output. The bit shift circuit 31 includes an 8-bit register 32, a switch 33, and an 8 + n bit register 34 (n is a positive integer). In the example shown,
The register 34 is a 9-bit register.

Next, the operation of the circuit shown in FIG. 3 will be described. The process until the 8-bit A / D converter 4 outputs digital data within the dynamic range is the same as that of the first embodiment, and the description thereof is omitted here. When the comparator 5 outputs the gain switching signal, the switch 33 switches the register 32.
The output of is shifted to the lower (left) by, for example, 1 bit and input to the register 34. Thereby, for example, when the input signal of the 8-bit A / D converter 4 is amplified by a double amplification factor, the output of the 8-bit A / D converter 4 is halved by the bit shift circuit 31. Therefore, the same resolution as that on the input side of the 8-bit A / D converter 4 can be secured on the output side without using a division circuit.

In FIG. 3, one input of the comparator 5 is connected to the output of the 8-bit A / D converter 4, but instead of this, one input of the comparator 5 is connected to the bit shift circuit 31. May be connected to output. In this case, F ₀ can be kept constant regardless of the comparison result. In FIG. 3, the bit shift circuit 31 is connected to the output of the 8-bit A / D converter 4 in the circuit of FIG. 1, but instead of this, the 8-bit A / D converter 4 of the circuit of FIG. A bit shift circuit may be connected to the output. In this case, the bit shift circuit is controlled according to the output of the flip-flop 22.

FIG. 4 is a block diagram showing a knock detection peak detection circuit according to a fourth embodiment of the present invention. In the figure, a DC power supply 41 for setting a bias voltage which is a center voltage of an output signal of a knock sensor attached to an internal combustion engine is connected to one terminal of a switch 42. The other terminal of the switch 42 is the input terminal I of this circuit.
N. By switching the switch 42,
The input terminal IN or the DC power supply 41 is connected to the amplifier 1. The output of the amplifier 1 is connected to the input of the 8-bit A / D converter 4. The output of the 8-bit A / D converter 4 is connected to the register 43 and the subtractor 44. The output of the register 43 is connected to the subtraction input of the subtractor 44.
The delay circuit 45 is connected between the knock determination section signal and the register 43.

Next, the operation of the circuit shown in FIG. 4 will be described. Since knocking occurs only during the combustion period in the internal combustion engine,
In order to avoid erroneous detection due to ignition noise and valve vibration,
Generally, only the timing at which knocking occurs (about 0 ° to 90 ° after top dead center) is the knock determination period. Therefore, there is a time when the signal from the knock sensor does not have to be A / D converted. On the other hand, the bias voltage created by the filter circuit in the preceding stage of the peak detection circuit is generated by the division of resistors connected in series between the power supply and the ground, IC, etc., so that there are individual differences and also fluctuate depending on temperature. . Therefore, in the present embodiment, the signal from the knock sensor is cut off at this time, and instead, the bias voltage serving as the center voltage of the output signal of the knock sensor is input to the A / D converter 4, and A
The value obtained by the / D conversion is used as the offset correction value.

More specifically, when the knock determination section signal given from the microcomputer is off, the switch 42 connects the DC power supply 41 to the input of the amplifier 1 and the voltage of the DC power supply 41, for example, 2.5V, Is A / D converted by the 8-bit A / D converter 4. Delay circuit 4
5 is a register 43 which is a latch trigger signal obtained by delaying the start time of turning off the knock determination section signal by a necessary time.
To enter. The register 43 responds to the latch trigger signal and outputs the offset A which is the output of the 8-bit A / D converter 4.
Stores the / D conversion value. The offset A / D conversion value is fetched from the register 43 as an offset correction value.

Next, when the knock determination section signal is turned on, the switch 42 is switched, and the signal from the knock sensor applied to the input terminal IN is amplified by the amplifier 1 to the 8-bit A / D converter 4. Is entered. 8-bit A
The / D converter 4 A / D-converts this to obtain digital data. The subtractor 44 subtracts the offset correction value from the register 43 from this digital data to obtain the peak value of Katayama. The peak value of this Katayama is sent to the microcomputer.

As a result, the offset correction value fluctuates during the non-knock determination section according to the individual difference of the DC power supply 41 and the temperature fluctuation, so that a proper peak value can be always inputted to the microcomputer, and the knocking value can be inputted. The determination can be made more accurately. FIG. 5 is a block diagram showing a register in a peak detection circuit for knocking detection according to a fifth embodiment of the present invention. In the figure, instead of the register 43 shown in FIG. 4, an 8-bit register 51 at the preceding stage for storing the offset A / D converted value output from the 8-bit A / D converter 4 in FIG. A shift register 53 for shifting the output of the adder 52 in the lower direction by 1 bit, an 8-bit shift register 54 in the subsequent stage for storing the contents of the shift register 53, and a delay circuit for delaying the knock determination section signal by a necessary time. 5, a register with 5 and a delay circuit 56 for further delaying the delayed signal is shown.

Next, the operation of the circuit shown in FIG. 5 will be described. The 8-bit register 51 at the preceding stage responds to the offset A / D converted value output from the 8-bit A / D converter 4 by the delay circuit 55 by delaying the knock determination section signal by a necessary amount for timing adjustment. To latch. The adder 52 adds the data latched in the subsequent 8-bit register 54 and the offset A / D conversion value latched in the previous 8-bit register 51. Shift register 53
Shifts one bit in the lower direction so that the added value is halved. The 8-bit register 54 is the shift register 53
The data shifted by is latched according to the signal obtained by further delaying the knock determination section signal by the delay circuit 56 by the amount necessary for timing adjustment. As a result, the average value of the offset A / D converted value at the time of the previous sampling and the offset A / D converted value at the time of the current sampling is latched in the subsequent 8-bit register 54. The average value data is input to the subtractor 44 of FIG. 4 as a new offset correction value. This reduces the probability that the peak value calculated by the abnormal offset value will be input to the microcomputer.

In FIG. 5, the average of the contents of the two registers, that is, the contents of the registers in the preceding stage and the contents of the registers in the latter stage is taken, but instead of this, the contents of the plurality of registers are averaged. Good. FIG. 6 is a block diagram showing a register in a peak detection circuit for knocking detection according to a sixth embodiment of the present invention. In the figure, instead of the register 43 shown in FIG. 4, the 8-bit A / D converter 4 of FIG.
An 8-bit register 61 in the preceding stage that stores the offset A / D conversion value that is the output of, and the upper limit setting value of the offset correction value (for example, 88 in hexadecimal notation, hereinafter described as 88h)
An upper limit set value register 62 for storing
A register including a standard value register 64 for storing a standard value (for example, 80h) of an offset correction value, a switch 65, an 8-bit register 66 at a subsequent stage, and a delay circuit 67 is shown.

Next, the operation of the circuit shown in FIG. 6 will be described. The 8-bit register 61 in the preceding stage responds to the offset A / D converted value output from the 8-bit A / D converter 4 by the delay circuit 67 by delaying the knock determination section signal by a necessary amount for timing adjustment. To latch. The comparator 63 includes the contents of the 8-bit register 61 and the upper limit set value register 62.
When the output of the 8-bit register 61 is larger than the output of the upper limit value storage register 62, an abnormality signal is output. When an abnormal signal is output from the comparator 63, the switch 65 stores the standard value stored in the standard value storage register 64 as a new offset correction value in the subsequent 8-bit register 66, and no abnormal signal is output. At this time, the output of the 8-bit register 66 in the previous stage is stored in the 8-bit register 66 in the subsequent stage as a new offset correction value.
The output of the 8-bit register 66 is the subtractor 44 shown in FIG.
As a new offset value.

As a result, the probability that the peak value calculated by the abnormal offset value is input to the microcomputer is further reduced. In FIG. 6, the offset A / D conversion value, which is the output of the 8-bit A / D converter 4 shown in FIG. 4 when the knock determination section signal is off, is input to the 8-bit register 61. The same effect can be obtained by inputting the new offset correction value, which is the content of the subsequent 8-bit register 54, to the 8-bit register 61.

Although FIG. 6 shows an example in which the upper limit set value register 62 is provided, instead of this, a lower limit set value register for setting the lower limit value of the offset correction value is provided and the offset A / D conversion value is set to the lower limit value. Even if the standard value is used as the new offset correction value when the value is less than, the same effect can be obtained. FIG. 7 is a block diagram showing a register in a knock detection peak detection circuit according to a seventh embodiment of the present invention. In the figure, instead of the register 43 shown in FIG. 4, a lower limit set value register 71 for storing a lower limit value (eg, 78h) of the offset correction value and an 8-bit A / D of FIG.
A register including a comparator 72 for comparing the offset A / D conversion value output from the converter 4 with the lower limit value, a switch 73, and an 8-bit A / D converter 74 is shown.

Next, the operation of the circuit shown in FIG. 7 will be described. The offset A / D conversion value output from the 8-bit A / D converter 4 of FIG.
Is compared with the lower limit value from the lower limit set value register 71. When the offset A / D converted value falls below a predetermined lower limit value due to the influence of noise or the like, the comparator 72 outputs an abnormal signal. When the abnormal signal is output from the comparator 72, the switch 73 gives the lower limit value stored in the lower limit set value register 71 to the subtractor 44 shown in FIG. 4 as the second new offset correction value. If the offset A / D conversion value is equal to or larger than the predetermined lower limit value due to the influence of noise or the like, the offset A / D conversion value is given to the subtractor 44 shown in FIG. 4 as the second new offset correction value.

As a result, the probability that the peak value calculated by the abnormal offset value is input to the microcomputer is further reduced. In FIG. 7, the offset A / D conversion value, which is the output of the 8-bit A / D converter 4 in FIG. 4 when the knock determination section signal is off, is input to the comparator 72.
Alternatively, the same effect can be obtained by inputting the new offset correction value, which is the contents of the 8-bit register 54 of FIG. 5, to the comparator 72.

Although FIG. 7 shows an example in which the lower limit set value register 71 is provided, instead of this, an upper limit set value register for setting the upper limit value of the offset correction value is provided and the offset A / D conversion value is set to the upper limit value. If the value exceeds
The same effect can be obtained even with the configuration in which the new offset correction value is used. FIG. 8 is a block diagram showing a register in a peak detection circuit for knocking detection according to an eighth embodiment of the present invention. In the figure, instead of the register 43 shown in FIG. 4, an 8-bit register 81 in the preceding stage for storing the offset A / D conversion value output from the 8-bit A / D converter 4 in FIG. The upper limit set value register 82 for storing the upper limit value of the offset correction value, the first comparator 83, the lower limit set value register 84 for storing the lower limit value of the offset correction value, the second comparator 85, the OR circuit 86, Switch 87,
A register including an 8-bit register 88 in the subsequent stage and a delay circuit 89 offset A / D conversion value 90 is shown.

Next, the operation of the circuit shown in FIG. 8 will be described. The contents of the 8-bit A / D converter 81 at the preceding stage are compared with the upper limit value and the lower limit value by the comparator 83 offset A / D converted value 85, respectively. When out of the range, the OR circuit 86 outputs an abnormal signal. When an abnormal signal is output, switch 8
7 is turned off, and the knock determination section signal via the delay circuits 89 and 90 is not input to the subsequent 8-bit A / D converter 88. As a result, the data at the previous sampling remains in the 8-bit A / D converter 88 in the subsequent stage without being updated. If the content of the 8-bit A / D converter 81 in the preceding stage is within the range between the upper limit value and the lower limit value, the switch 87 remains on, and the 8-bit A / D signal in the preceding stage depends on the knock determination section signal. The contents of the D converter 81 are sequentially latched in the subsequent 8-bit A / D converter 88. The data stored in the subsequent 8-bit A / D converter 88 is input to the subtractor 44 in FIG. 4 as a new offset correction value.

As a result, the probability that the peak value calculated from the abnormal offset value is input to the microcomputer is further reduced. In FIG. 8, the offset A / D conversion value, which is the output of the 8-bit A / D converter 4 in FIG. 4 when the knock determination section signal is off, is input to the 8-bit A / D converter 81 in the preceding stage. Alternatively, the same effect can be obtained by inputting the new offset correction value, which is the contents of the 8-bit register 54 of FIG. 5, to the 8-bit A / D converter 81.

FIG. 9 is a block diagram showing a knock determination circuit according to the ninth embodiment of the present invention. In this figure, this circuit shows the maximum value of the A / D converted value which is the output of the 8-bit A / D converter 4 in the peak detection circuit for knocking detection shown in FIGS. 1 to 8 for each knock determination section. A maximum value hold circuit 91 for holding, an averaging circuit 92 for averaging the maximum value, an amplifier 93 for k times, an amplifier 94 for k × 0.9 times, and FIGS. 6, 7, and 8. A switch 95 that switches in response to the abnormal signal shown and a comparator 96 that makes a knock determination are provided.

Next, the operation of the circuit shown in FIG. 9 will be described. The value held in the maximum value hold circuit 91 is given to one input of the comparator 96 and also to the moderating circuit 92. The smoothing circuit 92 averages the hold values by the method shown in FIG. The output of the averaging circuit 92 is amplified k times by the amplifier 93, and the amplifier 94
Is amplified by k × 0.9 times. When no abnormal signal is generated, the output of the amplifier 93 having a large amplification factor is given to the other input of the comparator 96. In this case, the output of the comparator 96 serves as a threshold for knock determination. However, when the offset A / D conversion value or the new offset correction value exceeds the limit value and the abnormal signal of the offset shown in FIGS. 6, 7, and 8 occurs, the switch 95 responds to this abnormal signal, and the switch 95 Amplifier 9 with switching and small amplification factor
The output of 4 is provided to the input of the other side of the comparator 96. In this way, when an abnormal signal is generated, the threshold level for knock determination is lowered to increase the chance of knock detection. Since ignition timing is retarded when knocking is detected, knocking is less likely to occur, which can contribute to prevention of destruction of the internal combustion engine.

FIG. 10 is a block diagram showing a reset circuit of a knock detection peak detection circuit according to a tenth embodiment of the present invention. In the figure, the reset circuit according to the present embodiment includes a one-shot multivibrator 101 for detecting an abnormal signal shown in FIGS. 6, 7, and 8 and an AN.
And a D circuit 102. In operation, when the abnormal signal shown in FIGS. 6, 7, and 8 is generated, the one-shot multivibrator 101 sets its output signal to the high level for a certain period of time and applies it to one input of the AND circuit 102. As a result, the peak detection circuit for knocking detection shown in FIGS. 1 to 8 is reset. Even when the external reset signal is input, it is applied to the other input of the AND circuit 102, and the peak detection circuit for knocking detection is also reset.

In the actual configuration, the reset is performed outside the knock determination section to reduce the influence on the knock control. In the above description,
Although the 8-bit A / D converter 4 is used, it is needless to say that an A / D converter having an arbitrary bit may be used instead of the 8-bit A / D converter 4.

[0044]

As is apparent from the above description, according to the present invention, the peak detection circuit for knocking detection is configured by using the A / D converter, so that the electronic control device can be highly integrated and integrated into an IC. It has the effect of being possible. As a more detailed effect, paying attention to the fact that the output waveform of the knock sensor is close to a sine wave and is close to a linear signal that slowly changes in each part, and the gain of the signal input to the A / D converter is input or It can be easily switched according to the amplitude of the output signal, and the dynamic range of the A / D converter can be effectively used.

Further, even if the offset value that determines the bias voltage, which is the center voltage of the output signal of the filter circuit, changes due to the individual difference of the power source supplying the bias voltage or the temperature change, the change can be learned. It is possible to obtain the knock detection peak detection circuit capable of outputting the output peak value to the microcomputer with the optimum offset correction value.

Further, when the offset correction value exceeds the preset limit range due to the influence of noise or the like, the peak value calculated by the abnormal offset value is set by setting the new offset correction value within the limit. Has the effect of reducing the probability of input to the microcomputer.
Further, when the offset correction value exceeds a preset limit range due to the influence of noise or the like, the knock detection threshold level is lowered or the peak detection circuit for knocking detection is reset to prevent the internal combustion engine from being destroyed. The effect that it can contribute is produced.

[Brief description of drawings]

FIG. 1 is a block diagram showing a peak detection circuit for knocking detection according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a peak detection circuit for knocking detection according to a second embodiment of the present invention.

FIG. 3 is a block diagram showing a peak detection circuit for knocking detection according to a third embodiment of the present invention.

FIG. 4 is a block diagram showing a peak detection circuit for knocking detection according to a fourth embodiment of the present invention.

FIG. 5 is a block diagram showing a register in a knock detection peak detection circuit according to a fifth embodiment of the present invention.

FIG. 6 is a block diagram showing a register in a knock detection peak detection circuit according to a sixth embodiment of the present invention.

FIG. 7 is a block diagram showing a register in a peak detection circuit for knocking detection according to a seventh embodiment of the present invention.

FIG. 8 is a block diagram showing a register in a knock detection peak detection circuit according to an eighth embodiment of the present invention.

FIG. 9 is a block diagram showing a knock determination circuit according to a ninth embodiment of the present invention.

FIG. 10 is a block diagram showing a reset circuit according to a tenth embodiment of the present invention.

FIG. 11 is a block diagram showing a conventional knock control device.

FIG. 12 is a circuit diagram showing a conventional peak detection circuit for knocking detection.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... 1st amplifier 2 ... 2nd amplifier 3 ... Switch 4 ... 8-bit A / D converter 5 ... Comparator 21 ... Comparator 31 ... Bit shift circuit 43 ... Register 44 ... Subtractor 50 ... Averaging circuit 61 ... front stage register 62 ... upper limit set value register 63 ... comparator 64 ... standard value register 65 ... switch 66 ... rear stage register 71 ... lower limit set value register 72 ... comparator 73 ... switch 74 ... 8-bit register 81 ... previous stage register 82 ... Upper limit set value register 83 ... Comparator 84 ... Lower limit set value register 85 ... Comparator 88 ... Post-stage register 90 ... Level forming circuit

Front page continuation (72) Inventor Kazuaki Murota 1-2-2 Goshodori, Hyogo-ku, Kobe-shi, Hyogo Within Fujitsu Ten Ltd. (72) Inventor Shuji Kimura 1-2-2 Gosho-dori, Hyogo-ku, Kobe, Hyogo Prefecture No. 28 within Fujitsu Ten Limited (72) Inventor Takahiro Aki 1-2-2 Goshodori, Hyogo-ku, Kobe, Hyogo Prefecture Within Ten Ten Fujitsu Limited

Claims (11)

[Claims] 1. A digital signal obtained by A / D converting the analog signal according to an A / D start signal in a peak detection circuit for detecting a peak value of the analog signal from a knock sensor attached to an internal combustion engine. And a comparator (5) for determining whether the output value of the A / D converter exceeds a predetermined value within the dynamic range of the A / D converter. ), A first amplifier (1) for amplifying an output signal of the knock sensor, a second amplifier (2) having a larger amplification factor than the first amplifier, and the comparator (5) When it is determined that the output value of the D converter (4) exceeds the predetermined value, the output of the first amplifier is input to the A / D converter, and the output of the A / D converter is output by the comparator. It was judged that the value was less than the specified value And a switch (3) for inputting the output of the second amplifier to the A / D converter when the peak detection circuit for knocking detection. 2. A digital signal obtained by A / D converting the analog signal according to an A / D determination start signal in a peak detection circuit for detecting a peak value of the analog signal from a knock sensor mounted on an internal combustion engine. An A / D converter (4) that gives a signal to a knock determination device, a first amplifier (1) that amplifies the output signal of the knock sensor, and a second amplifier (amplification factor that is larger than the first amplifier ( 2)
A comparator (21) for determining whether or not the output level of the first amplifier exceeds a predetermined value within the dynamic range of the A / D converter; and the comparator when the A / D start signal is input. Is the output level of the first amplifier is A
When it is determined that the A / D converter exceeds the predetermined value, the output of the first amplifier is input to the A / D converter, and the comparator causes the output level of the first amplifier to be less than or equal to the predetermined value. And a switch (3) for inputting the output of the second amplifier to the A / D converter when it is determined that the peak detection circuit for knocking detection. 3. The A / D converter when the comparator determines that the output value of the A / D converter exceeds the predetermined value.
The output of the D converter is shifted by n bits (n is a positive integer), and when the comparator determines that the output value of the A / D converter is less than or equal to the predetermined value, the A / D converter outputs Bit shift circuit that outputs the output without bit shifting (3
2. The peak detection circuit for knocking detection according to claim 1, further comprising 1), wherein the output of the bit shift circuit is input to the knock determination device. 4. The A / D converter () when the comparator (21) determines that the output level of the first amplifier (1) exceeds the predetermined value when the A / D start signal is input. The output of 4) is shifted by n bits, and when the comparator (21) determines that the output level of the first amplifier is less than or equal to the predetermined value when the A / D start signal is input, the A
3. A peak detection circuit for knocking detection according to claim 2, further comprising a bit shift circuit for outputting the output of the D / D converter (4) without bit shifting, and inputting the output of the bit shift circuit to the microcomputer. . 5. A DC power supply (41) for providing a bias voltage which is a center voltage of an output signal from a knock sensor mounted on an internal combustion engine, an A / D converter (4), and a knock determination section signal when the signal is off. The DC power source (41) is
The output signal from the knock sensor is connected to the A / D converter (4) when the knock determination section signal is ON.
Switch (42) connected to input of D / D converter (4)
A register (43) for latching a value output from the A / D converter as an offset correction value when the knock determination section signal is off, and an output from the A / D converter when the knock determination section signal is on And a subtracter (44) for obtaining a digital signal indicating a peak value by subtracting the offset correction value from the digital data stored therein, and the output of the subtractor (44) is applied to a microcomputer for detecting knocking. Peak detection circuit for detection. 6. The register (43) includes an averaging circuit (50) that obtains a new offset correction value obtained by averaging the offset correction value over a plurality of sampling timings, and the subtractor (4) includes the averaging circuit (50). When the knock determination section signal is turned on, the new offset correction value is subtracted from the digital data output from the A / D converter (4) to obtain a digital signal indicating a peak value.
The knocking peak detecting circuit according to claim 5. 7. The register (43) includes a previous stage register (61) for storing the offset correction value or the new offset correction value, and a limit value storage register (62) for storing a preset offset limit value. ), A comparator (63) that outputs an abnormal signal when the content of the register (61) of the preceding stage is out of the range of the content of the limit value storage register (62), and a standard value of preset offset is stored. Standard value storage register (64) and switch (6
5) and a register (66) in the subsequent stage, and the switch (65) uses the standard value stored in the standard value storage register (64) as a new offset correction value when the abnormal signal is output. When the abnormal signal is not output, the output of the register (61) of the preceding stage is stored in the register (66) of the following stage as a new offset correction value. The peak detection circuit for knocking detection according to claim 5 or 6, wherein the output of the register (66) is given to the subtractor (44). 8. The register (43) comprises: a register at a previous stage for storing the offset correction value or the new offset correction value; a limit value register (71) for storing a predetermined limit value; A comparator (72) that outputs an abnormal signal when the output of the register is out of the range of the limit value, a switch (73), and a register (7) in the subsequent stage.
4), the switch (73) applies the limit value stored in the limit value register (71) to the subtracter as a second new offset correction value when the abnormal signal is output. The peak detection circuit for knocking detection according to claim 5 or 6, wherein 9. The register (43) includes a preceding stage register (81) for storing the offset correction value or the new offset correction value, and a limit value register (82, 84) for storing a predetermined limit value. A comparator (83, 85) for outputting an abnormal signal when the output of the register of the preceding stage is out of the range of the limit value, and a switch (87)
And a register (88) in the subsequent stage, the switch (87) does not update the register (88) with the contents of the register (81) in the previous stage when the abnormal signal is output, and the second offset correction value. 7. The peak detection circuit for knocking detection according to claim 5, wherein the peak detection circuit is given to the subtractor as. 10. A maximum value holding circuit (91) for holding the maximum value of the A / D converted value output from the subtractor (44) for each knock determination section, and a level for determining a threshold level for knock determination. The formation circuit (90) and a comparator (96) are provided, and the threshold level determined by the level determination circuit (90) is lowered when the abnormal signal is output. And a knock determination circuit connected to the output of the knock detection peak detection circuit according to claim 9. 11. A reset circuit that resets the entire knock detection peak detection circuit according to claim 7, 8 or 9 when the abnormal signal is output.