JPH09181183A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To impart freedom to the combination of a chip and a package by improving the layout of the peripheral part of the chip. SOLUTION: This device is constituted by arranging I/O regions 14 and pad regions 12 in the peripheral part of a chip. A wiring region 15 is formed between the I/O regions 14 and the pad regions 12. First wiring groups 16 parallel to the sides of the chip are formed in the wiring region 15. The part between the first wiring groups 16 and a second wiring group stretching from each I/O is selectively connected, and the part between the first wiring groups 16 and a third wiring group stretching from each pad 11 is selectively connected.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device (hereinafter sometimes abbreviated as "LSI"), and more particularly,
LS having an I / O area and a pad area in the periphery of the chip
Regarding I.

[0002]

2. Description of the Related Art FIG. 4 is a schematic plan view of an LSI of this type, and 1 is a chip. In the peripheral portion of the chip 1, a pad region 3 having a large number of pads 2 and an I / O region 5 having a large number of I / Os (input / output buffers) 4 are provided, and adjacent pads and I / Os (for example, Pad 2a and I / O 4a)
And is connected by wiring (not shown),
The diameter between the pad 2 and the terminal 8 of the package 7 is 20 to 3
They are connected by a thin gold wire (wire) 9 of about 0 μm.

[0003]

However, in such a conventional semiconductor integrated circuit device, since the arrangement order of the I / O 4 and the arrangement order of the terminals 8 correspond one-to-one, the chip 1 and the package 7 are There is a problem in that there is no flexibility in combination, and for example, even if chips having the same function are applied to packages having different terminal arrangements, at least a large design change of the I / O area is required. .

By crossing the wires 9, the functions of some terminals (or I / O) can be exchanged.
In addition to denying a short between wires at an intersection,
This is not practical because the bonding process itself becomes complicated. Therefore, the present invention has been made in view of these problems, and devises the layout of the chip peripheral portion to
The purpose is to give flexibility to the combination of chips and packages.

[0005]

In the semiconductor integrated circuit device having an I / O region and a pad region on the periphery of a chip, a wiring region is formed between the I / O region and the pad region. At the same time, a first wiring group parallel to the side of the chip is formed in the wiring region, and the first wiring group and each I
This can be achieved by selectively connecting the second wiring group extending from / O and the first wiring group and the third wiring group extending from each pad.

[0006]

Embodiments of the present invention will be described below with reference to the drawings. 1 is a schematic plan view of a chip showing an embodiment of a semiconductor integrated circuit device according to the present invention, and FIG. 2 is an enlarged view of a main part thereof (A part in FIG. 1). In the figure, 10 is a chip, and a large number of pads 11 are provided around the chip 10.
And a pad region 12 having a plurality of I / Os 13 and an I / O region 14 having a large number of I / Os 13 are formed.

The first characteristic feature of this embodiment is that the wiring region 15 is formed between the pad region 12 and the I / O region 14, and the first wiring group is formed in this wiring region 15. 16 is formed. The first wiring group 16 is continuously formed so as to surround the I / O regions 14 provided on the four sides of the chip 10, and the number of lines thereof is equal to or greater than that of the I / O 13.

The second characteristic item is omitted in FIG. 1 for convenience of illustration, but as shown in FIG.
The second wiring group 17 extending from O13 and the third wiring group 18 extending from each pad 12 are crossed on the first wiring group 16 with different wiring layers and the first wiring group 16 and the second wiring group. 17 and between the first wiring group 16 and the third wiring group 18 are selectively connected by interlayer contacts 19a and 19b.

Although the first wiring group 16 is shown by four lines in FIG. 2, this is a convenient measure for making the drawing easy to see. In such a structure, the pad 11 of FIG.
And I / O 13 and first to third wiring groups 16, 17, 18
The respective lines are labeled with identification symbols (a to d), and the connection relationship between each pad and each I / O when the illustrated interlayer contacts 19a and 19b are provided is first examined. The pad 11a is located below the uppermost line 18a of the third wiring group 18, four interlayer contacts 19b, 19b, 19a, 19a, and the lower two lines 17c, 17d of the second wiring group 17. It is connected to two I / Os 13c and 13d. Therefore, for example, if the lowermost I / O 13d is the output buffer and the upper I / O 13c is the input buffer, the uppermost pad 11a will have these two I / Os 13c, 1
Functions as an input / output pad for 3d.

Next, the second pad 11b is the second line 18b of the third wiring group 18, and the two interlayer contacts 19 are formed.
b, 19a and the second line 17b of the second wiring group 17
Is connected to the second I / O 13b through the intermediary of one interlayer contact 19b and the third interlayer contact 19b.
It is also connected to the bottom pad 11d via the bottom line 18d of the wiring group 18. Therefore, the second pad 11b and the bottom pad 11d are connected to the second I / O1.
It functions as a shared pad of 3b.

Next, the third pad 11c is connected to the third line 18c of the third wiring group 18 and the two interlayer contacts 19.
b, 19a and the top line 17a of the second wiring group 17
Is connected to the top I / O 13a via. Therefore, the third pad 11c is the top I / O 13
Functions as a dedicated pad for a. As described above, in this embodiment, the interlayer contacts 19a and 19b are selectively arranged at each intersection of the first wiring group 19 to the third wiring group 18,
Regardless of the order of arrangement of I / O 13, each pad 11 and I / O
A particularly advantageous effect is obtained in that the connection relationship with 13 can be set freely. Therefore, it is possible to give flexibility to the combination of the chip and the package, for example,
A technology suitable for use when a plurality of functional circuits are formed on one chip and these functions are selected and mounted in different types of packages, or when bonding is changed to make it look like an LSI having a different function. Can be provided.

In the above embodiment, the first wiring group 16
Are continuously formed so as to surround the I / O regions 14 provided on the four sides of the chip 10. According to this, since pads and I / Os located on different sides can be connected to each other, the degree of freedom is the highest, which is preferable. However, only pads and I / Os located on the same side can be connected. Alternatively, it may be as shown in FIG. That is, the first wiring groups 16 ', 16', 16 ', 16' may be provided separately for each side of the chip 10 '. The enlarged view of the portion A is FIG. 2 which is common to the above embodiment.

Further, in each of the above embodiments, the example in which the pad area and the I / O area are provided on the four sides of the chip is shown, but the invention is not limited to this. It may be one side, two sides or three sides.
Further, in each of the above embodiments, the bonding wire method is applied, but the tape carrier method can also be applied, for example.

[0014]

According to the present invention, the combination of a chip and a package can be made flexible, and a particularly advantageous effect that the degree of freedom in LSI design can be improved, which is not available in the prior art, can be obtained.

[Brief description of the drawings]

FIG. 1 is a schematic plan view of a chip according to an embodiment.

FIG. 2 is an enlarged view of a main part of the embodiment.

FIG. 3 is a schematic plan view of a chip of another embodiment.

FIG. 4 is a schematic plan view of a conventional chip including a package.

[Explanation of symbols]

 11: Pad 12: Pad Area 13: I / O 14: I / O Area 15: Wiring Area 16: First Wiring Group 17: Second Wiring Group 18: Third Wiring Group

Claims (1)

[Claims] 1. A semiconductor integrated circuit device having an I / O region and a pad region in the periphery of a chip, wherein a wiring region is formed between the I / O region and the pad region, and a chip region is formed in the wiring region. A first wiring group parallel to the side is formed, and between the first wiring group and a second wiring group extending from each I / O, and between the first wiring group and a third wiring group extending from each pad. A semiconductor integrated circuit device characterized by selectively connecting between them.