JPH09148625A - Iii-group nitride semiconductor light emitting element - Google Patents
Iii-group nitride semiconductor light emitting elementInfo
- Publication number
- JPH09148625A JPH09148625A JP32801195A JP32801195A JPH09148625A JP H09148625 A JPH09148625 A JP H09148625A JP 32801195 A JP32801195 A JP 32801195A JP 32801195 A JP32801195 A JP 32801195A JP H09148625 A JPH09148625 A JP H09148625A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- light emitting
- diode
- electrode layer
- nitride semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は逆方向の静電耐圧を
向上させた３族窒化物半導体を用いた発光素子に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a light emitting device using a Group III nitride semiconductor having an improved electrostatic breakdown voltage in the reverse direction.
【０００２】[0002]
【従来技術】従来、３族窒化物半導体発光素子として、
ZnとSiとを添加したIn1-XGaXN から成る発光層をホール
濃度 1×1018/cm3以下のｐ伝導型のAlGaN からなるｐ層
と電子濃度 2×1018/cm3のGaN から成るｎ層とで挟んだ
ダブルヘテロ構造のものが知られている。この発光素子
は、420 〜520nm の青色の発光が得られている。2. Description of the Related Art Conventionally, as a group III nitride semiconductor light emitting device,
A light emitting layer made of In 1-X Ga X N doped with Zn and Si was used as a p-type layer made of p-conduction type AlGaN with a hole concentration of 1 × 10 18 / cm 3 or less and an electron concentration of 2 × 10 18 / cm 3 . A double hetero structure is known which is sandwiched between n layers of GaN. This light-emitting device emits blue light of 420 to 520 nm.
【０００３】[0003]
【発明が解決しようとする課題】しかし、上記の構成の
発光素子は、静電気に対する正、逆方向の耐電圧が低い
という問題がある。However, the light emitting device having the above-mentioned structure has a problem that the withstand voltage in the forward and reverse directions against static electricity is low.
【０００４】本発明は上記の課題を解決するために成さ
れたものであり、その目的は、静電気に対する耐絶縁破
壊性を向上させることである。The present invention has been made to solve the above problems, and an object thereof is to improve the dielectric breakdown resistance against static electricity.
【０００５】[0005]
【課題を解決するための手段】本発明は、３族窒化物半
導体から成るｐ層、そのｐ層に接続するｐ電極層、ｎ層
及びそのｎ層に接続するｎ電極層とから成る発光部を有
した発光素子において、発光部のｐ電極層に電気的に接
続されるｎ伝導型の第１層と、発光部のｎ電極層に電気
的に接続されるｐ伝導型の第２層とが接合された逆耐圧
補償用の補償ダイオードを設けたことを特徴とする。DISCLOSURE OF THE INVENTION The present invention provides a light emitting section comprising a p-layer made of a group III nitride semiconductor, a p-electrode layer connected to the p-layer, an n-layer and an n-electrode layer connected to the n-layer. And a p-conduction type second layer electrically connected to the p-electrode layer of the light-emitting portion, and a p-conduction type second layer electrically connected to the n-electrode layer of the light-emitting portion. And a compensating diode for compensating the reverse breakdown voltage is provided.
【０００６】この補償ダイオードの作用により、発光部
に逆方向に印加される静電気による破壊を防止すること
ができる。請求項２、３の発明は、補償ダイオードと発
光部とを別々の基板に形成し、両者の接続をリードで行
ったものであり、特に、請求項３の発明は、共通に樹脂
で封止したものである。Due to the action of this compensating diode, it is possible to prevent breakdown due to static electricity applied to the light emitting portion in the opposite direction. According to the inventions of claims 2 and 3, the compensating diode and the light emitting portion are formed on different substrates, and the two are connected by leads. In particular, the invention of claim 3 is sealed with resin in common. It was done.
【０００７】請求項４、５、６の発明は、補償ダイオー
ドと発光部とを同一基板に形成したものであるので、発
光部の層形成工程において補償ダイオードを製造するこ
とができる。特に、請求項５の発明は、補償ダイオード
の層構造と発光部の層構造と同一に形成し、発光部と補
償ダイオードとの間に絶縁分離の溝を形成し、発光部と
補償ダイオードとの電気的接続をリードワイヤにより行
ったものである。よって、この発明では、発光部の３族
窒化物半導体の層形成により補償ダイオードを構成する
層を形成されるので、製造が極めて簡単化される。又、
請求項６の発明は、発光部の上に補償ダイオードを積層
したものであり、発光部を形成する工程に続いて補償ダ
イオードを形成できるため、製造が簡単となる。Since the compensating diode and the light emitting section are formed on the same substrate, the compensating diode can be manufactured in the layer forming step of the light emitting section. In particular, the invention of claim 5 is the same as the layer structure of the compensating diode and the layer structure of the light emitting portion, and the insulating isolation groove is formed between the light emitting portion and the compensating diode. The electrical connection is made by a lead wire. Therefore, according to the present invention, since the layer forming the compensating diode is formed by forming the layer of the group III nitride semiconductor of the light emitting portion, the manufacturing is extremely simplified. or,
According to the invention of claim 6, the compensating diode is laminated on the light emitting portion, and the compensating diode can be formed subsequent to the step of forming the light emitting portion, so that the manufacturing is simplified.
【０００８】[0008]
【発明の実施の形態】第１実施例 図１において、本発明の発光部に該当する発光ダイオー
ド１００は、サファイア基板１を有しており、そのサフ
ァイア基板１上に500 ÅのAlN のバッファ層２が形成さ
れている。そのバッファ層２の上には、順に、膜厚約2.
0 μｍ、電子濃度2 ×1018/cm3のシリコンドープGaN か
ら成る高キャリア濃度ｎ+ 層３、膜厚3000Å、電子濃度
1×1017/cm3のシリコンドープのGaN から成るｎ層４、
膜厚約0.05μｍのIn0.08Ga0.92N から成る発光層５、膜
厚約1.0 μｍ、ホール濃度5 ×1017/cm3、濃度1 ×1020
/cm3にマグネシウムがドープされたAl0.08Ga0.92N から
成るｐ層６１、膜厚約0.2 μｍ、ホール濃度 7×1017/c
m3、マグネシウム濃度 2×1020/cm3のマグネシウムドー
プのGaN から成るコンタクト層６２が形成されている。
そして、コンタクト層６２上にはその層６２に接合する
Niから成るｐ電極層７が形成されている。さらに、高キ
ャリア濃度ｎ+ 層３の表面の一部は露出しており、その
露出部上にその層３に接合するNiから成るｎ電極層８が
形成されている。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment Referring to FIG. 1, a light emitting diode 100 corresponding to a light emitting portion of the present invention has a sapphire substrate 1, on which a buffer layer of 500 Å AlN 3 is provided. 2 is formed. On the buffer layer 2, a film thickness of about 2.
0 [mu] m, the electron concentration of 2 × 10 18 / cm high carrier concentration comprising a silicon-doped GaN of 3 n + layer 3, the thickness 3000 Å, electron concentration
N layer 4 of 1 × 10 17 / cm 3 of silicon-doped GaN,
Light emitting layer 5 made of In 0.08 Ga 0.92 N with a film thickness of about 0.05 μm, film thickness of about 1.0 μm, hole concentration 5 × 10 17 / cm 3 , concentration 1 × 10 20
/ cm 3 magnesium-doped Al 0.08 Ga 0.92 N p-layer 61, film thickness about 0.2 μm, hole concentration 7 × 10 17 / c
A contact layer 62 made of magnesium-doped GaN with m 3 and a magnesium concentration of 2 × 10 20 / cm 3 is formed.
Then, the contact layer 62 is bonded to the layer 62.
A p electrode layer 7 made of Ni is formed. Further, a part of the surface of the high carrier concentration n + layer 3 is exposed, and an n electrode layer 8 made of Ni and bonded to the layer 3 is formed on the exposed portion.
【０００９】次に、この構造の発光ダイオード１００の
製造方法について説明する。上記発光ダイオード１００
は、有機金属化合物気相成長法( 以下「M0VPE 」と記
す) による気相成長により製造された。用いられたガス
は、NH3 とキャリアガスH2又はＮ2 とトリメチルガリウ
ム(Ga(CH3)3)（以下「TMG 」と記す) とトリメチルアル
ミニウム(Al(CH3)3)（以下「TMA 」と記す) とトリメチ
ルインジウム(In(CH3)3)（以下「TMI 」と記す) と、シ
ラン(SiH4)とシクロペンタジエニルマグネシウム(Mg(C5
H5)2)(以下「CP2Mg 」と記す）である。Next, a method of manufacturing the light emitting diode 100 having this structure will be described. Light emitting diode 100
Was produced by vapor phase growth by metalorganic compound vapor phase epitaxy (hereinafter referred to as "M0VPE"). The gas used was NH 3 and carrier gas H 2 or N 2 , trimethylgallium (Ga (CH 3 ) 3 ) (hereinafter referred to as “TMG”), and trimethylaluminum (Al (CH 3 ) 3 ) (hereinafter referred to as “TMA )), Trimethylindium (In (CH 3 ) 3 ) (hereinafter referred to as “TMI”), silane (SiH 4 ), and cyclopentadienyl magnesium (Mg (C 5
H 5 ) 2 ) (hereinafter referred to as “CP 2 Mg”).
【００１０】まず、有機洗浄及び熱処理により洗浄した
ａ面を主面とする厚さ100 〜400 μｍの単結晶のサファ
イア基板１をM0VPE 装置の反応室に載置されたサセプタ
に装着する。次に、常圧でH2を流速2 liter/分で反応室
に流しながら温度1100℃でサファイア基板１を気相エッ
チングした。First, a 100-400 μm thick single crystal sapphire substrate 1 having an a-plane as a main surface, which has been cleaned by organic cleaning and heat treatment, is mounted on a susceptor mounted in a reaction chamber of a M0VPE apparatus. Next, the sapphire substrate 1 was subjected to gas phase etching at a temperature of 1100 ° C. while flowing H 2 at a flow rate of 2 liter / min at normal pressure into the reaction chamber.
【００１１】次に、温度を 400℃まで低下させて、H2を
20 liter／分、NH3 を10 liter／分、TMA を 1.8×10-5
モル／分で供給してAlN のバッファ層２が約 500Åの厚
さに形成された。次に、サファイア基板１の温度を1150
℃に保持し、H2を20 liter／分、NH3 を10 liter／分、
TMG を 1.7×10-4ル／分、H2ガスにより0.86ppm に希釈
されたシランを20×10-8mol/分で30分供給して、膜厚約
2.2 μｍ、電子濃度 2×1018/cm3のシリコンドープのGa
N から成る高キャリア濃度ｎ+ 層３を形成した。[0011] Next, by lowering the temperature to 400 ° C., and H 2
20 liter / min, NH 3 10 liter / min, TMA 1.8 × 10 -5
Supplying at mol / min, an AlN buffer layer 2 was formed to a thickness of about 500 °. Next, the temperature of the sapphire substrate 1 was set to 1150
° C, H 2 at 20 liter / min, NH 3 at 10 liter / min,
About 1.7 × 10 -4 L / min of TMG and 20 × 10 -8 mol / min of silane diluted to 0.86 ppm with H 2 gas were supplied for 30 minutes to obtain a film thickness of about
2.2 μm, electron concentration 2 × 10 18 / cm 3 silicon-doped Ga
A high carrier concentration n + layer 3 made of N 2 was formed.
【００１２】次に、サファイア基板１の温度を1150℃に
保持し、N2又はH2を10 liter／分、NH3 を 10liter／
分、TMG を1.12×10-4モル／分、及び、H2ガスにより0.
86ppmに希釈されたシランを 1×10-8mol/分で、 4分供
給して、膜厚約3000Å、濃度1×1017/cm3のシリコンド
ープのGaN から成るｎ層４を形成した。Next, the temperature of the sapphire substrate 1 is maintained at 1150 ° C., N 2 or H 2 is 10 liter / min, and NH 3 is 10 liter / min.
Min, TMG 1.12 × 10 −4 mol / min, and H 2 gas to 0.
Silane diluted to 86 ppm was supplied at 1 × 10 −8 mol / min for 4 minutes to form an n-layer 4 made of silicon-doped GaN with a film thickness of about 3000 Å and a concentration of 1 × 10 17 / cm 3 .
【００１３】続いて、温度を850 ℃に保持し、N2又はH2
を20 liter／分、NH3 を 10liter／分、TMG を1.53×10
-4モル／分、及び、TMI を0.02×10-4モル／分で、6 分
間供給して0.05μｍのIn0.08Ga0.92N から成る発光層５
を形成した。Subsequently, the temperature was maintained at 850 ° C. and N 2 or H 2 was added.
20 liter / min, NH 3 10 liter / min, TMG 1.53 × 10
-4 mol / min and TMI at 0.02 × 10 -4 mol / min for 6 minutes to form a 0.05 μm In 0.08 Ga 0.92 N emitting layer 5
Was formed.
【００１４】続いて、温度を1100℃に保持し、N2又はH2
を20 liter／分、NH3 を 10liter／分、TMG を1.12×10
-4モル／分、TMA を0.47×10-4モル／分、及び、CP2Mg
を2×10-4モル／分で60分間導入し、膜厚約1.0 μｍの
マグネシウム(Mg)ドープのAl0.08Ga0.92N から成るｐ層
６１を形成した。ｐ層６１のマグネシウムの濃度は1×1
020/cm3である。この状態では、ｐ層６１は、まだ、抵
抗率108 Ωcm以上の絶縁体である。Subsequently, the temperature is maintained at 1100 ° C. and N 2 or H 2
20 liter / min, NH 3 10 liter / min, TMG 1.12 × 10
-4 mol / min, 0.47 × 10 -4 mol / min of TMA and CP 2 Mg
Was introduced at 2 × 10 −4 mol / min for 60 minutes to form a p-layer 61 made of Al 0.08 Ga 0.92 N doped with magnesium (Mg) and having a thickness of about 1.0 μm. The concentration of magnesium in the p-layer 61 is 1 × 1
It is 0 20 / cm 3 . In this state, the p layer 61 is still an insulator having a resistivity of 10 8 Ωcm or more.
【００１５】続いて、温度を1100℃に保持し、N2又はH2
を20 liter／分、NH3 を10 liter／分、TMG を1.12×10
-4モル／分、及び、CP2Mg を 4×10-4モル／分の割合で
4分間導入し、膜厚約0.2 μｍのマグネシウム(Mg)ドー
プのGaN から成るコンタクト層６２を形成した。コンタ
クト層６２のマグネシウムの濃度は 2×1020/cm3であ
る。この状態では、コンタクト層６２は、まだ、抵抗率
108 Ωcm以上の絶縁体である。Subsequently, the temperature was maintained at 1100 ° C. and N 2 or H 2 was added.
20 liter / min, NH 3 10 liter / min, TMG 1.12 × 10
-4 mol / min and CP 2 Mg at a rate of 4 × 10 -4 mol / min
This was introduced for 4 minutes to form a contact layer 62 made of GaN doped with magnesium (Mg) and having a thickness of about 0.2 μm. The magnesium concentration of the contact layer 62 is 2 × 10 20 / cm 3 . In this state, the contact layer 62 still has a resistivity
It is an insulator of 10 8 Ωcm or more.
【００１６】このようにして、図２に示す断面構造のウ
エハが得られた。次に、このウエハを、４５０℃で４５
分間、熱処理した。この熱処理により、コンタクト層６
２、ｐ層６１は、それぞれ、ホール濃度 7×1017/cm3，
5×1017/cm3、抵抗率 2Ωcm，0.8 Ωcm のｐ伝導型半
導体となった。このようにして、多層構造のウエハが得
られた。In this way, a wafer having a sectional structure shown in FIG. 2 was obtained. Next, this wafer is subjected to 45 ° C. at 45 ° C.
Heat treated for minutes. By this heat treatment, the contact layer 6
2, the p-layer 61 has a hole concentration of 7 × 10 17 / cm 3 ,
It became a p-conductivity type semiconductor with 5 × 10 17 / cm 3 and a resistivity of 2 Ωcm and 0.8 Ωcm. Thus, a wafer having a multilayer structure was obtained.
【００１７】次に、図３に示すように、コンタクト層６
２の上に、スパッタリングによりSiO2層９を2000Åの厚
さに形成し、そのSiO2層９上にフォトレジスト１０を塗
布した。そして、フォトリソグラフにより、図３に示す
ように、コンタクト層６２上において、高キャリア濃度
ｎ+ 層３に対するｎ電極層形成部位Ａ' のフォトレジス
ト１０を除去した。次に、図４に示すように、フォトレ
ジスト１０によって覆われていないSiO2層９をフッ化水
素酸系エッチング液で除去した。Next, as shown in FIG. 3, the contact layer 6
A SiO 2 layer 9 having a thickness of 2000 Å was formed on the No. 2 layer by sputtering, and a photoresist 10 was applied on the SiO 2 layer 9. Then, by photolithography, as shown in FIG. 3, on the contact layer 62, the photoresist 10 at the n-electrode layer forming portion A ′ for the high carrier concentration n + layer 3 was removed. Next, as shown in FIG. 4, the SiO 2 layer 9 not covered with the photoresist 10 was removed with a hydrofluoric acid-based etching solution.
【００１８】次に、フォトレジスト１０及びSiO2層９に
よって覆われていない部位のコンタクト層６２、ｐ層６
１、発光層５、ｎ層４を、真空度0.04Torr、高周波電力
0.44W/cm2 、BCl3ガスを10 ml/分の割合で供給しドライ
エッチングした後、Arでドライエッチングした。この工
程で、図５に示すように、高キャリア濃度ｎ+ 層３に対
するｎ電極層取出しのための孔Ａが形成された。Next, the contact layer 62 and the p-layer 6 in the portion not covered with the photoresist 10 and the SiO 2 layer 9 are formed.
1, light emitting layer 5, n layer 4, vacuum degree 0.04 Torr, high frequency power
0.44 W / cm 2 and BCl 3 gas were supplied at a rate of 10 ml / min for dry etching, and then Ar was used for dry etching. In this step, as shown in FIG. 5, a hole A for taking out the n-electrode layer for the high carrier concentration n + layer 3 was formed.
【００１９】次に、試料の上全面に、一様にNiを蒸着
し、フォトレジストの塗布、フォトリソグラフィ工程、
エッチング工程を経て、図１に示すように、高キャリア
濃度ｎ+ 層３及びコンタクト層６２に対するｎ電極層
８，ｐ電極層７を形成した。その後、上記の如く処理さ
れたウエハを各チップに切断して、発光ダイオードチッ
プを得た。Next, Ni is vapor-deposited uniformly on the entire surface of the sample, photoresist coating, photolithography process,
Through the etching process, as shown in FIG. 1, the n electrode layer 8 and the p electrode layer 7 for the high carrier concentration n + layer 3 and the contact layer 62 were formed. Then, the wafer treated as described above was cut into each chip to obtain a light emitting diode chip.
【００２０】このようにして形成された発光ダイオード
１００は、図６に示すように、リード２０３の上部の平
坦部２０３に取り付けられ、ｎ電極層８とリード２０１
がワイヤ２０４で接続され、ｐ電極層７とリード２０２
がワイヤ２０５で接続された後、レンズ２０６を形成す
るために樹脂成形される。一方、補償ダイオード３００
のアノード３０１がリード２０１に接続され、補償ダイ
オード３００のカソード３０２がリード２０２に接続さ
れている。The light emitting diode 100 thus formed is attached to the flat portion 203 above the lead 203 as shown in FIG. 6, and the n electrode layer 8 and the lead 201 are attached.
Are connected by a wire 204, and the p-electrode layer 7 and the lead 202 are connected.
Are connected by wire 205 and then resin-molded to form lens 206. On the other hand, the compensation diode 300
Is connected to the lead 201, and the cathode 302 of the compensation diode 300 is connected to the lead 202.
【００２１】これにより、発光ダイオード１００のｎ電
極層８が補償ダイオード３００のｐ伝導型の第２層に接
続され、ｐ電極層７がｎ伝導型の第１層に接続されるこ
とになる。よって、発光ダイオード１００にとって逆電
圧となるリード２０２に対してリード２０１が高い電圧
が印加される時、補償ダイオード３００が導通すること
になり、発光ダイオード１００には逆電圧が印加されな
いため、絶縁破壊は起こらない。As a result, the n-electrode layer 8 of the light emitting diode 100 is connected to the p-conduction type second layer of the compensation diode 300, and the p-electrode layer 7 is connected to the n-conduction type first layer. Therefore, when a high voltage is applied to the lead 202 with respect to the lead 202, which is a reverse voltage for the light emitting diode 100, the compensation diode 300 becomes conductive, and the reverse voltage is not applied to the light emitting diode 100, so that dielectric breakdown occurs. Does not happen.
【００２２】第２実施例 図７に示すように、補償ダイオード３１０を発光ダイオ
ード１００と共に樹脂成形し、レンズ２０６の中に組み
込んでも良い。 Second Embodiment As shown in FIG. 7, the compensation diode 310 may be resin-molded together with the light emitting diode 100 and incorporated in the lens 206.
【００２３】第３実施例 本実施例は、図８に示すように、発光ダイオード１１０
と補償ダイオード３２０とを同一基板、即ち、サファイ
ア基板１上に形成した例である。上述したように、バッ
ファ層２からコンタクト層６２まで形成する。その後、
ｎ電極層８を形成するための層６２から層４までのエッ
チング工程において、補償ダイオード３２０のｎ電極層
３２２を形成するための溝４１０を形成する。次に、補
償ダイオード３２０を発光ダイオード１１０から絶縁分
離するために、コンタクト層６２、ｐ層６１、発光層
５、ｎ層４、高キャリア濃度ｎ+ 層３、バッファ層２を
エッチングして溝４００を形成してサファイア基板１を
露出させる。 Third Embodiment In this embodiment, as shown in FIG.
In this example, the compensation diode 320 and the compensation diode 320 are formed on the same substrate, that is, the sapphire substrate 1. As described above, the buffer layer 2 to the contact layer 62 are formed. afterwards,
In the etching process from the layer 62 to the layer 4 for forming the n-electrode layer 8, the groove 410 for forming the n-electrode layer 322 of the compensation diode 320 is formed. Next, in order to insulate the compensation diode 320 from the light emitting diode 110, the contact layer 62, the p layer 61, the light emitting layer 5, the n layer 4, the high carrier concentration n + layer 3, and the buffer layer 2 are etched to form the groove 400. To expose the sapphire substrate 1.
【００２４】次に、第１実施例と同様に、発光ダイオー
ド１１０のｐ電極層７、ｎ電極層８、補償ダイオード３
２０のｐ電極層３２１、ｎ電極層３２２を形成する。こ
のようにして形成された発光素子は図９に示すようにリ
ード２０１の平坦部２０３に取り付けられる。そして、
発光ダイオード１１０のｐ電極層７はリード２０２にワ
イヤ２１０で電気的に接続され、補償ダイオード３２０
のｎ電極層３２２（カソード）はワイヤ２１１によりリ
ード２０２に電気的に接続される。同様に、発光ダイオ
ード１１０のｎ電極層８はリード２０１にワイヤ２１２
で電気的に接続され、補償ダイオード３２０のｐ電極層
３２１はワイヤ２１３によりリード２０１に電気的に接
続される。Next, as in the first embodiment, the p-electrode layer 7, the n-electrode layer 8 and the compensation diode 3 of the light emitting diode 110 are formed.
Twenty p-electrode layers 321 and n-electrode layers 322 are formed. The light emitting element thus formed is attached to the flat portion 203 of the lead 201 as shown in FIG. And
The p-electrode layer 7 of the light emitting diode 110 is electrically connected to the lead 202 by the wire 210, and the compensation diode 320
The n-electrode layer 322 (cathode) of is electrically connected to the lead 202 by the wire 211. Similarly, the n-electrode layer 8 of the light emitting diode 110 is connected to the lead 201 by the wire 212.
And the p-electrode layer 321 of the compensation diode 320 is electrically connected to the lead 201 by the wire 213.
【００２５】これにより、発光ダイオード１１０のｐ電
極層７は補償ダイオード３２０のｎ伝導型である高キャ
リア濃度ｎ+ 層３（第１層）に電気的に接続され、発光
ダイオード１１０のｎ電極層８は補償ダイオード３２０
のｐ伝導型であるコンタクト層６２（第２層）に電気的
に接続される。よって、発光ダイオード１１０にとって
逆電圧となるリード２０２に対してリード２０１が高い
電圧が印加される時、補償ダイオード３２０が導通する
ことになり、発光ダイオード１１０には逆電圧が印加さ
れないため、絶縁破壊は起こらない。As a result, the p-electrode layer 7 of the light-emitting diode 110 is electrically connected to the n-conducting high carrier concentration n + layer 3 (first layer) of the compensation diode 320, and the n-electrode layer of the light-emitting diode 110 is formed. 8 is a compensation diode 320
Is electrically connected to the contact layer 62 (second layer) of p conductivity type. Therefore, when a high voltage is applied to the lead 202 with respect to the lead 202, which is a reverse voltage for the light emitting diode 110, the compensation diode 320 becomes conductive, and the reverse voltage is not applied to the light emitting diode 110, so that the dielectric breakdown occurs. Does not happen.
【００２６】第４実施例 本実施例は、図１０に示すように、発光ダイオード１２
０のコンタクト層６２の上に補償ダイオード３３０を形
成した例である。上述したように、バッファ層２からコ
ンタクト層６２まで形成する。その後、補償ダイオード
３３０を形成するために、ｎ型のGaN から成る第１層３
３３とｐ型のGaN から成る第２層３３４を形成する。 Fourth Embodiment In this embodiment, as shown in FIG.
In this example, the compensation diode 330 is formed on the zero contact layer 62. As described above, the buffer layer 2 to the contact layer 62 are formed. Then, in order to form the compensation diode 330, the first layer 3 of n-type GaN is formed.
A second layer 334 of 33 and p-type GaN is formed.
【００２７】そして、第１実施例と同様な工程により、
エッチングした後、発光ダイオード１２０のｐ電極層
７、ｎ電極層８、補償ダイオード３３０のｐ電極層３３
１、ｎ電極層３３２を形成する。このようにして形成さ
れた発光素子は図１０に示すようにリード２０１の平坦
部２０３に取り付けられる。そして、発光ダイオード１
２０のｐ電極層７は補償ダイオード３３０のｎ電極層３
３２（カソード）にワイヤ２２０で電気的に接続される
と共にワイヤ２２１によりリード２０２に電気的に接続
される。同様に、発光ダイオード１２０のｎ電極層８は
リード２０１にワイヤ２２２で電気的に接続され、補償
ダイオード３３０のｐ電極層３３１はワイヤ２２３によ
りリード２０１に電気的に接続される。Then, by the same steps as in the first embodiment,
After etching, the p-electrode layer 7 and the n-electrode layer 8 of the light emitting diode 120 and the p-electrode layer 33 of the compensation diode 330 are formed.
1, the n-electrode layer 332 is formed. The light emitting element thus formed is attached to the flat portion 203 of the lead 201 as shown in FIG. And the light emitting diode 1
20 is the n-electrode layer 3 of the compensation diode 330.
32 (cathode) is electrically connected to the lead 202 by the wire 220 and is also electrically connected to the lead 202 by the wire 221. Similarly, the n-electrode layer 8 of the light emitting diode 120 is electrically connected to the lead 201 by the wire 222, and the p-electrode layer 331 of the compensation diode 330 is electrically connected to the lead 201 by the wire 223.
【００２８】これにより、発光ダイオード１２０のｐ電
極層７は補償ダイオード３３０のｎ伝導型である第１層
３３３に電気的に接続され、発光ダイオード１２０のｎ
電極層８は補償ダイオード３３０のｐ伝導型である第２
層３３４に電気的に接続される。よって、発光ダイオー
ド１２０にとって逆電圧となるリード２０２に対してリ
ード２０１が高い電圧が印加される時、補償ダイオード
３３０が導通することになり、発光ダイオード１２０に
は逆電圧が印加されないため、絶縁破壊は起こらない。As a result, the p-electrode layer 7 of the light emitting diode 120 is electrically connected to the n-conduction first layer 333 of the compensating diode 330, and the n electrode of the light emitting diode 120 is connected.
The electrode layer 8 is a p-type second electrode of the compensation diode 330.
Electrically connected to layer 334. Therefore, when a high voltage is applied to the lead 202 with respect to the lead 202, which is a reverse voltage for the light emitting diode 120, the compensation diode 330 becomes conductive, and the reverse voltage is not applied to the light emitting diode 120, so that the dielectric breakdown occurs. Does not happen.
【００２９】又、上記の第１〜第４の実施例において、
発光ダイオード１００、１１０、１２０に正方向にも静
電圧を印加して、その静電耐圧を測定した。500Vの静電
圧を印加しても絶縁破壊は見られなかった。これは、発
光層５とｎ+ 層３との間に、電子濃度が発光層やｎ+ 層
３よりも低いｎ層を設けたために、正方向の正電圧によ
る各層及び各層間での電界が小さくなるためと思われ
る。Further, in the above-mentioned first to fourth embodiments,
A static voltage was applied to the light emitting diodes 100, 110 and 120 in the positive direction and the electrostatic breakdown voltage was measured. No dielectric breakdown was observed even when a static voltage of 500 V was applied. This is because an n layer having an electron concentration lower than that of the light emitting layer or the n + layer 3 is provided between the light emitting layer 5 and the n + layer 3, so that an electric field between each layer and each layer due to a positive voltage in the positive direction is generated. It seems that it becomes smaller.
【００３０】上記のいずれの実施例においても、発光層
５のバンドギャップが両側に存在するｐ層６１とｎ層４
のバンドギャップよりも小さくなるようなダブルヘテロ
接合に形成されている。又、発光層５とｐ層６１の成分
比は、GaN の高キャリア濃度ｎ+ 層の格子定数に一致す
るように選択されている。又、上記実施例ではダブルヘ
テロ接合構造を用いたが、シングルヘテロ接合構造であ
っても良い。さらに、上記実施例は、発光ダイオードの
例を示したが、レーザダイオードであっても同様に構成
可能である。又、上記の第３、第４実施例において、補
償ダイオード３２０，３３０は３族窒化物半導体を用い
たが他の物質であっても良い。In any of the above embodiments, the p layer 61 and the n layer 4 in which the band gap of the light emitting layer 5 exists on both sides.
Is formed in a double heterojunction that is smaller than the band gap. The component ratio between the light emitting layer 5 and the p layer 61 is selected so as to match the lattice constant of the high carrier concentration n + layer of GaN. Further, although the double heterojunction structure is used in the above embodiment, a single heterojunction structure may be used. Further, in the above-described embodiment, the example of the light emitting diode is shown, but a laser diode can be similarly configured. Further, in the above third and fourth embodiments, the compensating diodes 320 and 330 use the group III nitride semiconductor, but other materials may be used.
【図１】本発明の具体的な第１実施例に係る発光ダイオ
ードの構成を示した構成図。FIG. 1 is a configuration diagram showing a configuration of a light emitting diode according to a first specific example of the present invention.
【図２】同実施例の発光ダイオードの製造工程を示した
断面図。FIG. 2 is a sectional view showing a manufacturing process of the light-emitting diode of the embodiment.
【図３】同実施例の発光ダイオードの製造工程を示した
断面図。FIG. 3 is a sectional view showing a manufacturing step of the light-emitting diode of the embodiment.
【図４】同実施例の発光ダイオードの製造工程を示した
断面図。FIG. 4 is a sectional view showing a manufacturing step of the light-emitting diode of the same embodiment.
【図５】同実施例の発光ダイオードの製造工程を示した
断面図。FIG. 5 is a sectional view showing the manufacturing process of the light emitting diode of the same embodiment.
【図６】第１実施例に係る発光素子の機構を示した構成
図。FIG. 6 is a configuration diagram showing a mechanism of the light emitting element according to the first embodiment.
【図７】第２実施例に係る発光素子の機構を示した構成
図。FIG. 7 is a configuration diagram showing a mechanism of a light emitting device according to a second embodiment.
【図８】第３実施例に係る発光素子の層構造を示した断
面図。FIG. 8 is a sectional view showing a layer structure of a light emitting device according to a third embodiment.
【図９】第３実施例に係る発光素子の機構を示した構成
図。FIG. 9 is a configuration diagram showing a mechanism of a light emitting device according to a third embodiment.
【図１０】第４実施例に係る発光素子の層構造及び機構
を示した構成図。FIG. 10 is a configuration diagram showing a layer structure and a mechanism of a light emitting device according to a fourth embodiment.
１００，１１０，１２０…発光ダイオード １…サファイア基板 ２…バッファ層 ３…高キャリア濃度ｎ+ 層 ４…ｎ層 ５…発光層 ６１…ｐ層 ６２…コンタトク層 ７…ｐ電極層 ８…ｎ電極層 ３００，３１０，３２０，３３０…補償ダイオード ３２１，３３１…ｐ電極層 ３２２，３３２…ｎ電極層 ２０１，２０２…リード ２１０，２１１，２１２，２１３…ワイヤ ２２０，２２１，２２２，２２３…ワイヤ100, 110, 120 ... Light emitting diode 1 ... Sapphire substrate 2 ... Buffer layer 3 ... High carrier concentration n + layer 4 ... N layer 5 ... Light emitting layer 61 ... P layer 62 ... Contact layer 7 ... P electrode layer 8 ... N electrode layer 300, 310, 320, 330 ... Compensation diode 321, 331 ... P electrode layer 322, 332 ... N electrode layer 201, 202 ... Leads 210, 211, 212, 213 ... Wire 220, 221, 222, 223 ... Wire
───────────────────────────────────────────────────── フロントページの続き (72)発明者 佐々 道成 愛知県西春日井郡春日町大字落合字長畑１ 番地 豊田合成株式会社内 (72)発明者 小出 典克 愛知県西春日井郡春日町大字落合字長畑１ 番地 豊田合成株式会社内 (72)発明者 柴田 直樹 愛知県西春日井郡春日町大字落合字長畑１ 番地 豊田合成株式会社内 (72)発明者 赤崎 勇 愛知県名古屋市西区浄心１丁目１番38− 805 (72)発明者 天野 浩 愛知県名古屋市名東区山の手２丁目104 宝マンション山の手508号 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Dosei Nasa, Nagachika, Ochiai, Kasuga-cho, Nishi-Kasugai-gun, Aichi 1st in Nagatahata Toyoda Gosei Co., Ltd. No. 1 in Toyoda Gosei Co., Ltd. (72) Inventor Naoki Shibata No. 1 Nagahata, Ochiai, Kasuga-cho, Nishikasugai-gun, Aichi Prefecture Within No. 1 Toyoda Gosei Co., Ltd. (72) Yuu Akasaki 1-3-1 Joshi, Nishi-ku, Aichi Prefecture 805 (72) Inventor Hiroshi Amano 2-104 Yamanote, Meito-ku, Nagoya, Aichi Prefecture Takara Condominium No.508, Yamanote
Claims (6)
に接続するｐ電極層、ｎ層及びそのｎ層に接続するｎ電
極層とから成る発光部を有した発光素子において、 前記発光部の前記ｐ電極層に電気的に接続されるｎ伝導
型の第１層と、前記発光部の前記ｎ電極層に電気的に接
続されるｐ伝導型の第２層とが接合された逆耐圧補償用
の補償ダイオードを設けたことを特徴とする３族窒化物
半導体発光素子。1. A light emitting device having a light emitting section comprising a p-layer made of a Group III nitride semiconductor, a p-electrode layer connected to the p-layer, an n-layer and an n-electrode layer connected to the n-layer, An n-conduction type first layer electrically connected to the p-electrode layer of the light-emitting portion and a p-conduction type second layer electrically connected to the n-electrode layer of the light-emitting portion were joined. A group III nitride semiconductor light-emitting device comprising a compensation diode for compensating reverse breakdown voltage.
されている基板と別の基板に形成され、前記発光部と前
記補償ダイオードとの電気的接続はリードにより行われ
ていることを特徴とする請求項１に記載の３族窒化物半
導体発光素子。2. The compensation diode is formed on a substrate different from the substrate on which the light emitting portion is formed, and the electrical connection between the light emitting portion and the compensation diode is performed by a lead. The Group III nitride semiconductor light emitting device according to claim 1.
されている基板と別の基板に形成され、前記発光部と前
記補償ダイオードとの電気的接続はリードにより行わ
れ、前記発光部と前記補償ダイオードとが同一樹脂で封
止されていることを特徴とする請求項２に記載の３族窒
化物半導体発光素子。3. The compensating diode is formed on a substrate different from the substrate on which the light emitting section is formed, and electrical connection between the light emitting section and the compensating diode is performed by a lead, and the light emitting section and the compensating diode are connected to each other. The group III nitride semiconductor light emitting device according to claim 2, wherein the compensating diode is sealed with the same resin.
されている基板と同一基板に形成されていることを特徴
とする請求項１に記載の３族窒化物半導体発光素子。4. The Group III nitride semiconductor light emitting device according to claim 1, wherein the compensation diode is formed on the same substrate as the substrate on which the light emitting section is formed.
部の層構造と同一に形成されており、前記発光部と前記
補償ダイオードとの間に絶縁分離の溝が形成され、前記
発光部と前記補償ダイオードとの電気的接続はリードワ
イヤにより行われいることを特徴とする請求項４に記載
の３族窒化物半導体発光素子。5. The layer structure of the compensating diode is the same as the layer structure of the light emitting section, and an insulating separation groove is formed between the light emitting section and the compensating diode, The group III nitride semiconductor light emitting device according to claim 4, wherein an electrical connection with the compensation diode is made by a lead wire.
ｐ層の上に積層された前記第１層とその第１層の上に積
層された第２層とで構成されていることを特徴とする請
求項４に記載の３族窒化物半導体発光素子。6. The compensating diode is composed of the first layer laminated on the p layer of the light emitting section and the second layer laminated on the first layer. The group III nitride semiconductor light emitting device according to claim 4.
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|---|---|---|---|
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| JP2007173830A (en) * | 2005-12-23 | 2007-07-05 | Ind Technol Res Inst | Light emitting device |
| JP2009152637A (en) * | 2005-01-27 | 2009-07-09 | Samsung Electro Mech Co Ltd | Gallium nitride-based light emitting element with led for protecting esd and its manufacturing method |
| JP2010524226A (en) * | 2007-04-02 | 2010-07-15 | エルジー イノテック カンパニー リミテッド | Light emitting device and manufacturing method thereof |
| KR101007137B1 (en) * | 2010-03-08 | 2011-01-10 | 엘지이노텍 주식회사 | Light emitting device, method of fabricating the light emitting device and light emitting device package |
| US8076694B2 (en) | 2005-05-02 | 2011-12-13 | Nichia Corporation | Nitride semiconductor element having a silicon substrate and a current passing region |
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1995
- 1995-11-21 JP JP32801195A patent/JP3705637B2/en not_active Expired - Fee Related
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009152637A (en) * | 2005-01-27 | 2009-07-09 | Samsung Electro Mech Co Ltd | Gallium nitride-based light emitting element with led for protecting esd and its manufacturing method |
| US8076694B2 (en) | 2005-05-02 | 2011-12-13 | Nichia Corporation | Nitride semiconductor element having a silicon substrate and a current passing region |
| JP2007129011A (en) * | 2005-11-02 | 2007-05-24 | Seiko Epson Corp | Optical semiconductor element |
| JP2007173830A (en) * | 2005-12-23 | 2007-07-05 | Ind Technol Res Inst | Light emitting device |
| JP2010524226A (en) * | 2007-04-02 | 2010-07-15 | エルジー イノテック カンパニー リミテッド | Light emitting device and manufacturing method thereof |
| KR101007137B1 (en) * | 2010-03-08 | 2011-01-10 | 엘지이노텍 주식회사 | Light emitting device, method of fabricating the light emitting device and light emitting device package |
| US8748917B2 (en) | 2010-03-08 | 2014-06-10 | Lg Innotek Co., Ltd. | Light emitting device and method thereof |
| JP2012023280A (en) * | 2010-07-16 | 2012-02-02 | Seiwa Electric Mfg Co Ltd | Semiconductor light-emitting element, light-emitting device, lighting device, display device, signal light and road information device |
| JP2015525973A (en) * | 2012-07-11 | 2015-09-07 | コーニンクレッカ フィリップス エヌ ヴェ | Reduction or elimination of nanopipe defects in III-nitride structures |
| US10193015B2 (en) | 2012-07-11 | 2019-01-29 | Lumileds Llc | Reducing or eliminating nanopipe defects in III-nitride structures |
| US10651340B2 (en) | 2012-07-11 | 2020-05-12 | Lumileds Llc | Reducing or eliminating nanopipe defects in III-nitride structures |
| US11152539B2 (en) | 2012-07-11 | 2021-10-19 | Lumileds Llc | Reducing or eliminating nanopipe defects in III-nitride structures |
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