JPH09147493A - Method for recording and reproducing digital signal and device therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the digital signal recording and reproducing device of an extended partial response(EPR) 4 or modified EPR 4 system, capable of high density recording and high speed processing. SOLUTION: A recording code is processed with calculation of 1/(1+D) mod 2 by a precoder 2 provided on the side of a recording circuit, and is then recorded on a storage medium. On the side of a reproducing circuit, an output of an EPR 4 or an MEPR 4 equalization circuit 8-1 is interleaved and converted into plural digital signal trains, which are then supplied in parallel to plural maximum likelihood decoding circuits 8-2-1 to 2. The state transitions of degenerated two conditions are dealt with the EPR 4 by each maximum likelihood decoding circuit. By this method, high density and high speed signal processing are realized.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal recording / reproducing method and device, and more particularly to a high density digital signal recording / reproducing method, a digital signal recording / reproducing device, and a digital signal recording / reproducing circuit for a magnetic recording medium.

[0002]

2. Description of the Related Art With the miniaturization of information storage devices represented by magnetic disks, it is required to improve the recording density on a recording medium. With the increase in calculation speed on the computer side using this recorded information, Therefore, there is an increasing demand for increasing the recording speed and reproducing speed of signals on a recording medium. From such a background, the recording / reproducing method in the magnetic disk field is, for example, a method of reproducing a recording signal by peak detection using a (1,7) run-length limited code with a coding rate of 2/3 as a recording code. As a recording code, a (0,4) run-length limited code with a coding rate of 8/9 is used, and a method of detecting a partial response class 4 (hereinafter referred to as PR4) is being used. Here, the coding rate m / n is defined as n bits of m-bit user data.
Means conversion to a bit recording code, (d, k)
The code reverses the recording magnetic field when the recording code is "1",
When it is "0", the so-called NRZ that maintains the state of the previous magnetic field
If I (Non Return to Zero Inverse) recording is assumed, the minimum number of "0" s allowed to exist between "1" and "1" of the code sequence is d, and the maximum number is k. It means that. For these technical features,
For example, Journal of Applied Magnetics of Japan, Vol. 18, No. 4, August 1994.
It is described in the month "PRML and Coding Techniques".

When information of a certain data transfer rate a bit / sec is input to a recording coding circuit (hereinafter referred to as a recording coder), the transfer rate of an output signal from the recording coder is: The speed is inversely proportional to the coding rate. For example, when (1-7) run-length limited coding with a coding rate of 2/3 is applied, the transfer speed increases by 1.5 times, and (0,4) run-length limited coding with a coding rate of 8/9 is applied. In that case, the transfer rate increases 1.125 times. However, the improvement of the transfer speed in the recording coder requires the speeding up of the circuit operation. Therefore, in order to reduce the speeding up condition of the circuit, an encoding method in which the coding rate is close to "1" is selected. Is desirable. This is one of the reasons why the 8/9 recording code is selected in recent digital signal recording / reproducing.

On the other hand, the method of detecting the reproduction signal is determined in consideration of the required band, the number of detection levels, the consistency with the maximum likelihood decoding, etc. from the viewpoint of speeding up the signal processing.
In the PR4 detection method, the response to the recording code “1” is “1, 0, −1” and the response to the recording code “0” is “−”.
1, 0, 1 "is equalized, so that a 1-bit (here, the coder output, that is, the bit interval in the digital recording signal sequence in the recording / reproducing system) delay operator is set to D. When expressed by, the PR4 detection method can be described as (1-D) (1 + D) = 1-D ² . In this case, in the maximum likelihood decoding circuit that processes the PR4 equalized output, since the bit and the signal delayed by 2 bits from the bit are calculated at each bit timing, the odd data and the even data are interleaved separately. Can be processed. Therefore, the processing of the detection circuit can be performed at half the data transfer rate, which is an extremely effective means when handling high-speed data. In addition to the PR4 system, various partial response systems have been proposed. For example, EPR4 (Extended Partial Response Cl
In the ass 4) method, the detection formula is given by (1 + D) (1-D ² ). Detection formula (1 + D) Modified those represented by the ^{(1-D 3) Extended Partial} Response Class
4 (hereinafter referred to as MEPR4) method.

Further, going back to the magnetization form of the magnetic recording medium, for high density recording, the direction perpendicular to the surface of the recording medium rather than the longitudinal recording system in which the magnetization reversal occurs along the track direction of the recording medium. It is said that the perpendicular recording method which causes the magnetization reversal is more advantageous. FIG. 2 shows a conceptual diagram of the longitudinal recording method and the vertical recording method. In the longitudinal recording method, recording magnetization remains in the traveling direction of the recording head, and information is recorded in such a manner that boundaries between front and rear magnetic domains face each other. Therefore, a repulsive force is generated in the adjacent magnetic zone, and the magnetization reversal interval T
If c is narrowed, it becomes difficult to record information. On the other hand, the perpendicular recording method has an advantage that stable remanent magnetization can be obtained even during high-density recording because a force attracting each other is generated in adjacent magnetic sections. Various proposals have been made for the equalization method in perpendicular magnetic recording, but from the viewpoint of signal processing, the fact that the differential waveform of the reproduction output in longitudinal recording is equal to the reproduction signal in perpendicular recording, PR4, which is the basic equalization method for longitudinal recording
Corresponding to the method (1-D ² ), in vertical recording − (1-2
The D ² + D ⁴ ) method is influential. This system can be interleaved like PR4. It should be noted that, just as there are EPR4 and MEPR4 as a method compatible with high density recording of PR4, as a high density recording method in perpendicular magnetic recording,
(1 + D) (1-2D ² + D ⁴ ) system, or-(1 + D)
There is a (1-2D ³ + D ⁶ ) system.

[0006]

However, the above-mentioned EP
Since both the R4 and MEPR4 systems have a term of (1 + D), interleave processing like PR4 cannot be performed.
For this reason, it is difficult to increase the speed of the reproducing circuit, and conventionally, it has been mainly applied to a medium-speed recording / reproducing apparatus for a magnetic disk. -(1 + D) (1-2D ² + D ⁴ ) in perpendicular magnetic recording
Scheme and - (1 + D) (1-2D 3 + D 6) Method same is true for.

The object of the present invention is generally ± (1 + D)
(1 ± k ₁ D ² ± k ₂ D ⁴ ± ... ± knY) (However, Y is 2 of D
nth power) or ± (1 + D) (1 ± k ₁ D ³ ± k ₂ D ⁶ ± ... ± k
nY) (where Y is the 3nth power of D) is adopted to provide a digital signal recording / reproducing method, a digital signal recording / reproducing apparatus, and a digital signal reproducing circuit, which facilitates maximum likelihood decoding processing. To do. Another object of the present invention is to apply a digital signal recording / reproducing method, a digital signal recording / reproducing apparatus, and a digital signal recording / reproducing device of high speed and high recording density by applying an EPR4 and MEPR4 system or an equalizing system corresponding to these in perpendicular magnetic recording. It is to provide a digital signal reproducing circuit. Another object of the present invention is to
In particular, the EPR4 and MEPR4 systems or the equalization system corresponding to these in the perpendicular magnetic recording is adopted,
An object of the present invention is to provide a digital signal recording / reproducing method, a digital signal recording / reproducing apparatus, and a digital signal reproducing circuit which can be interleaved by a maximum likelihood decoding circuit.

[0008]

In order to achieve the above object, according to the present invention, an equalization method corresponding to these in EPR4, MEPR4, or perpendicular magnetic recording has less equalization noise at high density. The feature is that the processing speed is increased at the expense of the improvement effect of the signal-to-noise ratio by the maximum likelihood decoding process.

In FIG. 3, the normalized linear density defined by the ratio of the half-value width T50 of the step response of the recording / reproducing system to the recording bit interval Tc is the horizontal axis, and the vertical axis is the equalization noise by the PR4 equalization method. 2 is a graph showing the magnitude of equalization noise of the EPR4 equalization method and the MEPR4 method with reference to. As you can see from the figure, as the recording density increases,
The equalization noise of EPR4 and MEPR4 is better than PR4. As can be seen from the above detection formula, EPR4 and MEP
Since the R4 method considers interference between signals over a long period, the effect of improving the signal-to-noise ratio is extremely large if the normal maximum likelihood decoding process is performed.

A feature of the digital signal recording / reproducing apparatus of the present invention is that the reproducing system includes an EPR4 system (or MEPR).
General formula represented by 4 methods) ± (1 + D) (1 ± k ₁ D ²
± k ₂ D ⁴ ± ... ± knY) (where Y is the 2nth power of D) or ± (1 + D) (1 ± k ₁ D ³ ± k ₂ D ⁶ ± ... ± knY) (where Y is D In the digital signal recording / reproducing apparatus provided with the equalizing means and the maximum likelihood decoding means represented by (3n powers), the recording system records the encoded signal sequence into "1 / (1 + D)".
-It is characterized by having a precoder for performing "mod 2" operation. With such a configuration, in the reproducing system, after equalizing the reproduced signal from the recording medium, the equalized outputs are interleaved for each predetermined bit to generate a digital signal of a plurality of columns, which are parallel to the maximum likelihood decoding means. Can be supplied. When the maximum-likelihood decoding processing means is composed of a plurality (for example, n) of maximum-likelihood decoding circuits, each maximum-likelihood decoding circuit may perform decoding processing at a speed of 1 / n of the bit rate. Maximum likelihood decoding Each circuit enables high-speed and high-density magnetic recording / reproduction.

For example, when the EPR4 system is adopted for the equalization circuit, the output of the equalization circuit is the result of (1 + D) (1-D ² ) operation on the precoder output of the recording system.
In the digital signal recording / reproducing apparatus of the present invention, the precoder is “1 / (1 + D) · mod for the recording code string.
Since 2 ”is calculated, the equalized output is (1-
D ² ). Therefore, the value of each bit is
As in the case of 4, it can be obtained from the equalized output of the bit and the equalized output delayed by 2 bits from that, and the interleaved maximum likelihood decoding processing that is divided into an odd bit string and an even bit string becomes possible. By interleaving the inputs, the maximum-likelihood decoding circuit of EPR4 described above becomes a simplified one degenerated into two states. Even when adopting an equalizing circuit of MEPR4 system and an equalizing system corresponding to these in perpendicular magnetic recording, by applying the same precoder as in the case of the above EPR4 system to the recording system, the maximum likelihood decoding is performed with the interleaved signal sequence. It can be processed.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a signal system diagram of a recording / reproducing apparatus for a magnetic disk according to the present invention. 1 is an encoder for converting m-bit binary information given as input data into an n-bit recording code, 2 is a precoder, 3 is a recording amplifier circuit, 4 is a magnetic recording head, 5 is a reproducing head, and 6 is recording. A medium (magnetic disk), 7 is an amplifier circuit, and 8 is a reproduction processing circuit. The reproduction processing circuit includes a reproduction equalization circuit 8-1 and
It comprises maximum likelihood decoding (ML) circuits 8-2-1 and 8-2-2 and an output circuit 8-3 for combining and outputting the interleaved decoding results. If the reproduction processing circuit 8 is provided as an integrated circuit IC chip on the same semiconductor substrate, the assembly and configuration of the device can be facilitated.

The encoder 1 converts input data into a predetermined recording code. Since the recording code is not limited in principle in the present invention, the conventional 8/9 recording code or the (1-7) run code is used. Length limited codes can be used. In this embodiment, for example, the 8/9 recording code is used. The recording code string and the signal waveform output from the encoder 1 are shown in FIG.

The precoder 2 is for performing an operation of "1 / (1 + D) .mod 2" on the recording code string output from the encoder 1, and as shown in FIG.
Bit delay circuit 21 and exclusive OR circuit 2
It is realized in 2. By passing through the precoder 2, the recording code string and the signal waveform shown in FIG. 4A are converted as shown in FIG. 4B. The recording / amplifying circuit 3, the magnetic recording head 4, the reproducing head 5, the recording medium 6, and the reproducing / amplifying circuit 7 are not particularly limited in the present invention, and therefore conventionally known ones can be applied. In this embodiment, the information equalized by 1 / (1 + D) · mod 2 in the recording system and stored in the reproduction equalization circuit 8 is equivalent to (1 + D) (1-D2) in the EPR4. . EP
Although various methods can be considered for the specific configuration method of the R4 equalization circuit, one example of the circuit configuration suitable for high-speed recording is shown in FIGS.

In FIG. 5, 8-1-1 is an amplifier having a variable amplification function for amplifying the reproduction output signal and controlling the output amplitude envelope to a constant value, and 8-1-2 is a reproduction equalization circuit. . The reproduction equalization circuit 8-1-2 includes the recording head 4, the recording medium 6, the reproduction head to the reproduction equalization circuit 8-1-2.
The transmission characteristics of the signal processing system including the signal are (1 + D) (1-D2)
The equalizing circuit characteristic is set as given by. The waveform of the equalized signal output from the reproduction equalization circuit 8-1-22 is shown in FIG. 8-1-3a, 8-1-3
b alternately takes in the output of the reproduction equalization circuit 8-1-2, and as shown in (C1) and (C2) of FIG. 4, digital signals (a group of odd data and a group of even data) whose transmission speed is half. Group)
It is an A / D converter for converting to. The two digital signal sequences (odd data group and even data group) C1 and C2 output from these A / D converters are the maximum likelihood decoding circuit 8-2-
1 or 8-2-2 and the clock extraction circuit 8-1-4. The recovered clock generated in the clock extraction circuit 8-1-4 is supplied to the A / D converter, the maximum likelihood decoding circuits 8-2-1 and 8-2-2, and other circuits.

The maximum likelihood decoding circuits are 8-2-1, 8-2-2,
The digital signal sequences C1 and C2 of the odd data group and the even data group supplied from the A / D converters 8-1-3a and 8-1-3b, respectively, are transferred to the equalizing circuit 8-1. Maximum likelihood decoding is performed at half speed. The output circuit 8-3 synthesizes the code strings identified by these maximum likelihood decoding circuits, and interfaces with the recording / reproducing processing circuit and the upper circuit section.
Processing (conversion from serial format data to parallel data in word units). Incidentally, in order to convert the data into parallel data, it is necessary to detect a synchronization signal contained in the data and establish word synchronization, but since these circuit parts are not directly related to the present invention, It is omitted from the drawing.

The structure shown in FIG. 5 has the advantage that an A / D converter with a low conversion speed can be used, but requires two A / D converters. FIG. 6 shows a variable amplifier 8-1-
The circuit configuration is such that the output of No. 1 is converted into a digital signal by the A / D converter 8-1-3c which operates at high speed, and then input to the digital filter type reproduction equalization circuit 8-1-5. The output of the equalizing circuit 8-1-5 is divided into an odd data group C1 and an even data group C2, and the maximum likelihood decoding circuit 8-2-
1, 8-2-2. A clock extraction circuit 8-1-4 generates a reproduced clock from the odd-numbered and even-numbered data groups. As another modified example of the reproduction processing circuit 8, a mode in which an analog filter for performing EPR4 equalization is arranged immediately after the variable amplification circuit 8-1-1 and thereafter A / D conversion processing is performed can be considered. In this case, the number of quantization bits of the A / D converter is small, and thus the speed is easily increased.

In the configuration of the maximum likelihood decoders 8-2-1 and 8-2-2, a trellis diagram obtained by installing a precoder for performing "1 / (1 + D) .mod 2" operation in the recording system. It is necessary to consider the peculiarities of. For example, in (A) of FIG.
Focusing on the correspondence between the marked odd-numbered recording codes and the equalized output shown in FIG. 6C, for example, it corresponds to the change “0 → 0” from the first recording code to the third recording code. The equalization output is "+2", "-1" corresponding to the change "0 → 1" from the third to the fifth, and "1 →" from the fifth to the seventh.
It is “+1” corresponding to “0”.

The trellis diagram of FIG. 7 is obtained by considering the correspondence between the transition of the recording code and the equalized output in all cases. This means that the maximum-likelihood decoding circuit of the present invention performs 2-state maximum-likelihood decoding as in the case of applying the conventional PR4, although the EPR4 is adopted. The EPR4 equalization method is intended to perform 8-state maximum likelihood decoding by originally distinguishing 5 values, thereby obtaining a high signal-to-noise ratio. On the other hand, in the present invention, as shown in FIG. 7, since the trellis diagram is degenerated into two states, the improvement of the signal-to-noise ratio is equivalent to that of the conventional PR4ML (PL4 Maximum Likelihood). Of course, the ML circuit may have the same configuration as the conventional PR4ML. From this, it can be said that one feature of the present invention is that the EPR4 system is applied to the reproduction equalization and the two-state maximum likelihood decoding equivalent to PR4ML is used for the maximum likelihood decoding process.

FIG. 8 shows, as another embodiment of the present invention, a signal system diagram when the MEPR4 system is adopted for the equalization circuit. Elements having the same functions as those in FIG. 1 are denoted by the same reference numerals. The MEPR4 equalization system is applied to the reproduction equalization circuit 8-1 ', and the equalized outputs are interleaved every 3 bits, and three ML processing circuits 8-2-1 to 8-2-1 operate in parallel.
It is sequentially supplied to 8-2-3. The precoder 2 is represented by the arithmetic expression of 1 / (1 + D),
This is the same as when the EPR4 system is adopted.

As can be understood from the above description, according to the above-described embodiment of the present invention, although the improvement of the signal-to-noise ratio is inferior to the conventional EPR4 and MEPR4, high speed processing is possible and high density recording is possible. It is possible to obtain a higher signal-to-noise ratio than in PR4. The above characteristics are effective, for example, for a magnetic disk device that requires high-speed recording while at the same time providing a certain margin for spacing between the magnetic disk and the head to improve reliability. For high-density recording, the spacing between the magnetic disk and the head may be narrowed, but the narrow spacing easily causes mechanical damage on the recording medium or the recording / reproducing head. From the standpoint of reliability of the disk device, it is important to allow a certain amount of spacing. However, if the spacing is widened, the normalized linear density becomes high. In recent years, for example, heads with excellent sensitivity, such as heads using magnetoresistive elements, have been developed, and therefore there is often a margin in the signal-to-noise ratio even if the standardized linear density is high. According to the present invention, it is possible to provide a highly reliable recording / reproducing system for a magnetic disk, which has a practical signal-to-noise ratio, is adaptable to high speed and high density. Further, when the recording / reproducing signal processing system described above is implemented as an LSI, the conventional PR4
Compared with the circuit configuration of the ML system, the precoder and the equalization circuit portion are different, but the circuit scale is the same and the cost is not so high. In addition, a circuit unit having the same function is shared and the operation mode is switched, so that the LSI can also be used as PR4ML.

[0022]

According to the present invention, EPR4 and MEPR4
The maximum likelihood decoding process for equalized output represented by
By applying the leave system, a digital signal recording / reproducing apparatus suitable for high density recording and high speed recording / reproducing can be realized.

[Brief description of the drawings]

FIG. 1 is a signal system diagram showing a first embodiment of a recording / reproducing system of a digital signal recording / reproducing apparatus according to the present invention.

FIG. 2 is a diagram conceptually showing a difference between longitudinal recording and vertical recording.

FIG. 3 is a characteristic diagram for comparing PR4, EPR4, and MEPR4.

FIG. 4 is a signal waveform diagram in the first embodiment.

5 is a diagram showing an example of a configuration of a reproduction equalization circuit 8-1 in FIG.

6 is a diagram showing another configuration example of the reproduction equalization circuit 8-2 in FIG.

FIG. 7 is a diagram showing state transitions of the maximum likelihood decoding circuit in the embodiment of FIG.

FIG. 8 is a signal system diagram showing a second embodiment of the recording / reproducing system of the digital signal recording / reproducing apparatus according to the present invention.

[Explanation of symbols]

1 ... Encoder, 2 ... Precoder, 3 ... Recording amplifier circuit, 4 ...
Magnetic recording head, 5 ... Reproducing head, 6 ... Recording medium, 7 Reproducing amplifier circuit, 8 ... Reproducing processing circuit, 8-1 ... Reproducing equalizing circuit, 8-2-1 to 3 ... Maximum likelihood decoding circuit, 8-3 … Output circuit.

Claims (14)

[Claims] 1. When a 1-bit delay operator of a digital recording code is represented by D, the digital recording code is 1 / (1 + D) in a recording system.
-Mod2 operation is performed and then recorded on the recording medium, and the reproduction signal from the recording medium is (1 ±
D) (1 ± k ₁ D ² ± k ₂ D ⁴ ......) or (1 + D) (1
± k ₁ D ³ ± k ₂ D ⁶ ± ...) Equalization processing is performed, and a digital signal recording / reproducing method characterized by the above-mentioned. 2. In the reproducing system, an equalizing process corresponding to (1 + D) (1-D ² ) or (1 + D) (1-D ³ ) is performed on the reproduced signal from the recording medium. The digital signal recording / reproducing method according to claim 1, which is characterized in that. 3. In a reproducing system, the equalized signal is interleaved for every predetermined bit to be converted into a plurality of digital signal strings, and maximum likelihood decoding processing is performed in parallel for the plurality of digital signal strings. Claim 1 characterized by the above.
Alternatively, the digital signal recording / reproducing method according to claim 2. 4. The digital signal recording / reproducing method according to claim 3, wherein the maximum likelihood decoding processing is performed by maximum likelihood decoding processing means for determining a likelihood based on a state transition between two states. 5. When the 1-bit delay operator of the encoded digital recording code is represented by D, the digital recording code is 1 / (1+) in the recording system.
D) · Mod2 is calculated and recorded on the recording medium, and in the reproducing system, the reproduced signal waveform from the recording medium is equalized by the equalization method corresponding to the extended partial response class 4 or its modification, and the equalized output is output. After converting into a plurality of digital signal sequences interleaved for each predetermined bit and performing maximum likelihood decoding processing for each digital signal sequence,
A digital signal recording / reproducing method characterized by synthesizing a plurality of maximum likelihood decoded signals. 6. The digital signal recording / reproducing method according to claim 5, wherein the digital recording code is obtained by converting 8-bit data into a 9-bit digital code. 7. A recording system for recording a digital signal on a magnetic storage medium via a recording head, and a reproduction system for identifying a digital recording signal from a reproduction signal read from the magnetic storage medium by a reproduction head. In the digital signal recording / reproducing apparatus consisting of, the recording system calculates 1 / (1 + D) .multidot.mod2 with respect to the digital recording code string to be supplied to the recording head (where D is 1 bit of the digital recording code). The reproduction system has (1 ± D) (1 ± k ₁ D ² ± k ₂ D ⁴ ......) for the reproduction signal from the recording medium. Or (1+
D) Equalization means for performing equalization processing corresponding to (1 ± k ₁ D ³ ± k ₂ D ⁶ ± ...) And outputting as a plurality of digital signal sequences interleaved for each predetermined bit, A maximum likelihood decoding processing means for processing digital signals of a plurality of columns in parallel and identifying a digital recording signal, and a plurality of digital recording signal sequences output from the maximum likelihood decoding processing means are combined. And a digital signal recording / reproducing device. 8. The equalizer means (1 + D) (1-D ² ) or (1 + D) for the reproduced signal from the recording medium.
D) (a digital signal recording and reproducing apparatus according to claim 7, wherein the 1-D ³⁾ to perform the corresponding equalization process. 9. An encoding means for the recording system to convert an m-bit (m is an integer) digital code into an n-bit (n is an integer of n> m) digital code and supply it to the precoder. 9. The digital signal recording / reproducing apparatus according to claim 7, further comprising: an amplifier circuit for amplifying the output of the precoder and supplying the amplified output to the recording head. 10. The digital signal recording / reproducing apparatus according to claim 9, wherein the maximum likelihood decoding processing means determines the likelihood of each of the digital signal sequences by a state transition of two states. 11. A reproduction signal from a recording medium is (1 ±
D) (1 ± k ₁ D ² ± k ₂ D ⁴ ......) or (1 + D) (1
± k ₁ D ³ ± k ₂ D ⁶ ± ...) Equalization means for performing equalization processing corresponding to each of the predetermined bits and outputting as a plurality of columns of digital signal sequence interleaved, It has maximum likelihood decoding processing means for processing digital signal sequences in parallel to identify digital recording signals, and means for synthesizing a plurality of digital recording signal sequences output from the maximum likelihood decoding processing means. A digital signal reproducing circuit characterized by the above. 12. The equalizer means (1 + D) (1-D ² ) or (1) for a reproduction signal from the recording medium.
+ D) (digital signal reproduction circuit according to claim 11, characterized in that the corresponding equalization processing on 1-D ^3). 13. Encoding means for the recording system to convert an m-bit (m is an integer) digital code to an n-bit (n is an integer of n> m) digital code and supply it to the precoder. 13. The digital signal reproducing circuit according to claim 11 or 12, further comprising: an amplifying circuit for amplifying an output of the precoder and supplying the amplified output to the recording head. 14. The digital signal reproducing circuit according to claim 13, wherein the maximum likelihood decoding processing means makes a likelihood determination for each of the digital signal sequences by a state transition of two states.