JPH0883208A - Memory access controller - Google Patents

Abstract

PURPOSE: To eliminate unnecessary margin and speed up memory access by controlling the output of a wait signal to a central processing unit on the basis of the monitoring result of a monitor means. CONSTITUTION: The monitor means (comparator) 112 monitors a memory access control signal which is outputted from this device to a memory. Then a wait control means (JK flip-flop) 123 controls the output of the wait signal to the central processor on the basis of the monitoring result of the monitor means so that the wait signal is outputted to the central processor (CPU) when the timing of variation of the memory access control signal monitored by the monitor means 112 is delayed behind specific timing, but not outputted when not. Consequently, memory access control is performed in timing corresponding to the delay of an actual memory access control signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory access control device for controlling access to a memory of an information processing device such as a computer or a peripheral device.

[0002]

2. Description of the Related Art Conventionally, in this type of memory access control device, an address signal, an address strobe signal,
The timing design of the change of the memory access control signal such as the chip select signal is performed until the memory access control signal is input from the central processing unit such as CPU and is output to the memory to be accessed through the memory access control unit. It is designed considering the maximum delay time.

When the connected memory is variable,
As the number of memory connections increases and the address space of the memory to be accessed increases, the delay time of the memory access control signal increases, but even in this case, the timing design for changes in the memory access control signal is the maximum. It is designed considering the maximum delay time corresponding to the number of memory expansions.

[0004]

Therefore, conventionally, as described above, the timing of the change of the memory access control signal is designed in consideration of the maximum delay time (delay). However, it is necessary to always apply a wait corresponding to the maximum delay time that can occur only to the central processing unit, resulting in a long memory access cycle.

The present invention has been made under such a background, and an object thereof is to provide a memory access control device capable of accessing a memory at high speed.

[0006]

To achieve the above object, the present invention provides a memory access control device for outputting a memory access control signal to a memory to be accessed under the control of a central processing unit. A monitor means for monitoring the memory access control signal output to the memory and a wait control means for controlling the output of the wait signal to the central processing unit based on the monitoring result by the monitor means are provided.

[0007]

The monitor means monitors the memory access control signal output from the device to the memory. The wait control means outputs a wait signal to the central processing unit when the timing of change of the memory access control signal monitored by the monitor means is behind the predetermined timing, and when not delayed, By controlling the output of the wait signal to the central processing unit based on the monitoring result by the monitoring means such as not outputting the wait signal, the memory access control is performed at the timing corresponding to the delay of the actual memory access control signal. By doing so, a wasteful margin considering the maximum delay time (delay) is eliminated to speed up memory access.

[0008]

【Example】

[First Embodiment] FIG. 1 is a circuit diagram showing the structure of a memory access control apparatus according to the first embodiment of the present invention. This memory access control device is a DRAM access control device for controlling access to DRAM from a central processing unit (CPU) such as a microcomputer realized by an ASIC such as a gate array.

In FIG. 1, 101 is an address signal input from the CPU, 102 is an input buffer of the present gate array (memory access control device), and 103 is an address of the address signals necessary for decoding the DRAM space. Signal, 104 is a row address signal used as a row address of the DRAM, and 105 is the DRAM
A column address signal used as a column address, 106 is a selector for switching the row address of 104 and the column address of 105 to output to the DRAM, 107 is a selected DRAM address signal, and 108 is a DRAM address externally. An output buffer for driving to the DRAM connected to the output terminal 109 is an address output signal output from the output buffer 108 to the DRAM.

Reference numeral 110 is an input buffer functioning as an input means for monitoring the address output signal 109 inside the memory access control apparatus, and 111 is the input buffer 11.
DRAM address input via 0, 112 is co
A comparator that compares the lumn address 105 with the monitored DRAM address 111, and outputs a match signal when they match.

Reference numeral 113 denotes a decoder that decodes the address signal 103 for decoding when the DRAM space is accessed by the CPU and outputs the decoded signal to the DRAM. Reference numeral 114 denotes an address strobe signal input from the CPU and indicating access start. To the inside of the memory access control device, and 115 is the decoder 11
3 and the decoded signal output from the input buffer 114.
D by the address strobe signal input via
An AND gate that outputs a signal indicating the timing of RAM access, 116 is a RAS (Row Address)
Strobe) is a JK flip-flop that generates the timing of the signal.

Reference numeral 117 is an output buffer for outputting the RAS signal to the DRAM, and 118 is an input means for inputting the RAS signal into the memory access control device in order to monitor the RAS signal output to the DRAM. Functioning input buffer, 119 from RAS signal to CA
This is a delay circuit for taking a hold time up to the S (Column Address Strobe) signal. 1
20 is an AND gate that determines the output of the CAS signal, 12
Reference numeral 1 is an output buffer that drives the CAS signal to the DRAM, and 122 is an input buffer that functions as an input unit for monitoring the CAS signal output to the DRAM.

Reference numeral 123 determines whether the input CAS signal is earlier or later than a predetermined timing, outputs a ready signal (RDY signal) to the CPU if it is earlier, and outputs C if it is later.
It is a JK flip-flop that creates a wait state without outputting the RDY signal to PU. The JK flip-flop 123 functions as a determination unit and a weight control unit, which are constituent elements of the present invention.

Reference numeral 124 is an output buffer for driving the RDY signal to the CPU, and 125 is an input buffer for inputting a clock from the CPU to internal JK flip-flops 116 and 123.

FIG. 2 is a time chart showing the basic operation timing of this embodiment. However, in this time chart, the actual signal delay is not considered and the ideal operation timing is not considered, and neither write nor read data is considered.

In FIG. 2, an address input is an address input from the CPU, an address strobe is a signal indicating the start of access from the CPU, and this address strobe is output for one clock from the first clock. In the decoder output, when the address input is decoded by the decoder 113, the address output from the CPU is DRAM.
The signal is output if it is in the mapped address space of. When both the address strobe signal and the output of this decoder are output, the JK flip-flop 116 is passed through the AND gate 115 at the next rising edge of the clock.
Is set.

The output signal of the JK flip-flop 116 is output to the DRAM as an RAS signal via the output buffer 117. The address output to the DRAM is initially the row selected by the selector 106.
The address 104 is output, and the output buffer 117
Drive the RAS signal, it is input to the delay circuit 119 via the monitor input buffer 118, and the delay circuit 119 selects the signal with a certain signal delay.
06 and the AND gate 120.

As a result, the selector 106 is
The column address 105 is output, and the column address 105 is output to the DRAM as the address output 109 via the output buffer 108. When the address output 109 is switched to the column address, the column address is changed to the input buffer 1 for monitoring.
It is input to the comparator 112 via 10. Comparator 112
, The column address 103 from the input buffer 102 is input in advance, and a match signal is output when the column address 103 matches the actual driven column address from the output buffer 108.

This match signal indicates that the column address has been correctly driven to the DRAM, and C
This indicates that the timing is when the AS signal can be driven. That is, the match signal is input to the AND gate 120 to turn on the AND gate 120, and the output buffer 12
The CAS signal is output to the DRAM through the 1.

The CAS signal is monitored by the input buffer 122 and input to the J input of the JK flip-flop 123, and the JK flip-flop 123 is set at the next rising edge of the clock. The JK flip-flop 123 functions as a determination unit that determines whether or not the output of the CAS signal is in time for the next clock.
If it is in time, it is set because "H" is input to the J input, and if it is not in time, it is not set because "L" is input to the J input.

The output of the JK flip-flop 123 is output to the C as an RDY signal via the output buffer 124.
It is output to the PU, and the CPU sends RDY at the next clock.
If the signal is output, the memory cycle is ended, and if it is not output, the memory cycle is not ended. Therefore, the JK flip-flop 123 also functions as weight control means. The timing of FIG. 2 shows the case where the CAS output is in time.

Whether the CAS output is actually in time for a predetermined timing is determined by the JK output in synchronization with the clock.
The signal path from the setting of the flip-flop 116 to the turning on of the monitor signal of the CAS output, that is, the output buffer 117 → input buffer 118 → selector 106 → output buffer 108 → input buffer 110
→ comparator 112 → AND gate 120 → output buffer 1
21 → sum of signal delays of the input buffer 122.

This signal delay usually has a considerable variation due to variations in the semiconductor manufacturing process, operating temperature, voltage variations, and other environmental factors. Therefore, when designing a timing circuit, conventionally, the maximum signal delay has always been assumed for reliable operation.
However, the maximum signal delay usually occurs almost rarely, and these design margins are actually useless margins in most cases, which hinders the design of high-speed circuits.

The present invention provides a solution to this problem, eliminates wasted design margins and, as noted above, weights only when the actual signal delay occurs.

FIG. 3 is a time chart in the case where the CAS output ends the memory cycle without waiting in time for the judgment timing in this embodiment. The waveform of each part of the path and each delay are d1.
~ D9. That is, when Σdk is earlier than the determination timing T3, the JK flip-flop 123 is set at the determination timing T3, the RDY signal is output, and the memory cycle ends in 3 clocks. The fact that the RDY signal is output in this way means to the CPU
It means that no weight was applied.

FIG. 4 is a time chart in the case where the CAS output is waited for the judgment timing and the memory cycle is completed in this embodiment, and the waveform of each part of the path and each delay are e1.
~ E9. That is, Σek is the determination timing T
If it is later than 3, the JK flip-flop 123 is not set at the determination timing T3 but is set at the next clock TW, and the RDY signal is output. Therefore, the CPU is 4
The clock completes the memory cycle. This is CP
For U, this means that a wait of one clock has been applied.

As described above, the actually driven signal is input and monitored, the delay of the monitored signal is judged at a certain timing, and a weight is applied based on the judgment result, so that the actual delay is calculated. By performing memory access control at a timing according to the above and eliminating a useless margin considering the conventional maximum delay time, it is possible to speed up memory access.

[Second Embodiment] A second embodiment is a ROM or S
It is an example of a memory access control device that controls access to a RAM. Usually, in ROMs and SRAMs, the access time from the determination of the address signal is determined, and since it is easy to add memory, etc., the number of connected memories is often variable. However, when the number of connections increases, the sum of the input load capacities of the memory device increases, and the delay of the memory access control signal increases. Therefore, it is considered to be most effective in applying the memory access control device according to the present invention.

FIG. 5 is a circuit diagram of a memory access control device according to the second embodiment. In FIG. 5, 201 is a CP
Address signal from U, 202 is input buffer for inputting address signal, 203 is internal address bus, 204 is output buffer for address output, 205 is address output,
Reference numeral 206 denotes an input buffer that functions as an input unit for monitoring the address output inside the memory access control device, 207 is a comparator, 208 is a decoder, 209 is an AND gate, and 210 is an output buffer for a chip select (CS) signal. , 211 is a JK flip-flop, 212 is an output buffer for outputting the RDY signal to the CPU, 2
Reference numeral 13 is an input buffer for the clock signal.

When the CPU starts a memory cycle and the address signal 201 is input, the R signal is passed through the input buffer 202, the internal address bus 203, and the output buffer 204.
The address signal 205 is output to the OM or SRAM (hereinafter referred to as memory). Address signal 205
Indicates that the delay time greatly changes depending on the memory capacity (load capacity).

The address signal 205 is input to the comparator 207 via the input buffer 206. Further, the address signal from the input buffer 202 is previously input to the comparator 207. Therefore, the comparator 207 uses the address signal from the input buffer 202 and the output buffer 20.
When the address signal 205 from 4 coincides, that is, when the address output is determined to be an accurate value, the coincidence signal is output.

At this time, the decoder 208 outputs a decode signal if the mapped address of the external memory (ROM, SRAM) is input. Then, the chip select signal is output via the AND gate 209 and the output buffer 210. The output of the AND gate 209 greatly changes due to the delay of the address output 205, so that the J functioning as a timing determination means
The K flip-flop 211 samples the signal and sets it if it is earlier than the clock signal that determines the timing, and if it is later, it is delayed by one clock.

That is, the JK flip-flop 211
Is set when the address output 205 is earlier than the clock signal, and the RDY signal is output to C through the output buffer 212.
By not outputting a wait by outputting to the PU, if the address output 205 is later than the clock signal, avoid setting it by the current clock signal, and not outputting the RDY signal to the CPU via the output buffer 212. Apply weight.

In other words, even when the delay of the memory access control signal changes in accordance with the change in the number of connected memories as in the second embodiment, as in the first embodiment,
By inputting and monitoring the actually driven signal, judging the delay of the monitored signal at a certain timing, and applying a wait based on the judgment result,
The memory access control can be performed at the timing according to the actual delay, and by eliminating the unnecessary margin considering the maximum delay time (delay) in the past,
It is possible to speed up memory access.

[0035]

As described above, according to the present invention,
The memory access control signal output from the device to the memory is monitored, and a wait signal is output to the central processing unit when the timing of change in the monitored memory access control signal is behind the predetermined timing. The timing corresponding to the delay of the actual memory access control signal is controlled by controlling the output of the wait signal to the central processing unit based on the monitoring result by the monitoring means, such as not outputting the wait signal when it is not delayed. By performing the memory access control by eliminating the useless margin considering the conventional maximum delay time, it is possible to speed up the memory access.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of a memory access control device according to a first embodiment of the present invention.

FIG. 2 is a time chart for explaining a basic operation of the memory access control device according to the first embodiment.

FIG. 3 is a time chart showing the operation timing when the memory access control device according to the first embodiment is not weighted.

FIG. 4 is a time chart showing the operation timing when a wait is applied to the memory access control device according to the first embodiment.

FIG. 5 is a circuit diagram showing a configuration of a memory access control device according to a second embodiment of the present invention.

[Explanation of symbols]

102, 110, 114, 118, 125, 202, 2
06, 213 ... Input buffer 106 ... Selector 108, 117, 121, 124, 204, 210, 2
12 ... Output buffer 112, 207 ... Comparator 113, 208 ... Decoder 115, 120, 209 ... AND gate 116, 123, 211 ... JK flip-flop

Claims (3)

[Claims] 1. A memory access control device for outputting a memory access control signal to a memory to be accessed under the control of a central processing unit, and a monitor means for monitoring the memory access control signal output from the device to the memory. A wait control means for controlling the output of the wait signal to the central processing unit based on the monitor result by the monitor means, and a memory access control device. 2. The wait control means outputs a wait signal to the central processing unit when the timing of change of the memory access control signal monitored by the monitor means is behind a predetermined timing. The memory access control device according to claim 1, wherein the memory access control device is a memory access control device. 3. The monitor means and the weight control means,
The memory access control device according to claim 1, wherein the memory access control device comprises a gate array.