JPH088268B2 - Semiconductor device - Google Patents

Semiconductor device

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Publication number
JPH088268B2
JPH088268B2 JP24249786A JP24249786A JPH088268B2 JP H088268 B2 JPH088268 B2 JP H088268B2 JP 24249786 A JP24249786 A JP 24249786A JP 24249786 A JP24249786 A JP 24249786A JP H088268 B2 JPH088268 B2 JP H088268B2
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JP
Grant status
Grant
Patent type
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP24249786A
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Japanese (ja)
Other versions
JPS6396931A (en )
Inventor
邦昭 内海
Original Assignee
松下電器産業株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1515Shape
    • H01L2924/15153Shape the die mounting substrate comprising a recess for hosting the device
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/15165Monolayer substrate
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3011Impedance

Description

【発明の詳細な説明】 産業上の利用分野 本発明は半導体装置に関し、特に半導体チップを搭載する絶縁性基板における配線及び半田付け用ランドに関する。 FIELD OF THE DETAILED DESCRIPTION OF THE INVENTION Industry The present invention relates to a semiconductor device, a wiring and soldering lands of the insulating substrate in particular mounting a semiconductor chip.

従来の技術 第2図は従来例における外部端子が絶縁性基板の側壁に設けられたLCC(Leadless Chip Carrier)形の半導体装置の断面図であり、1は絶縁性基板、2は絶縁性基板1に搭載された半導体チップ、3は絶縁性基板1のボンディングパッド4と半導体チップ2の電極を結線するボンディングワイヤ、5は外部端子、6はボンディングパッド4と外部端子5を結線する金属配線である。 Prior Art Figure 2 is a cross-sectional view of a LCC (Leadless Chip Carrier) type semiconductor device which external terminals are provided on the side wall of the insulating substrate in a conventional example, 1 denotes an insulating substrate, 2 denotes an insulating substrate 1 semiconductor chip, mounted on 3 bonding wires for connecting the electrodes of the bonding pad 4 and the semiconductor chip 2 of the insulating substrate 1, 5 is an external terminal, 6 is a metal wire for connecting the bonding pad 4 and the external terminal 5 .

高周波信号を扱う電気回路の場合、信号の流れる伝送路の特性インピーダンスと同じ値の抵抗で伝送路の最後が終端されていないと正常な信号の伝送は行われない。 For electrical circuit that handles high-frequency signals, the last of the transmission line with a resistance of the same value as the characteristic impedance of the transmission path of flow of the signal is not terminated transmission of the normal signal is not performed.
そこで半導体装置をプリント基板に搭載して使用する場合、信号が入力する半導体装置の外部端子5近傍で信号伝送路を抵抗で終端することが行われている。 Therefore when used in mounting a semiconductor device on a printed circuit board, it is terminated signal transmission line external terminal 5 near the semiconductor device signal is input by the resistance have been made. しかしながら外部端子5の間隔が0.5mmや0.25mmのように狭くなってくると抵抗の大きさがそれらに比較して大きいため、複数の入力用の外部端子5同士が接近している場合、抵抗の位置を半導体装置からかなり離さないと抵抗を接続できない。 However because the spacing between the external terminal 5 is large compared to those with the magnitude of the resistance becomes narrow as 0.5mm and 0.25 mm, when the external terminal 5 with each other for a plurality of input is approaching, resistance position can not connect the fairly separated without the resistance from the semiconductor device of. したがってこのような場合、抵抗で終端された位置から外部端子5までの配線部分と、半導体装置内部における外部端子5とボンディングパッド4及びその間の金属配線6の部分は特性インピーダンス不整合の状態で信号が伝送することになり正常な伝送は行われなくなる。 Therefore, when such a wiring portion from the terminated position to the external terminal 5 by a resistor, the external terminal 5 and the portion of the bonding pad 4 and between metal wiring 6 in the semiconductor device signal in the form of characteristic impedance mismatch There is not performed in a normal transmission will be transmitted.

また、電源用バイパスコンデンサを接続する場合も上記と同様にコンデンサの位置から半導体装置内部のボンディングパッド4までが長くなり、そのインピーダンスの影響で電源用バイパスコンデンサの電源の安定化の効果が弱くなる。 Further, to the semiconductor device inside the bonding pads 4 from the position of the capacitor in the same manner as described above even if a bypass capacitor for the power supply is increased, the effect of the power supply stabilizing the power supply bypass capacitor is weakened under the influence of the impedance .

発明が解決しようとする問題点 上記のように半導体装置をプリント基板に搭載してプリント基板上において抵抗で信号の終端を行う場合、終端位置から半導体装置内部のボンディングパッドまでの距離が長くなり正常な信号伝送が行われなくなる。 If the invention performs the termination of the signal by the resistance in by mounting a semiconductor device on a printed circuit board on a printed circuit board as problems described above to be solved, the normal becomes the distance from the end position to the semiconductor device inside the bonding pads is long signal transmission is not performed such. また、電源用バイパスコンデンサの場合も同様にその効果が弱くなる。 Similarly, the effect is weakened in the case of power supply bypass capacitor.

本発明は上記欠点に鑑みなされたものであり、ボンディングパッドの近くで終端用抵抗や電源用バイパスコンデンサの接点が可能な半導体装置を提供することを目的とする。 The present invention has been made in view of the above drawbacks, and an object thereof is to provide a semiconductor device capable of contact of the bypass capacitor for the terminating resistor and supply close to the bonding pads.

問題点を解決するための手段 本発明は上記問題点を解決するためになされたものであり、半導体装置裏面で終端用抵抗及び電源用バイパスコンデンサ等を接続するために半田付け用ランドを設け、それらに対応するボンディングパッドにスルーホールを介して結線するものである。 Means the present invention for solving the problems has been made to solve the above problems, provided the soldering lands to connect the terminal resistor and the power supply bypass capacitor, etc. in the semiconductor device backside, the bonding pads corresponding thereto is intended for connecting via the through hole.

作用 ボンディングパッドをスルーホールを介して半導体装置裏面の半田付け用ランドに結線し、半導体装置裏面においてバイアス電源用の半田付け用ランドとの間に終端用抵抗または電源用バイパスコンデンサを接続することにより、上記部品接続位置とボンディングパッドとの距離を短かくすることができる。 And connect to the semiconductor device rear surface of the soldering lands through the through holes the effect bonding pad, by connecting a bypass capacitor for the terminating resistor or power between the soldering lands of the bias power supply in the semiconductor device backside , it can be shorter the distance between the component connecting position and the bonding pad. また抵抗終端の場合、ボンディングパッドまで特性インピーダンスを保つことができる。 In the case of resistive termination, it is possible to keep the characteristic impedance to the bonding pad.

実施例 以下図面を参照して本発明の実施例を説明する。 With reference to the following drawings examples illustrate the practice of the present invention.

第1図は本発明の一実施例におけるLCC形半導体装置の図面であり、同図aは断面図、同bは裏面から見た平面図である。 FIG. 1 is a drawing of LCC type semiconductor device according to an embodiment of the present invention, the Figure a cross-sectional view, and b is a plan view seen from the back. 但しし、実装された部品を含む。 However then, including the implemented parts. 従来例と同一番号のものは同じものを示す。 Those of the conventional example and the same number indicates the same thing.

7,71,72は終端抵抗及びバイパスコンデンサを半田付けするための部品用ランド、8は部品用ランド7,71,72 7, 71, and 72 are parts for land for soldering the terminal resistors and bypass capacitors, 8 parts lands 7, 71, and 72
との間に上記部品を半田付けするための電源用ランド、 Power supply for the land for soldering the components between the,
9はスルーホール、10,11は終端用抵抗、12はバイパスコンデンサである。 9 through hole, 10, 11 terminating resistor, 12 is a bypass capacitor.

本例においては部品用ランド7、及び71は信号入力の端子に対応し、部品用ランド72は電源の端子に対応する。 Parts for land 7, and 71 in this example corresponds to the terminal of the signal input, parts land 72 corresponds to the power supply terminal. その他の出力端子等には必ずしもこれらのスルーホール9や部品用ランド7,71,72を設ける必要はなく、終端を必要とする入力端子及び電源端子にのみ設ければよい。 The other output terminal or the like is not always necessary to provide the through-holes 9 and components for land 7, 71, and 72 may be provided only to the input terminal and a power supply terminal that requires termination. 電源用ランド8には外部から電源を供給する。 Supplying power from the outside to the power supply for the land 8. 本例の場合、同一のランドとなっているが複数の電源を必要とする場合はそれに対応して複数個の電源用ランドを設ければよい。 In this example, if it has the same land that require multiple power may be provided a plurality of power lands correspondingly.

たとえばECLレベルの入力の場合、入力端はバイアス電圧−2V、終端抵抗50Ωが接続されるが、このような場合、電源用ランド8には外部から−2Vを供給し、終端用抵抗10,11を50Ωの抵抗にすればよい。 For example, in the case of ECL level input, input bias voltage -2V, but the terminating resistor 50Ω is connected, in this case, to supply -2V externally to the power supply land 8, the terminal resistor 10, 11 the may be set to 50Ω of resistance.

また、外部端子5、金属配線6、スルーホール9が所望の特性インピーダンスを有するようにしておく、つまり本実施例におけるように終端用抵抗が50Ωであれば、 The external terminal 5, the metal wiring 6, the through hole 9 is kept to have a desired characteristic impedance, that is, if the terminal resistor is 50Ω, as in this embodiment,
当然それに合わせて上記3者の特性インピーダンスを50 Naturally accordingly 50 the characteristic impedance of the three-way
Ωとしておけば、ほぼボンディングパッド4まで正常な信号伝送ができる。 Once you have the Omega, it is normal signal transmission to near the bonding pad 4. 終端抵抗10,11は裏面にあるので、 Since the terminating resistors 10 and 11 on the back side,
半導体装置の外側のプリント基板上で終端する場合よりはるかにボンディングパッド4の近くで終端できることになる。 It would be terminated much near the bonding pads 4 than terminating at the outside of the printed circuit board of the semiconductor device.

終端の場合と同様にバイパスコンデンサ12を接続する場合、できるだけボンディングパッド4に近いほうがよい。 When connecting a bypass capacitor 12 as in the case of termination, it is possible closer to the bonding pad 4. 近ければ近いほど電源の安定化に効果がある。 There is an effect on the stabilization of the closer power. したがってプリント基板上で接続するよりも本例のように半導体装置裏面で接続するほうが効果が大きくなる。 Therefore better to connect the semiconductor device rear surface as in this example than connected by printed circuit board increases the effect.

発明の効果 以上述べてきたように、本発明によれば、ボンディングパッドまで正常な高周波の信号が伝送でき、また電源のバイパスによる安定化の効果を大きくでき、その実用的効果は大なるものがある。 As has been described effect more, according to the present invention, can transmit the normal frequency of the signal to the bonding pad, also possible to increase the effect of stabilization by bypassing the power supply, those its practical effect is made large is there.

【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS

第1図aは本発明の一実施例におけるLCC形半導体装置の断面図、第1図bは同装置を裏面からみた平面図、第2図は従来におけるLCC形半導体装置の断面図である。 Sectional view of the LCC type semiconductor device in an embodiment of Figure 1 a according to the present invention, the first panel b plan view of the same device from the back, FIG. 2 is a sectional view of the LCC type semiconductor device in the prior art. 1……絶縁性基板、2……半導体チップ、3……ボンディングワイヤ、4……ボンディングパッド、5……外部端子、6……金属配線、7……部品用ランド、8……電源用ランド、9……スルーホール、10……終端用抵抗、 1 ...... insulating substrate, 2 ...... semiconductor chip, 3 ...... bonding wires, 4 ...... bonding pads, 5 ...... external terminal, 6 ...... metal wires, 7 ...... part land, 8 ...... power supply land , 9 ...... through-hole, 10 ...... terminating resistor,
12……バイパスコンデンサ。 12 ...... bypass capacitor.

Claims (2)

    【特許請求の範囲】 [The claims]
  1. 【請求項1】絶縁性基板及びこの基板に搭載された半導体チップからなり、それぞれのボンディングパッドと対応する電極とが金属線により結線されており、前記ボンディングパッドは前記絶縁性基板の側面の外部端子へ金属配線で結線され、かつ前記ボンディングパッドの近傍に設けられたスルーホールを介して前記絶縁性基板裏面の半田付け用ランドに結線されており、前記絶縁性基板の裏面には前記半田付け用ランドとの間に終端用抵抗が半田付けでき、また外部からの電源線が接続可能な別の半田付け用ランドが設けられ、前記終端用抵抗に接続されるべき信号伝搬側の前記スルーホール、前記金属配線および前記外部端子が前記終端用抵抗と同一の値の特性インピーダンスを有することを特徴とする半導体装置。 1. A consists semiconductor chip mounted insulating substrate and the substrate, and each of the bonding pads and the corresponding electrodes are connected by metal wires, the bonding pads outside the side surface of the insulating substrate are connected by a metal wire to the terminal, and the are connected to the insulating substrate back surface of the soldering lands through the through hole provided in the vicinity of the bonding pad, wherein the soldering on the back surface of the insulating substrate can soldering termination resistor between the use land and power lines from the outside is different soldering land provided connectable, the through hole of the signal propagation side to be connected to the termination resistor , wherein a said metal wiring and said external terminal has a characteristic impedance of the same value as the resistor for the termination.
  2. 【請求項2】絶縁性基板及びこの基板に搭載された半導体チップからなり、それぞれのボンディングパッドと対応する電極とが金属線により結線されており、前記ボンディングパッドは前記絶縁性基板の側面の外部端子へ金属配線で結線され、かつ前記ボンディングパッドの近傍に設けられたスルーホールを介して前記絶縁性基板裏面の半田付け用ランドに結線されており、前記絶縁性基板の裏面には前記半田付け用ランドとの間にバイパス用コンデンサが半田付けでき、また外部からの電源線が接続可能な別の半田付け用ランドが設けられたことを特徴とする半導体装置。 2. A consists semiconductor chip mounted insulating substrate and the substrate, and each of the bonding pads and the corresponding electrodes are connected by metal wires, the bonding pads outside the side surface of the insulating substrate are connected by a metal wire to the terminal, and the are connected to the insulating substrate back surface of the soldering lands through the through hole provided in the vicinity of the bonding pad, wherein the soldering on the back surface of the insulating substrate the semiconductor device, wherein a bypass capacitor can be soldered, also the power supply line from the outside is different soldering lands connectable provided between the use lands.
JP24249786A 1986-10-13 1986-10-13 Semiconductor device Expired - Lifetime JPH088268B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24249786A JPH088268B2 (en) 1986-10-13 1986-10-13 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24249786A JPH088268B2 (en) 1986-10-13 1986-10-13 Semiconductor device

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JPS6396931A true JPS6396931A (en) 1988-04-27
JPH088268B2 true JPH088268B2 (en) 1996-01-29

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JP24249786A Expired - Lifetime JPH088268B2 (en) 1986-10-13 1986-10-13 Semiconductor device

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2979930B2 (en) * 1993-10-28 1999-11-22 富士電機株式会社 Package of power semiconductor device
US5600175A (en) * 1994-07-27 1997-02-04 Texas Instruments Incorporated Apparatus and method for flat circuit assembly
US5608261A (en) * 1994-12-28 1997-03-04 Intel Corporation High performance and high capacitance package with improved thermal dissipation

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JPS6396931A (en) 1988-04-27 application
JP2094698C (en) grant

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