JPH087471A - Reading circuit - Google Patents

Abstract

PURPOSE:To perform a speedy pull-in operation during the switching of a control system circuit caused by a mode change by controlling an AGC amplifier be employing amplitude errors and error voltages of logic signals. CONSTITUTION:An amplitude detecting circuit 9 is operated and closes a switch A. Then, a first control system circuit is operated, the circuit 9 controls a charge pump 11 in accordance with output error signals and a coarse adjustment of an AGC amplifer 4 is initiated. After a prescribed time, a mode change is conducted, a level detector 8 is operated and a switch B is closed. Then, a second control system circuit is operated and a fine adjustment of the amplifier 4 is started by the operations of the detector 8, an averaging circuit 30 and a VDAC 31. The circuit 8 compares the voltage level of the output logic signals of an ADC 5 with a set value and detects error voltages. The voltages are averaged by the circuit 30, converted into an analog voltage by the VDAC 31, inputted to the amplifier 4 through the switch B as an AGC control voltage for the fine adjustment.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a read circuit (read system circuit) used for reading data from a medium in a magnetic disk device or the like.

[0002]

2. Description of the Related Art FIGS. 8 to 10 are views showing a conventional example. In FIGS. 8 to 10, 3 is a head IC (integrated circuit), 4 is a head IC.
Is an AGC amplifier, 5 is an analog / digital converter (hereinafter referred to as "ADC"), 6 is a data demodulator, 7 is a hard disk controller (hereinafter referred to as "HDC"),
8 is a level detection circuit, 9 is an amplitude detection circuit, 10 is a timer, 11 is a charge pump, 12 is a charge pump (hereinafter referred to as a current output type digital / analog converter "ID
AC "), 14 is an automatic gain control circuit.

§1: Description of read circuit of magnetic disk device--see FIG. 8 FIG. 8 is a block diagram of a read circuit of a conventional example. Less than,
The read circuit of the magnetic disk device will be described with reference to FIG.

As shown in the figure, the read circuit (read system circuit) of the magnetic disk device includes an automatic gain control circuit 14 for performing automatic gain control of a read signal (read signal) output from the head IC 3, and the automatic gain. An ADC 5 for converting the output signal of the control circuit 14 into a digital signal (logic signal), a data demodulator 6 for demodulating read data based on the output signal of the ADC 5, and the like are provided.

The automatic gain control circuit 14 controls the AGC amplifier 4 which outputs a signal in which the gain of the read signal is changed according to the AGC control voltage (VAGC) input to the control terminal, and the AGC amplifier 4. A capacitor C connected to the terminal, and an amplitude detection circuit 9 that detects the amplitude error by comparing the amplitude of the analog signal output from the AGC amplifier 4 with a reference value (threshold value), and outputs the error signal. According to the error signal output from the amplitude detection circuit 9, the voltage level of the charge pump 11 that turns on / off the switch and charges / discharges the capacitor C, and the voltage level of the logic signal output from the ADC 5 are set in advance. And a level detection circuit 8 which detects an error of the voltage by comparing with the reference value (threshold value) and outputs the error signal. ID to charge / discharge Densa C
An AC (charge pump) 12 is provided.

In this way, the automatic gain control circuit 14 has
Based on the error signal output from the level detection circuit 8 and the first control system circuit that controls the AGC control voltage by controlling the charge pump 11 based on the error signal output from the amplitude detection circuit 9. , IDAC12 performs current conversion to control the AGC control voltage (VAGC).
There are two control system circuits including the control system circuit of FIG.

Details of the above-mentioned respective parts are as follows. (1): The AGC amplifier 4 inputs the read signal (read signal) output from the head IC 3, and controls the gain so that the amplitude of the read signal becomes constant according to the AGC control voltage VAGC input to the control terminal. Is to do.

For example, in the AGC amplifier 4, the AGC amplifier
When the control voltage VAGC is high, the gain is reduced, and when the AGC control voltage VAGC is low, the gain is increased to perform automatic gain control.

(2): The ADC 5 converts the read signal (analog signal) passing through the AGC amplifier 4 into a digital signal (logic signal). (3): The data demodulator 6 receives the read signal (logic signal) that has passed through the ADC 5 and demodulates the data.

(4): The level detection circuit 8 uses the read signal (logic signal) passing through the ADC 5 as an input signal Vin, compares the voltage level of this input signal with a preset reference value (threshold value), It detects a voltage error and outputs the error signal.

(5): The amplitude detection circuit 9 is the AGC amplifier 4
The read signal (analog signal) that has passed through is used as an input signal, and the amplitude of the input signal is set to a preset reference value (threshold value).
By comparing with, the amplitude error is detected and the error signal is output.

(6): The timer 10 has a read gate signal (READ GATE) output from the HDC 7 and a clock CLOC.
K (system clock) is input and a mode switching signal (high level H / low level L) is output.

In this case, the timer 10 starts (time measurement starts) when the read gate signal (READ GATE) rises from the low level L to the high level H, and outputs a high level H mode switching signal after a lapse of a certain time. At the same time, when the read gate signal (READ GATE) falls to the low level L again, the mode switching signal is set to the low level L.

The mode switching signal is sent to the amplitude detection circuit 9 and the level detection circuit 8, and at the time when the mode switching signal switches from the low level L to the high level H.
This is a signal for switching the operation mode from the operation by the first control system circuit to the operation by the second control system circuit.

(7): The charge pump 11 switches the internal transistors U and D on the basis of the error signal output from the amplitude detection circuit 9 to charge or discharge the capacitor C and thereby the AGC control voltage. It changes the VAGC.

In this case, when the transistor U is turned on, the capacitor C is charged by the power supply voltage Vcc, and when the transistor D is turned on, the capacitor C is discharged through the transistor D.

(8): The IDAC 12 has a level detection circuit 8
It is a charge pump that converts the error signal output from the device into an analog current to charge or discharge the capacitor C. In this case, for example, the output current of the IDAC 12 is
When the current is in the + direction, the capacitor C is charged, and when the current is in the-direction, the capacitor C is discharged.

§2: Outline of operation of read circuit The operation of the read circuit shown in FIG. 8 is as follows. The read signal (read signal) output from the head IC 3 is input to the AGC amplifier 4, and the AGC amplifier 4 performs gain control to convert the read signal to a constant amplitude signal (analog signal).

The read signal whose amplitude is constant in the AGC amplifier 4 is converted into a digital signal (logic signal) by the ADC 5, demodulated by the data demodulator 6, and then HD.
Sent to C7.

On the other hand, the gain control of the AGC amplifier 4 is as follows. First, the amplitude error of the signal that has passed through the AGC amplifier 4 is detected by the amplitude detection circuit 9, and the charge pump 11 uses the error signal output from the amplitude detection circuit 9 to perform the AG operation.
It is converted into a C voltage and the gain of the AGC amplifier 4 is controlled. This gain control is a rough adjustment of the gain by the first control system circuit, and is performed only for the first fixed period.

When the rough adjustment of the gain is completed, the level detection circuit 8 detects the level of the logic signal passing through the AGC amplifier 4 and the ADC 5, and the gain control of the AGC amplifier 4 is performed via the charge pump of the IDAC 12. . This gain control is a fine adjustment of the gain performed by the second control system circuit.

§3: Operation explanation by time chart
-See Fig. 9 and Fig. 10. Fig. 9 is a time chart 1 of the conventional example (without phase shift), and Fig. 10 is a time chart 2 of the conventional example (with phase shift). The operation of the conventional example will be described below with reference to FIGS. 9 and 10. The signals shown in FIGS. 9 and 10 are as follows.

READ GATE: Read gate signal, + Vth hig
h: + side high level threshold, + Vth low: + side low level threshold, -Vth high: -side high level threshold, -Vth low: -side low level threshold, + Vth: + side level threshold, -Vth:- Side level threshold, VH: error signal, VL: error signal, Vin: input signal (data signal), VAGC: AGC control voltage, CLOCK: clock.

In FIGS. 9 and 10, CLOCK is
(System clock), READ GATE (read gate signal), mode switching signal, AGC circuit output (read signal), transistor U drive signal,
Is a drive signal of the transistor D, and is an output of the IDAC 12.

Among the above signals, the drive signal of the transistor U is a signal which turns on the transistor U at a high level H and turns off the transistor U at a low level L, and the drive signal of the transistor D at a high level H is a transistor. This is a signal in which D is on and the transistor D is off at low level L.

(1): The timer 10 is read at the timing t1 when the read gate (READ GATE) which is a read command of the data output from the HDC 7 rises to the high level H.
Will start (start time measurement).

The read gate signal (READ GATE)
The amplitude detection circuit 9 starts operating at the timing t1 when the signal rises to the high level H, and the coarse adjustment of the gain of the AGC amplifier 4 by the operation of the amplitude detection circuit 9 (coarse adjustment by the first control system circuit) starts.

After that, at a timing t2 when the count value of the timer 10 reaches a fixed time (a fixed time elapses), the mode switching signal output from the timer 10 is at a low level L.
When it rises to a high level H from, the operation of the amplitude detection circuit 9 ends.

(2): On the other hand, at the timing t2 when the mode switching signal rises to the high level H, the level detection circuit 8 starts its operation, and the operation of the level detection circuit 8 causes A
Fine adjustment of the gain of the GC amplifier 4 (fine adjustment by the second control system circuit) is started. This fine adjustment operation ends at the timing t3 when the read gate signal (READ GATE) falls to the low level L and the mode switching signal falls to the low level L.

(3): The timer 10 starts (time measurement starts) when the read gate signal (READ GATE) rises from low level L to high level H, and when the timer measured value by the timer 10 reaches a certain time. , High level H
The mode switching signal of is output.

After that, when the read gate signal (READ GATE) falls from the high level H to the low level L, the timer 10 is reset and the mode switching signal also returns to the low level L.

(4): In the amplitude detection circuit 9, when the amplitude of the read signal passed through the AGC amplifier 4 is larger than + Vth high or smaller than -Vth high, the transistor U of the charge pump 11 is It outputs a high level H signal.

This high level H signal turns on the transistor U of the charge pump 11 to charge the capacitor C and raise the AGC control voltage (VAGC).
As a result, the gain of the AGC circuit is reduced.

Further, in the amplitude detection circuit 9, when the amplitude of the read signal is larger than + Vth low, or -Vth low.
When smaller, the transistor D of the charge pump 11
In response, a high level H signal is output.

This high level H signal turns on the transistor D of the charge pump 11, discharges the capacitor C and lowers VAGC, thereby increasing the gain of the AGC amplifier 4.

In the amplitude detecting circuit 9, when the amplitude of the read signal is smaller than + Vth low or -Vth low.
When it is larger, a low level L signal is output to the transistors U and D of the charge pump 11. This turns off the transistors U and D. This is done in order to prevent the gain from rising by discharging the capacitor C when the erased data comes (when there is no signal only due to noise).

(5): The level detection circuit 8 has a value obtained by sampling data at the timing of the clock CLOCK through the ADC 5, a preset level threshold value + Vth, and
-Detects the voltage (error voltage) that is the difference from -Vth. Then, the detected error voltages VH and VL are output to the IDAC 12. I
The DAC 12 outputs an analog current proportional to the error voltage.

In this case, the error voltages VH and VL are as follows. Note that Vin is an input signal (voltage) of the level detection circuit 8. When Vin> + Vth, VH = {Vin − (+ Vth)}, Vin <−V
If th, VH =-{Vin-(-Vth)}, if Vin <+ Vth, VL = {Vin-(+ Vth)}, if Vin> -Vth, VL =
-{Vin-(-Vth)}.

(6) Therefore, if the initial phase of the read signal does not deviate from the clock as shown in FIG. 9, normal operation is possible even when mode switching is performed at timing t2 by the mode switching signal. Is.

However, as shown in FIG. 10, when the initial phase (the phase of the clock and the read signal) is shifted, when the mode is switched at the timing t2,
Due to the current converted by the IDAC 12, the capacitor C is only discharged and the pull-in operation of the AGC amplifier 4 becomes discontinuous.

[0041]

SUMMARY OF THE INVENTION The above-mentioned conventional device has the following problems. (1): The first control system circuit is a control system using an analog signal, and the second control system circuit is a control system using a logic signal (digital signal). Then, switching between the two control system circuits by mode switching is performed by a logic signal.

Therefore, when the mode is switched, the amplitude detecting circuit and the level detecting circuit are switched in a random relationship. Therefore, if the phase at the moment of switching is opposite, the control direction is opposite. Become. As a result, the operation of the AGC amplifier becomes uncertain at the moment of switching,
The control voltage is disturbed and the output signal becomes unstable.

(2): For example, when the initial phase is shifted as in the conventional example, when the mode is switched, the capacitor C is only discharged by the current converted by the IDAC (charge pump). Therefore, the pull-in operation of the AGC amplifier becomes discontinuous.

The present invention solves the above-mentioned conventional problems, and prevents the circuit operation from becoming unstable at the time of switching between the first control system circuit and the second control system circuit by the mode switching, so that quick operation is possible. The purpose is to be able to perform a simple pull-in operation.

[0045]

FIG. 1 is a diagram for explaining the principle of the present invention. In FIG. 1, the same parts as those in FIGS. 8 to 10 are designated by the same reference numerals. 31 is a voltage output type digital /
Analog converter (hereinafter referred to as "VDAC"), 3
0 indicates an averaging circuit. The present invention is configured as follows to achieve the above object.

That is, the automatic gain control circuit 1 for controlling the gain of the read signal from the head 18 to the read circuit.
4 and an ADC 5 for converting an analog signal output from the automatic gain control circuit into a digital logic signal. The automatic gain control circuit 14 has a control terminal CT and an AGC control voltage input to the control terminal. Depending on (VAGC), output the signal with the gain of read signal changed
The amplitude error is detected by comparing the amplitude of the GC amplifier 4, the capacitor C connected to the control terminal of the AGC amplifier, and the amplitude of the analog signal output from the AGC amplifier 4 with a preset reference value, and the error signal is detected. Output amplitude detection circuit 9
And according to the error signal output from the amplitude detection circuit 9,
The voltage level of the logic signal output from the ADC 5 and the charge pump 11 that turns on / off the switch and charges / discharges the capacitor C is compared with a preset reference value to detect an error voltage, A level detection circuit 8 that outputs an error signal, an averaging circuit 30 that creates an average value of the error signal output from the level detection circuit 8, and an analog that is proportional to the average value of the error signal output from the averaging circuit 30. VDA that generates a voltage (an analog voltage proportional to the amplitude error) and outputs it to the control terminal CT of the AGC amplifier
C31 is provided.

The automatic gain control circuit 14 includes:
Based on the error signal output from the level detection circuit 8 and the first control system circuit that controls the AGC control voltage by controlling the charge pump 11 based on the error signal output from the amplitude detection circuit 9. Then, by generating an analog voltage from the VDAC 31, two control system circuits including a second control system circuit for controlling the AGC control voltage are configured.

[0048]

The operation of the present invention based on the above construction will be described with reference to FIG. At the time of reading data, first, the amplitude detection circuit 9 starts its operation and the switch A is closed. As a result, the first control system circuit operates, the charge pump 11 is controlled according to the error signal output from the amplitude detection circuit 9, and the capacitor C is charged / discharged, whereby the gain of the AGC amplifier 4 is increased. Start coarse adjustment of.

After that, when a certain period of time has passed, the mode is switched, the level detection circuit 8 starts operating, and the switch B is closed. As a result, the second control system circuit starts to operate, and the level detection circuit 8 and the averaging circuit 3
0, fine adjustment of the gain of the AGC amplifier 4 by the operation of the VDAC 31 is started.

In the fine adjustment of the gain, the level detection circuit 8
Thus, the error voltage is detected by comparing the voltage level of the logic signal output from the ADC 5 with a preset reference value.

The error voltage is averaged by the averaging circuit 30 and then output to the VDAC 31. In VDAC31,
The averaged error voltage is converted into an analog voltage and output. The voltage output from the VDAC 31 is output as the AGC control voltage VAGC to the control terminal of the AGC amplifier 4 via the switch B.

The analog voltage output from the VDAC 31 as described above is a voltage proportional to the amplitude error of the read signal, and this voltage is output to the control terminal of the AGC amplifier 4 and used for gain control in the AGC amplifier 4. used.

In this case, the AGC control voltage (charge pump output) before mode switching and A after mode switching are set.
The GC control voltage (VDAC output) should be substantially the same analog voltage (voltage proportional to the amplitude error).

Therefore, the gain control of the AGC amplifier 4 can be performed without being influenced by the switching timing of the switch A and the switch B. Therefore, when switching between the first control system circuit and the second control system circuit by mode switching, the circuit operation does not become unstable, and a quick pull-in operation can be performed.

[0055]

Embodiments of the present invention will be described below with reference to the drawings. 2 to 7 are views showing an embodiment of the present invention. In FIGS. 2 to 7, the same parts as those in FIGS. 1 and 8 to 10 are
It is indicated by the same reference numeral.

Further, 16 is a magnetic disk (medium), 17
Is a spindle motor, 18 is a head, 19 is a filter,
20 is a crystal oscillator, 21 is a frequency comparison circuit, 22 is a voltage controlled oscillator (hereinafter referred to as “VCO”), 23 is a charge pump, 24 is a data modulator, 25 is a microprocessor (hereinafter referred to as “MPU”), 26 Is the servo control circuit,
27 is a phase detection circuit, 30 is an averaging circuit, 31 and 40 are voltage output type digital / analog converters (hereinafter referred to as “V
"DAC"), 33, 34, 37, 38 are analog switches (FETs), 39 is an averaging circuit, and 42 is a PLL.
1 shows a circuit (PLL: phase locked loop).

§1: Explanation of configuration of magnetic disk device ...
See FIG. 2. FIG. 2 is a device block diagram of the first embodiment. The configuration of the magnetic disk device will be described below with reference to FIG.

The magnetic disk 16 is a medium for recording data and is rotationally driven by the spindle motor 17. The head 18 is mounted on the head arm and reads / writes (reads / writes) data from / to the magnetic disk 16. The head IC 3 drives the head 18 when reading / writing data.

The filter 19 filters the read signal that has passed through the AGC amplifier 4 (noise removal, waveform shaping, etc.). The ADC 5 converts the read signal that has passed through the filter 19 into a digital signal (logic signal).

The data demodulator 6 receives the read signal (logic signal) that has passed through the ADC 5 and demodulates the data. The MPU 25 is a processor that performs various controls of the magnetic disk device, and the HDC 7 is a higher-level controller. The servo control circuit 26 uses the head 18
Position control, rotation control of the spindle motor 17, and the like.

The automatic gain control circuit 14 is composed of an AGC amplifier 4, an amplitude detection circuit 9, a level detection circuit 8, a charge pump 11, etc., and controls the gain of the read signal output from the head IC 3. (Detailed configuration will be described later).

The PLL circuit 42 is composed of a VCO 22, a frequency comparison circuit 21, a phase detection circuit 27, a crystal oscillator 20, a charge pump 23, etc., creates a system clock, and supplies the clock to the ADC 5 etc. Yes (detailed configuration will be described later).

§2: Outline of operation of magnetic disk device
.. Refer to FIG. 2. The operation outline of the magnetic disk device shown in FIG. (1): When writing data to the magnetic disk 16 (data write), the write signal from the HDC 7 is modulated by the data modulator 24 and sent to the head IC 3. Head IC3
Then, based on the write signal (modulated write data), the head 18 is driven to write data to the magnetic disk 16.

(2): When data is read from the magnetic disk 16 (data read), it is as follows. First, a read signal (read signal) read from the magnetic disk 16 by the head 18 is sent to the AGC via the head IC 3.
Input to the amplifier 4.

In the AGC amplifier 4, the charge pump 11
The gain control is performed based on the AGC control voltage controlled by, for example, and a read signal having a constant amplitude is output. That is, since the read signal output from the head IC 3 has a large variation in amplitude, the AGC amplifier 4 keeps the read signal amplitude constant.

After that, the read signal that has passed through the AGC amplifier 4 passes through the filter 19 and the ADC 5 and is sent to the data demodulator 6 where it is demodulated. (3): The outline of the operation of the AGC amplifier 4 is as follows. First, the amplitude detection circuit 9 detects the amplitude of the read signal that has passed through the filter 19, and the charge pump 11 is controlled based on the output signal of the amplitude detection circuit 9 so that A
The gain control of the AGC amplifier 4 is performed by changing the GC control voltage. By this control, the gain is roughly adjusted for the first fixed time.

When the rough adjustment is completed, the filter 19,
And read signal (logic signal) that passed ADC5
Is detected by the level detection circuit 8, and an AGC control voltage is generated based on the output signal of the level detection circuit 8.
The gain of the AGC amplifier 4 is controlled. With this control, the gain is finely adjusted.

The reason for finely adjusting the gain in the AGC amplifier 4 is that the read signal (read data) is used because the data demodulator 6 demodulates data at a fixed slice level.
This is because it is necessary to accurately adjust the amplitude of the to the fixed slice level.

(4): The outline of the operation of the PLL circuit 42 is as follows. The PLL circuit 42 creates a system clock as follows. First, when reading data from the medium, the output of the VCO 22 is read via the phase detection circuit 27 in order to match the phase of the signal output from the VCO 22 with the phase of the read signal (data signal). The phase error from the signal is input to the charge pump 23.

Then, the charge pump 23
The VCO 22 generates a clock that matches the phase of the input signal by controlling the VCO 22. At this time, the frequency comparison circuit 2
1 is separated from the charge pump 23.

Next, since the read signal does not come in except when the data is read, instead, the system clock is created based on the signal from the crystal oscillator 20. For this reason,
The frequency of the VCO 22 is compared with the frequency of the crystal oscillator 20 by the frequency comparison circuit 21, and the oscillation frequency of the VCO 22 is controlled via the charge pump 23. At this time, the phase detection circuit 27 is separated from the charge pump 23.

§3: Detailed description of automatic gain control circuit
-Refer to FIG. 3 FIG. 3 is a detailed block diagram of the automatic gain control circuit. Hereinafter, the automatic gain control circuit will be described in detail with reference to FIG.

The automatic gain control circuit 14 shown in FIG.
AGC amplifier 4, level detection circuit 8, amplitude detection circuit 9,
Charge pump 11, timer 10, averaging circuit 30, V
A DAC 31 and analog switches 33 and 34 are provided.

Of these circuits, the amplitude detection circuit 9, the charge pump 11, and the analog switch 33 are the first control system circuit, and the level detection circuit 8, the averaging circuit 30, and the VD
The AC 31 and the analog switch 34 are a second control system circuit.

The averaging circuit 30 includes a level detecting circuit 8
It is a circuit that creates and outputs the average value of the error signal output from. The VDAC 31 converts the average value of the error signal output from the averaging circuit 30 into an analog voltage and outputs a control voltage (AGC control voltage) (voltage output type D
AC).

The timer 10 has a read gate signal (READGATE) output from the HDC 7 shown in FIG.
Input the clock CLOCK (system clock) output from 22 to input the mode switching signal (high level H /
It outputs a low level L).

In this case, the timer 10 starts (time measurement starts) when the read gate signal (READ GATE) rises from the low level L to the high level H, and outputs the mode switching signal of the high level H after a lapse of a fixed time. At the same time, when the read gate signal (READ GATE) falls to the low level L again, the mode switching signal is set to the low level L.

The mode switching signal is sent to the amplitude detecting circuit 9 and the level detecting circuit 8, and at the time when the mode switching signal switches from the low level L to the high level H.
This is a signal for switching the operation mode from the operation by the first control system circuit to the operation by the second control system circuit.

Also, from the timer 10 to the analog switch 3
The timer output A and the timer output B are output to the modes 3 and 34 in order to perform the mode switching. The analog switch 33 is an analog switch (for example, FET) that is on / off controlled by the timer output A output from the timer 10. This analog switch 33
Is turned on, the charge pump 11 is connected to the capacitor C, and when the analog switch 33 is turned off, the charge pump 11 and the capacitor C are disconnected.

The analog switch 34 is the timer 10
Is an analog switch (for example, FET) which is on / off controlled by a timer output B output from the VDAC 31 when the analog switch 34 is turned on.
Connect to the GC amplifier 4.

When the analog switch 34 is off, the VDAC 31 and the AGC amplifier 4 are disconnected. Since the other configurations are the same as those of the conventional example, description thereof will be omitted. §4: Description of gain control of AGC amplifier--see FIG. 4 FIG. 4 is an explanatory diagram of gain control. The gain control in the AGC amplifier 4 will be described below with reference to FIG.

In FIG. 4, the horizontal axis represents the AGC control voltage VAGC input to the control terminal of the AGC amplifier 4, and the vertical axis represents the AGC.
Indicates the gain. As shown, the AGC amplifier 4
Then, when the AGC control voltage VAGC input to the control terminal is small, the gain is increased, and the gain is decreased as the AGC control voltage VAGC increases.

For example, the capacitor C is charged more,
When the voltage rises, the AGC control voltage VAGC increases, so the gain in the AGC amplifier 4 decreases, and conversely,
When the discharge of the capacitor C increases and the voltage thereof decreases, the AGC control voltage VAGC decreases, so that the gain of the AGC amplifier 4 increases.

In this way, the amplitude of the read signal passing through the AGC amplifier 4 is made constant by performing the negative feedback (negative feedback) on the AGC amplifier 4 to control the gain.

§5: Explanation of operation of read circuit based on time chart ... See FIGS. 5 and 6. FIG. 5 is a time chart 1 of the embodiment (without phase shift), and FIG. 6 is a time chart 2 of the embodiment ( (There is a phase shift). The operation of the read circuit will be described below with reference to FIGS.

The signals shown in FIGS. 5 and 6 are as follows. CLOCK: Clock (clock signal), READ GATE: Read gate signal, + Vth high: + side high level threshold, + Vth
low: + side low level threshold, -Vth high: -side high level threshold, -Vth low: -side low level threshold, + Vth: + side level threshold, -Vth:-side level threshold, Vin: Input signal (data Signal), VH: error voltage, VL: error voltage, VAGC: AG
The C control voltage, t1 to t3, shows each timing.

In the figure, CLOCK (system clock), READ GATE (read gate signal), timer output A (switch signal of analog switch 33),
Is a timer output B (switching signal of the analog switch 34), is an output of the AGC circuit (reading signal), is a drive signal of the transistor U, is a drive signal of the transistor D, and is an output of the VDAC 31 (analog voltage).

Of the above signals, the timer output A is a switching signal of the analog switch 33, and is a signal which is turned on at a high level H and turned off at a low level L. The timer output B is a switching signal of the analog switch 34 and is a signal which is turned on at a high level H and turned off at a low level L.

The drive signal of the transistor U is
This signal is turned on at a high level H and turned off at a low level L. The drive signal of the transistor D of is high level H
The signal is turned on at, and turned off at low level L.

The mode switching signal is output from the timer 10 to the amplitude detecting circuit 9 and the level detecting circuit 8 as in the conventional example (the mode switching signal is not shown in FIGS. 5 and 6). Have been done).

(1): The read gate signal (READ GATE) which is a data read command output from the HDC 7 is
When rising to the high level H at the timing t1, the timer 10 is started (time measurement is started).

Further, the read gate signal (READ GATE)
Rises to a high level H, the amplitude detection circuit 9 starts operating, and the AGC amplifier 4 according to the operation of the amplitude detection circuit 9 operates.
The coarse adjustment of the gain starts.

After that, at the timing t2 when the count value of the timer 10 reaches a certain time (when a certain time has passed), the mode switching signal output from the timer 10 is at the low level L.
Rises to a high level H, and the operation of the amplitude detection circuit 9 ends.

(2): Further, at the timing t1, when the read gate signal (READ GATE) rises to the high level H, the timer output A output from the timer 10 becomes the high level H and the timer output B becomes the low level. It is L. Therefore, the analog switch 33 is turned on, and the output of the charge pump 11 is connected to the capacitor C.

In this state, coarse adjustment of the gain of the AGC amplifier 4 by the operation of the amplitude detection circuit 9 starts. And
At timing t2, the timer output A output from the timer 10 becomes low level L, the analog switch 33 is turned off, and the charge pump 11 and the capacitor C are separated. Therefore, the rough adjustment by the operation of the amplitude detection circuit 9 ends.

(3): Further, when the mode switching signal rises to the high level H at the timing t2, the level detection circuit 8 starts its operation. At this time, the timer output A becomes low level L and the timer output B becomes high level H.

Therefore, the analog switch 33 is turned off and the analog switch 34 is turned on, and the fine adjustment of the gain by the operation of the level detection circuit 8 is started. After that, at timing t3, when the read gate signal (READ GATE) falls to the low level L, the operation of the level detection circuit 8 ends. At this time, the timer output B becomes low level L and the analog switch 34 is turned off.

As described above, the timings t1 to t2
During the period, the gain is roughly adjusted by the operation of the amplitude detection circuit 9, and during the timings t2 to t3, the gain is finely adjusted by the operation of the level detection circuit 8.

(4): As described above, the timings t1 to t
Between the two, the analog switch 33 is turned on, and the gain of the AGC amplifier 4 is roughly adjusted by the operation of the amplitude detection circuit 9, but this processing is the same as the conventional example.

After that, at the timing t2, the analog switch 33 is turned off, the analog switch 34 is turned on, and the AGC amplifier 4 by the operation of the level detection circuit 8 is turned on.
Perform a coarse adjustment of the gain of.

At this time, in the level detection circuit 8, the input signal
Vin (logic signal that has passed through ADC5), preset + side level threshold + Vth, and-side level threshold -V
The error voltage (VH or VL) is detected by comparing with th.

The error voltage is averaged by the averaging circuit 30 and then output to the VDAC 31. In VDAC31,
The averaged error voltage is converted into an analog voltage and output. The voltage output from the VDAC 31 is output as the AGC control voltage VAGC to the control terminal of the AGC amplifier 4 via the analog switch 34.

The analog voltage output from the VDAC 31 as described above is a voltage proportional to the amplitude error of the read signal, and this voltage is output to the control terminal of the AGC amplifier 4 and used for gain control in the AGC amplifier 4. used.

Therefore, A is not affected by the switching timing of the analog switch 33 and the analog switch 34.
The gain control of the GC amplifier 4 can be performed. (5): In the amplitude detection circuit 9, the amplitude of the input signal is + Vth h
When it is larger than igh or smaller than -Vth high,
It outputs a high level H signal to the transistor U. This turns on the transistor U, charges the capacitor C, and raises the AGC control voltage VAGC.
As a result, the gain of the AGC circuit is reduced.

When the amplitude of the input signal is larger than + Vth low or smaller than -Vth low, a high level H signal is output to the transistor D. This turns on the transistor D, discharges the capacitor C, and lowers VAGC, thereby increasing the gain of the AGC amplifier 4.

When the amplitude of the input signal is smaller than + Vth low or larger than -Vth low, the amplitude detection circuit 9 outputs a low level L signal to the transistors U and D, and the transistor U, Turn off D. This is done in order to prevent the gain from rising by discharging the capacitor C when the erased data comes (when there is no signal only due to noise).

(6): The level detection circuit 8 detects the voltage difference between the value (the voltage level of the logic signal) at which the data is sampled at the clock timing through the ADC 5 and the preset level thresholds + Vth and -Vth. Is detected as an error voltage and the error signal is output.

In this case, the error signals VH and VL are as follows. When Vin> + Vth, VH = {Vin − (+ Vth)}, Vin <−V
If th, VH =-{Vin-(-Vth)}, if Vin <+ Vth, VL = {Vin-(+ Vth)}, if Vin> -Vth, VL =
-{Vin-(-Vth)}.

§6: Description of PLL Circuit--See FIG. 7 FIG. 7 is a detailed block diagram of the PLL circuit. Below, FIG.
The PLL circuit shown in will be described in detail.

As shown in the figure, the read circuit is provided with an automatic gain control circuit 14 for controlling the gain of a read signal output from the head IC 3, an ADC 5, and a data demodulator 6. Further, the read circuit includes the PLL circuit 42.
Is provided and supplies a clock to the ADC 5 and the like.

The PLL circuit 42 has a control terminal VT, and outputs a signal (clock) whose oscillation frequency is changed according to a control voltage input to the control terminal VT.
O22 and a capacitor C2 connected to the control terminal VT of the VCO 22 and applying a control voltage to the control terminal, and VC
The frequency of the signal (clock) output from O22 is compared with the frequency of the reference signal to detect a frequency error, and a frequency comparison circuit 21 that outputs the error signal and an error signal output from the frequency comparison circuit 21 are used. Accordingly, the switch is turned on / off to charge / discharge the capacitor C2, the phase of the logic signal output from the ADC 5, and the output signal (clock) of the VCO 22.
A phase detection circuit 27 that detects the phase error by comparing the phases of the two and outputs the error signal; and an averaging circuit 39 that creates an average value of the error signal output from the phase detection circuit 27.
The VDAC 40 that generates an analog voltage proportional to the average value of the error signal output from the averaging circuit 39 and outputs it to the control terminal of the VCO 22, and the analog switches 37, 3
8 and so on.

As described above, in the PLL circuit 42, the first control system circuit for controlling the control voltage of the VCO 22 by controlling the charge pump 23 based on the error signal output from the frequency comparison circuit 21. And the VCO2 based on the error signal output from the phase detection circuit 27.
And a second control system circuit for controlling the second control voltage.

Then, the frequency of the clock output from the VCO 22 is controlled by switching between the two control system circuits at the time of reading data and at other times.

In the above mode switching, the analog switch 38 is turned on at the rising of the read gate signal, and at other times, the analog switch 37 is turned on to turn on the first control system circuit and the second control system circuit. Switch.

The PLL circuit 42 controls the frequency of the clock as follows. At the time of reading data from the medium, mode switching is performed to switch to the second control system circuit, the phase detection circuit 27 is operated, the analog switch 38 is turned on, and the analog switch 37 is turned on.
Turn off.

Then, the averaging circuit 39 creates an average value of the error signal output from the phase detection circuit 27, and V
The DAC 40 generates an analog voltage proportional to the average value, and the VCO 22 is supplied via the analog switch 38.
The analog voltage is output to the control terminal VT of.

In this way, control is performed to match the phase of the signal output from the VCO 22 with the phase of the read signal (data signal), and the VCO 22 generates a clock that matches the phase of the input signal.

Next, since the read signal does not come in except when the data is read, the mode is switched and the first control system circuit is operated. During the operation of the first control system circuit, the system clock is created based on the signal from the crystal oscillator 20. At this time, the frequency comparison circuit 21 operates,
Analog switch 37 is on and analog switch 38
Turns off.

Therefore, the frequency of the VCO 22 is compared with the frequency of the crystal oscillator 20 by the frequency comparison circuit 21, and the oscillation frequency of the VCO 22 is controlled via the charge pump 23.

(Other Embodiments) The embodiments have been described above, but the present invention can also be implemented as follows. (1): The analog switch of the above embodiment is not limited to the FET (field effect transistor), but may be replaced with another similar switch element (for example, a bipolar transistor).

(2): Not limited to the magnetic disk device, other similar devices (eg, magnetic tape device, optical disk device)
Also, it is possible to carry out similarly. (3): In the above embodiment, it is possible to preset the AGC control voltage from VDAC by overlapping the mode switching timings.

In this case, for example, in FIG. 3, when the mode is switched, the analog switch 34 is turned on and the charge pump 11 is connected to the capacitor C, the analog switch 34 is turned on, and the VDAC 31 is turned on.
The analog voltage is output (overlap state), and then the analog switch 33 is turned off while the analog switch 34 is kept on.

This control can be carried out by changing the timer output from the timer 10. If you do this,
In the automatic gain control, the pull-in time at the time of mode switching can be further shortened.

[0124]

As described above, the present invention has the following effects. (1): As described in the above embodiment, the analog voltage output from the VDAC is a voltage proportional to the amplitude error of the read signal, and this analog voltage is output to the control terminal of the AGC amplifier during mode switching. , Used for gain control in AGC amplifier.

Therefore, the gain control of the AGC amplifier can be performed without being affected by the switch switching timing at the time of mode switching. Therefore, when switching between the first control system circuit and the second control system circuit by mode switching, the circuit operation does not become unstable, and a quick pull-in operation can be performed.

(2): As described above, the circuit operation does not become unstable at the time of mode switching, and a quick pull-in operation can be performed. Therefore, it is possible to detect data immediately after mode switching, and wait time at the time of switching. Disappears.

Conventionally, the data for the waiting time at the time of switching could not be read, but according to the present invention, the waste of the storage capacity for the waiting time at the time of switching can be eliminated. Therefore, the reliability of the magnetic disk device or the like can be improved.

(3): Even in the PLL circuit, the analog voltage output from the VDAC is a voltage proportional to the phase error, and this analog voltage is V when the mode is switched.
It is output to the control terminal of the CO and used for frequency control of the clock in the VCO.

Therefore, the VCO frequency control can be performed without being affected by the switch switching timing at the time of mode switching. Therefore, when switching between the first control system circuit and the second control system circuit by mode switching, the circuit operation does not become unstable, and a quick frequency pull-in operation can be performed.

(4): By overlapping the mode switching timing and presetting the AGC control voltage from VDAC, the AGC pull-in time at the time of mode switching can be further shortened.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a device block diagram of the first embodiment.

FIG. 3 is a detailed block diagram of an automatic gain control circuit in the example.

FIG. 4 is an explanatory diagram of gain control in the embodiment.

FIG. 5 is a time chart 1 (no phase shift) of the embodiment.

FIG. 6 is a time chart 2 (with a phase shift) of the embodiment.

FIG. 7 is a detailed block diagram of a PLL circuit according to a second embodiment.

FIG. 8 is a block diagram of a conventional read circuit.

FIG. 9 is a time chart 1 (no phase shift) of a conventional example.

FIG. 10 is a time chart 2 of the conventional example (with phase shift).
Is.

[Explanation of symbols]

4 AGC amplifier 5 analog / digital converter (ADC) 8 level detection circuit 9 amplitude detection circuit 11 charge pump 18 head 30 averaging circuit 31 voltage output type digital / analog converter (V
DAC) AGC automatic gain control circuit C capacitor CT control terminal VAGC AGC control voltage

Claims (4)

[Claims] 1. An automatic gain control circuit for controlling a gain of the read signal is provided on a transmission path of a read signal from a head, and the automatic gain control circuit has a control terminal and inputs to the control terminal. An AGC amplifier that outputs a signal in which the gain of the read signal is changed according to an AGC control voltage; a capacitor that is connected to a control terminal of the AGC amplifier and applies an AGC control voltage to the control terminal; The amplitude of the analog signal output from the comparator is compared with a preset reference value to detect an error in the amplitude, and an amplitude detection circuit that outputs the error signal and an error signal output from the amplitude detection circuit , A charge pump that turns on / off the switch to charge / discharge the capacitor, and a logic output from the analog / digital converter. A level detection circuit that detects a voltage level error by comparing the voltage level of the signal with a preset reference value and outputs the error signal, and creates an average value of the error signals output from the level detection circuit And an amplitude output circuit for generating an analog voltage proportional to the average value of the error signal output from the averaging circuit and outputting the analog voltage to the control terminal of the AGC amplifier. Based on the error signal output from
A first control system circuit that controls the AGC control voltage by controlling the charge pump, and a second control system circuit that controls the AGC control voltage based on an error signal output from the level detection circuit. And a control circuit including two control system circuits and switching between these two control system circuits to perform automatic gain control by rough adjustment and fine adjustment. 2. The read circuit according to claim 1, wherein the voltage output circuit is a voltage output type digital / analog converter. 3. A transmission line for a read signal from the head is provided with an automatic gain control circuit for controlling the gain of the read signal and a PLL circuit for generating a clock, and the PLL circuit has a control terminal, A voltage-controlled oscillator that outputs a signal (clock) whose oscillation frequency is changed according to a control voltage input to the control terminal; and a control terminal that is connected to the control terminal of the voltage-controlled oscillator and applies the control voltage to the control terminal. A frequency comparator circuit for detecting a frequency error by comparing a frequency of a signal (clock) output from the voltage controlled oscillator with a capacitor and a frequency of a reference signal, and a frequency comparator circuit for outputting the error signal; Depending on the output error signal,
Switch on / off to charge / charge the capacitor
A phase error is detected by comparing the phase of the logic signal output from the charge pump that discharges with the analog / digital converter with the phase of the output signal (clock) of the voltage controlled oscillator, and the error signal is output. A phase detection circuit, an averaging circuit that creates an average value of the error signal output from the phase detection circuit, and generate an analog voltage proportional to the average value of the error signal output from the averaging circuit, A voltage output type circuit that outputs to a control terminal of the voltage controlled oscillator, and controls the charge pump based on an error signal output from the frequency comparison circuit to control a control voltage of the voltage controlled oscillator. Based on the first control system circuit and the error signal output from the phase detection circuit,
A second control system circuit for controlling the control voltage of the voltage controlled oscillator is provided, and the frequency of the clock is controlled by switching between these two control system circuits. 4. The read circuit according to claim 3, wherein the voltage output circuit is a voltage output type digital / analog converter.