JPH0864755A - Semiconductor device - Google Patents

Abstract

PURPOSE: To prevent the adverse effect caused by the surge voltage generated by the wiring inductance in a semiconductor device, and to obtain a semiconductor device with which the dielectric breakdown and the like of a semiconductor element can be prevented. CONSTITUTION: An insulating plate 2, having the first, the second and the third metal plates, is fixed on the fourth metal plate 1. A diode 7 and an IGBT 6 are antiparallel-connected and fixed to the first metal plate 3, and the emitter electrode 18 on the IGBT 6 is connected to the second metal plate 5 by a conducting wire 14. The anode electrode 19 on the diode 7 is connected to the second metal plate 5 by a conducting wire 15. A collector main terminal 8 and a collector auxiliary terminal 12 are connected and fixed to the first metal plate 3 in such a manner that they are rising from the metal plate, and an emitter main terminal 9, an emitter control terminal 10 and an emitter auxiliary terminal 13 are connected and fixed to the second metal plate 5 in such a manner that they are rising from the metal plate vertically. Besides, the gate electrode 17 on the IGBT 6 is connected to the third, metal plate 4 by a conductive wire 16, and a gate control terminal 11 is connected and fixed to the fourth metal plate 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having an auxiliary terminal for protecting a semiconductor element incorporated in the semiconductor device.

[0002]

2. Description of the Related Art Inverter devices, uninterruptible power supply devices, resonance type power supply devices and the like are often semiconductor devices having a semiconductor element such as a power MOSFET and an insulating gate type bipolar transistor (IGBT). in use. And
Higher efficiency has been promoted, and the switching characteristics of built-in semiconductor elements have been increasing year by year. Therefore, it is important to optimize the internal wiring layout and the input / output terminal structure of the semiconductor device.

As a conventional technique of such a semiconductor device,
For example, there is one disclosed in Japanese Patent Laid-Open No. 3-263363.

According to this, an auxiliary electrode connected to the first auxiliary terminal and one main electrode connected to the main terminal and the second auxiliary terminal are provided on one surface of the semiconductor piece fixed on the support plate. And each terminal is raised perpendicular to the support plate surface,
In the case where the main current is controlled by a voltage applied between the first and second auxiliary terminals and connected to each electrode, the connection wiring with the second auxiliary terminal is the main connection wiring with the main terminal. An example of a semiconductor device connected at a position close to the terminal rising portion is shown.

[0005]

In recent years, as the switching characteristics of semiconductor elements built into semiconductor devices have become faster, the current change rate di / dt of the main current has increased.
The increase in / dt is due to the wiring inductance L in the semiconductor device.
The interaction with and causes an increase in the surge voltage corresponding to (L × di / dt). And by this phenomenon,
When the semiconductor device is turned off during switching and when the diode is reversely recovered, the surge voltage becomes an overvoltage, causing dielectric breakdown of the semiconductor device.

However, in the above conventional semiconductor device,
A protection circuit for suppressing the surge voltage is installed between the main terminals, but a protection circuit for suppressing the surge voltage generated by the wiring inductance in the semiconductor device is not installed, and the surge voltage is not absorbed and the dielectric breakdown occurs. Was not resolved. Moreover, the current imbalance, which was a problem when the semiconductor devices were connected in parallel, could not be eliminated.

Therefore, an object of the present invention is to provide a semiconductor device capable of preventing dielectric breakdown of a semiconductor element due to a surge voltage generated by wiring inductance in the semiconductor device.

[0008]

A semiconductor device which achieves the above object comprises a first metal plate, a second metal plate and a third metal plate made of an electric conductor, and the first, second and third metal plates. A semiconductor element having an emitter electrode and a gate electrode and a diode having an anode electrode; and a fourth metal plate fixedly held on the lower surface of the insulating plate. (1) A collector main terminal which is fixed to the upper surface of one metal plate in an antiparallel connection and which is made of an electric conductor and is vertically raised from the surface of the first metal plate to be connected and fixed; Main terminal and emitter control terminal vertically rising from the surface and connected and fixed, a gate control terminal made of an electric conductor vertically rising and connected and fixed from the third metal plate surface, emitter electrode and second metal Connect to the board A wire, a conducting wire for connecting the anode electrode and the second metal plate, and a conducting wire for connecting the gate electrode and the third metal plate, and in a case, an insulating plate, each metal plate, each terminal, In a semiconductor device in which each conductive wire is enclosed together with a coating material, a collector auxiliary terminal electrically connected to the first metal plate and capable of exchanging electricity with a protection circuit, and a second metal plate electrically It is provided with an emitter auxiliary terminal which is connected and enables the exchange of electricity with the protection circuit.

The collector electrode is electrically connected to the collector main terminal, the gate electrode is electrically connected to the gate control terminal, and the emitter electrode is electrically connected to the emitter main terminal and the emitter control terminal. In a semiconductor device in which a main current is controlled by a voltage applied between a gate control terminal and an emitter control terminal, a collector auxiliary terminal electrically connected to a collector electrode and an emitter auxiliary terminal electrically connected to an emitter electrode A protective circuit may be provided between the collector auxiliary terminal and the emitter auxiliary terminal to absorb a surge voltage generated by the current change of the main current and the wiring inductance held by each main terminal. is there.

[0010]

In this structure, the surge voltage generated by the interaction between the current change rate of the main current flowing through the main terminal and the wiring inductance in the semiconductor device held by the main terminal is the surge voltage generated by the collector auxiliary terminal and the emitter auxiliary terminal. Since the terminals are used to guide and be absorbed by the protection circuit, dielectric breakdown of the semiconductor element can be prevented. Further, it is possible to eliminate the current imbalance by being guided to a protection circuit in which a circuit composed of a resistor and a capacitor is connected in a cross.

[0011]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a plan view showing a semiconductor device of an embodiment according to the present invention. As an example of a semiconductor device, I
1 shows a module structure of GBT. 2 is a side view of the semiconductor device of FIG. Referring to FIG. 1 and FIG. 2 at the same time, regarding the configuration of the semiconductor device of the present invention,
Next, a description will be given.

An insulating plate 2 is fixed to the upper surface of the fourth metal plate 1 which also serves as a cooling fin. The first metal plate 3, the second metal plate 5, and the third metal plate 4, which are electric conductors, are fixed to the upper surface of the insulating plate 2. The first metal plate 3 as a collector electrode
On the upper surface of the diode 7 and the IGB as a semiconductor element.
T6 and T6 are fixed so as to form an antiparallel circuit.

The emitter electrode 18 fixed to the upper surface of the IGBT 6 has a plurality of conductive wires 14 on the second metal plate 5.
Connected by. The anode electrode 19 fixed to the upper surface of the diode 7 is connected to the second metal plate 5 by a plurality of conducting wires 15.

On the first metal plate 3, a collector main terminal 8 made of an electric conductor and a newly provided collector auxiliary terminal 12 made of an electric conductor stand upright vertically from the surface of the first metal plate 3. And is electrically connected and fixedly connected. That is, the collector auxiliary terminal 12 is connected to the first metal plate 3
It is an auxiliary terminal that is electrically connected to the outside of the case 20 and is capable of exchanging electricity with a protection circuit described later.

On the second metal plate 5, the emitter main terminal 9 and the emitter control terminal 10 made of an electric conductor, and the emitter auxiliary terminal 13 also made of a newly installed electric conductor are provided on the second metal plate 5. Stand up vertically and slenderly from the surface,
It is electrically conducting and is connected and fixed. That is, the emitter auxiliary terminal 13 is an auxiliary terminal that is electrically connected to the second metal plate 5 and is outside the case 20 and that can exchange electricity with a protection circuit described later.

Further, the gate electrode 17 fixed to the upper surface of the IGBT 6 is connected to the third metal plate 4 by a conductive wire 16, and the third metal plate 4 has a gate made of an electric conductor. The control terminal 11 rises vertically from the surface of the third metal plate 4, electrically conducts, and is connected and fixed.

Then, in the case 20, the above metal plates, terminals, etc. are enclosed together with a coating material to form a semiconductor device.

In such a semiconductor device, the main current flowing through the collector main terminal 8 and the emitter main terminal 9 is controlled by the voltage applied between the gate control terminal 11 and the emitter control terminal 10.

The collector main terminal 8, the collector auxiliary terminal 12, and the first metal plate 3 may be the same electric conductor. Even if the main emitter terminal 9, the emitter control terminal 10, the auxiliary emitter terminal 13 and the second metal plate 5 are the same conductor, the gate control terminal 11 and the third metal plate 4 are the same conductor. It is possible to have it.

FIG. 3 is a diagram showing an equivalent circuit of the semiconductor device of FIG. The same reference numerals as those in FIG. 1 are given to the portions corresponding to the reference numerals of the respective portions shown in the equivalent circuit of FIG.

The collector main terminal 8 and the collector auxiliary terminal 12 share the wiring inductance held by the first metal plate 3, but the influence of the wiring inductance is not the same at each terminal. That is, even if a surge current occurs in the collector main terminal 8 side due to the main current flowing through the collector main terminal 8 and the current variation rate of the wiring inductance 38 and the main current on the collector main terminal 8 side, the collector auxiliary terminal 1
A current that is so large as to correspond to the main current does not flow in 2, so a voltage that can be called a surge voltage does not occur. that is,
This is because the current flowing through the collector auxiliary terminal 12 has a small value that is used for the control signal.

The same can be said for each terminal on the emitter side connected to the second metal plate 5, and depending on the wiring inductance 39 on the emitter main terminal 9 side and the current change rate of the main current, the emitter main terminal 9 Side, a surge voltage is generated, but no surge voltage is generated on the emitter auxiliary terminal 13 side.

The above-described functions of the newly provided collector auxiliary terminal 12 and emitter auxiliary terminal 13 will be further described by using a semiconductor device as a three-phase inverter device.

FIG. 4 shows a case where the semiconductor device of the present invention is used.
FIG. 6 is a diagram showing an equivalent circuit for one phase when a phase inverter device is configured. This will be described next.

IGBTs 6a, 6 provided as a pair
b, the diodes 7a and 7b are connected to the DC power source 33 and the inductive load 30 as shown in the figure. The IGBTs 6a, 6
b and the diodes 7a and 7b are integrated in a module.
May be converted into a package.

Reference numerals 38a and 38b, 39a and 39b are wiring inductances in the semiconductor device, and 29 is a main circuit wiring inductance. Reference numerals 31 and 32 are drive circuits for the respective IGBTs. In addition, capacitors 34 and 35, resistors 36 and 37
The protection circuit consisting of is the main circuit wiring inductance 2
An overvoltage is applied by the surge voltage generated at 9,
The purpose is to prevent the IGBTs 6a and 6b from being destroyed.

In such a circuit configuration, the IGBT 6
a is off and the IGBT 6b is on, and the inductive load 3
When the IGBT 6b is turned off from the state in which the load current is flowing to 0, the load current that has been flowing until then continues to flow through the diode 7a due to the influence of the inductive load 30. Then, when the IGBT 6b is turned on again in this state, the load current flowing in the diode 7a is changed to the IGBT 6
The commutation operation to move to b occurs, and the diode 7a reversely recovers.

That is, when the turn-off of the self-arm IGBT is turned off and the diode reversely recovers by turning on of the anti-arm IGBT, the wiring inductances 38a, 38b, 39a, and 39b produces | generates a surge voltage in the same direction as the DC power supply 33 which is a main power supply.

At this time, the surge voltage generated in the main circuit wiring inductance 29 can be suppressed by the surge absorbing circuit means as a protection circuit composed of the capacitors 34 and 35 and the resistors 36 and 37. However, the surge voltage generated in the wiring inductance 38a in the semiconductor device is
It is applied as an overvoltage to the IGBT 6a and the diode 7a.

Therefore, by utilizing the collector auxiliary terminal 12a provided on the first metal plate 3 and the emitter auxiliary terminal 13a provided on the second metal plate 5, the wiring inductance 3
8a leads the surge voltage generated to the outside and is connected to these auxiliary terminals, for example, resistor 40 and capacitor 42.
It is absorbed by the surge absorbing circuit means as a protection circuit composed of.

As a result, the surge voltage generated in the wiring inductance 38a in the semiconductor device can be absorbed by the above protection circuit, and the IGBT 6a can be protected from the overvoltage.
Thus, the diode 7a can be protected.

Regarding the IGBT 6b and the diode 7b as well, a protection circuit composed of a resistor 41 and a capacitor 43 is provided for the collector auxiliary terminal 12b and the emitter auxiliary terminal 13b.
Can be connected and protected with.

Incidentally, in FIG. 4, the collector auxiliary terminal 12
a and the emitter auxiliary terminal 13a are provided inside the case without being provided outside the case 20, and the resistor 40 and the capacitor 42 are provided.
It is also possible to integrally incorporate the protection circuit configured by and the collector auxiliary terminal 12a and the emitter auxiliary terminal 13a into the semiconductor device. That is, the resistor 40 and the capacitor 42 are directly connected between the first metal plate and the second metal plate. In this case, there is no auxiliary terminal portion that is elongated and elongated, which is advantageous in terms of price. A simple surge absorbing circuit means composed of a resistor and a capacitor is preferable because it can be easily housed in the small case 20 and leads to a low cost.

FIG. 5 is a circuit diagram showing an example in which the IGBT as a semiconductor device according to the present invention is connected in parallel and applied to an inverter device, a power supply device or the like.

IGBT 6a, 6b, diode 7a, 7
Two semiconductor devices composed of b, etc. are connected to the collector main terminal 8
a, 8b and main emitter terminals 9a, 9b are connected in parallel.
Then, a circuit in which resistors 60, 61 and capacitors 62, 63 are connected in series to the collector auxiliary terminals 12a, 12b and the emitter auxiliary terminals 13a, 13b are connected in a crossing manner as shown in the figure.

In the above circuit, the collector auxiliary terminal 12a, the resistor 60, the capacitor 62, and the emitter auxiliary terminal 13b are connected on one side, and the collector auxiliary terminal 12b on the other side.
, Resistor 61, capacitor 63, and auxiliary emitter terminal 13a
Constitutes a plow-shaped connection circuit in which and are connected, that is, a crossing circuit means. As described above, the collector auxiliary terminals 12a, 12 provided on the first metal plate 3 are connected to the IGBT.
b and the emitter auxiliary terminal 13 provided on the second metal plate 5.
Since there are a and 13b, the auxiliary circuit group can be utilized to form a crossing circuit means as a protection circuit as shown in the figure.

As described above, with the plow-shaped protection circuit configuration, when the IGBTs connected in parallel are switched, a difference in ON voltage between the IGBTs causes a difference in switching time, which is a problem of current imbalance. Is
As described below, electricity is exchanged through the auxiliary terminal group to be eliminated.

For example, when the IGBT 6a is turned on first at the time of turning on, the capacitors 62 and 63 are discharged and the current changes, so that the wiring inductance 3
8a and 39a are in a direction in which the voltage applied to the IGBT 6a is low, and the wiring inductances 38b and 39b are IG.
A voltage is generated in the direction in which the voltage applied to BT6b increases.
Therefore, the IGBT 6b is easily turned on, and the current imbalance is suppressed.

On the other hand, at the time of turn-off, if the IGBT 6a is turned-off first, the capacitors 62 and 63 are charged, and the wiring inductances 38a and 3 are changed due to the change of the current.
9a generates a voltage in the direction in which the voltage applied to the IGBT 6a increases, and the wiring inductances 38b and 39b generate a voltage in the direction in which the voltage applied to the IGBT 6b decreases. Therefore, IGB
T6b is easily turned off and current imbalance is suppressed.

In FIG. 5 as well, a crossing circuit means composed of resistors 60 and 61 and capacitors 62 and 63, a collector auxiliary terminal 12a and an emitter auxiliary terminal 13a.
It is possible to provide the and inside the semiconductor device without providing the outside of the case 20 and to integrally integrate them in the semiconductor device in advance.
In this case as well, there is no elongated auxiliary terminal portion, which is advantageous in terms of price.

[0041]

According to the present invention, since the semiconductor device is provided with the collector auxiliary terminal and the emitter auxiliary terminal,
By connecting a protection circuit to these auxiliary terminals, the influence of the surge voltage due to the current change rate of the main current generated in the wiring inductance in the semiconductor device is prevented. As a result, the effect of preventing dielectric breakdown of the semiconductor element incorporated in the semiconductor device is obtained.

When two semiconductor devices are connected in parallel, by connecting a plow-shaped protection circuit to the auxiliary terminal, it is possible to eliminate the current imbalance which is a problem in parallel connection. .

[Brief description of drawings]

FIG. 1 is a plan view showing a semiconductor device of an embodiment according to the present invention.

FIG. 2 is a side view of the semiconductor device of FIG. 1;

FIG. 3 is a diagram showing an equivalent circuit of the semiconductor device of FIG.

FIG. 4 is a diagram showing an equivalent circuit for one phase when a three-phase inverter device is configured using the semiconductor device of the present invention.

FIG. 5 shows an IGBT as a semiconductor device according to the present invention,
FIG. 9 is a circuit diagram showing an example in which the components are connected in parallel and applied to an inverter device, a power supply device or the like.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... 4th metal plate, 2 ... Insulation plate, 3 ... 1st metal plate, 4 ... 3rd metal plate, 5 ... 2nd metal plate, 6 ... Semiconductor element, 7 ... Diode, 8 ... Collector main terminal, 9 ... Emitter main terminal, 1
0 ... Emitter control terminal, 11 ... Gate control terminal, 12 ...
Collector auxiliary terminal, 13 ... Emitter auxiliary terminal, 14, 1
5, 16 ... Lead wire, 17 gate electrode, 18 ... Emitter electrode, 19 ... Anode electrode, 20 ... Case, 38, 39 ...
Wiring inductance.

Claims (7)

[Claims] 1. A first metal plate, a second metal plate and a third metal plate made of an electric conductor, an insulating plate for fixing and holding the first, second and third metal plates on an upper surface thereof, and an insulating plate of the insulating plate. A fourth metal plate fixedly held on the lower surface, a semiconductor element having an emitter electrode and a gate electrode, and a diode having an anode electrode are fixed to the upper surface of the first metal plate in antiparallel connection. And a collector main terminal which is made of an electric conductor and vertically rises and is connected and fixed to the first metal plate surface, and a collector main terminal which is made of an electric conductor and vertically rises and is connected and fixed to the second metal plate surface. An emitter main terminal and an emitter control terminal,
A gate control terminal which is made of an electric conductor and stands upright from the surface of the third metal plate and is fixedly connected thereto; a conductor wire which connects the emitter electrode and the second metal plate; the anode electrode and the first electrode. (2) A conductor for connecting the metal plate and a conductor for connecting the gate electrode and the third metal plate are provided. In the case, the insulating plate, each metal plate, each terminal, and each conductor are coated with a coating material. In a semiconductor device encapsulated together, a collector auxiliary terminal electrically connected to the first metal plate and capable of exchanging electricity with the protection circuit, and a protection circuit electrically connected to the second metal plate A semiconductor device provided with an emitter auxiliary terminal capable of exchanging electricity with the semiconductor device. 2. The protection circuit according to claim 1, wherein the protection circuit is surge absorbing circuit means for absorbing a surge voltage generated at each of the main terminals between the collector auxiliary terminal and the emitter auxiliary terminal. Semiconductor device. 3. The collector circuit according to claim 1, wherein the collector main terminals and the emitter main terminals are connected in parallel and the semiconductor devices are arranged side by side, the protection circuit includes one of the collector auxiliary terminals and the other of the emitters. It is a combing circuit means in which a circuit composed of a resistor and a capacitor connected in series is connected between the auxiliary terminal and the other collector auxiliary terminal and one of the emitter auxiliary terminals in a crossed manner. A semiconductor device characterized by: 4. A first metal plate, a second metal plate, and a third metal plate made of an electric conductor, an insulating plate for fixing and holding the first, second, and third metal plates on an upper surface, and the insulating plate. A fourth metal plate fixedly held on the lower surface, a semiconductor element having an emitter electrode and a gate electrode, and a diode having an anode electrode are fixed to the upper surface of the first metal plate in antiparallel connection. And a collector main terminal which is made of an electric conductor and vertically rises and is connected and fixed to the first metal plate surface, and a collector main terminal which is made of an electric conductor and vertically rises and is connected and fixed to the second metal plate surface. An emitter main terminal and an emitter control terminal,
A gate control terminal which is made of an electric conductor and stands upright from the surface of the third metal plate and is fixedly connected thereto; a conductor wire which connects the emitter electrode and the second metal plate; the anode electrode and the first electrode. (2) A conductor for connecting the metal plate and a conductor for connecting the gate electrode and the third metal plate are provided. In the case, the insulating plate, each metal plate, each terminal, and each conductor are coated with a coating material. A semiconductor device which is sealed together, wherein a protection circuit that absorbs a surge voltage generated at each of the main terminals is provided between the first metal plate and the second metal plate. . 5. A first metal plate, a second metal plate, and a third metal plate made of an electric conductor, an insulating plate for fixing and holding the first, second, and third metal plates on an upper surface, and the insulating plate. A fourth metal plate fixedly held on the lower surface, a semiconductor element having an emitter electrode and a gate electrode, and a diode having an anode electrode are fixed to the upper surface of the first metal plate in antiparallel connection. And a collector main terminal which is made of an electric conductor and vertically rises and is connected and fixed to the first metal plate surface, and a collector main terminal which is made of an electric conductor and vertically rises and is connected and fixed to the second metal plate surface. An emitter main terminal and an emitter control terminal,
A gate control terminal which is made of an electric conductor and stands upright from the surface of the third metal plate and is fixedly connected thereto; a conductor wire which connects the emitter electrode and the second metal plate; the anode electrode and the first electrode. (2) A conductor for connecting the metal plate and a conductor for connecting the gate electrode and the third metal plate are provided. In the case, the insulating plate, each metal plate, each terminal, and each conductor are coated with a coating material. A semiconductor device which is encapsulated together, wherein two sets of the insulating plate, each metal plate, each terminal, and each conductor wire are encapsulated together with a coating material in the case, Between the plate and the second metal plate on the other side, and between the first metal plate on the other side and the second metal plate on the one side, a protection circuit in which a resistor and a capacitor are connected in series is provided in a hook. A semiconductor device characterized by the above. 6. A collector electrode conducting to a collector main terminal, a gate electrode conducting to a gate control terminal, and an emitter electrode conducting to an emitter main terminal and an emitter control terminal. In a semiconductor device in which a main current is controlled by a voltage applied between the gate control terminal and the emitter control terminal, a collector auxiliary terminal electrically connected to the collector electrode,
An emitter auxiliary terminal connected to the emitter electrode is provided, and a surge generated between the collector auxiliary terminal and the emitter auxiliary terminal due to a current change of the main current and a wiring inductance held by each main terminal. A semiconductor device having a protection circuit for absorbing a voltage. 7. The semiconductor device according to claim 2, 4, or 6, wherein the protection circuit is formed by connecting a resistor and a capacitor in series.