JPH0855920A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

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Publication number
JPH0855920A
JPH0855920A JP6191534A JP19153494A JPH0855920A JP H0855920 A JPH0855920 A JP H0855920A JP 6191534 A JP6191534 A JP 6191534A JP 19153494 A JP19153494 A JP 19153494A JP H0855920 A JPH0855920 A JP H0855920A
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Japan
Prior art keywords
film
mask material
material film
mask
step
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JP6191534A
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Japanese (ja)
Inventor
Seiichi Aritome
Tetsuo Endo
Riichiro Shirata
誠一 有留
理一郎 白田
哲郎 遠藤
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Toshiba Corp
株式会社東芝
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Priority to JP6191534A priority Critical patent/JPH0855920A/en
Publication of JPH0855920A publication Critical patent/JPH0855920A/en
Application status is Pending legal-status Critical

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Abstract

PURPOSE:To form a line-and-space pattern having a pitch narrower than the smallest pitch determined by PEP, and also to contribute to the microscopic formation and high integration of an element by a method wherein a conductive film is selectively etched using the mask material film left on the side wall part of a stripe-like pattern. CONSTITUTION:A semiconductor device, having a plurality of paralleled stripe- like conductive film pattern on a semiconductor substrate 11, is manufactured. In that case, a conductive film 15 is formed on the semiconductor substrate 11, first mask material film 16 is formed thereon, and the first mask material film 16 is patterned into stripe form. Then, second mask material film 19, which is different from the above-mentioned films, is formed on the conductive film 15 and the first mask material film 16, and the second mask material film 19 is left on the side wall only of the stripe-formed pattern by etching the whole surface of the second mask material film 19. Then, the first mask material film 16 is removed, and the conductive film 15 is selectively etched using the second mask material film 19 as a mask.

Description

【発明の詳細な説明】 DETAILED DESCRIPTION OF THE INVENTION

【0001】 [0001]

【産業上の利用分野】本発明は、半導体装置の製造方法に係わり、特にNANDセル型EEPROMの制御ゲート等のような微小ピッチのストライプ状パターンを有する素子の製造に適した半導体装置の製造方法に関する。 The present invention relates relates to a method of manufacturing a semiconductor device, in particular a method of manufacturing a semiconductor device suitable for the manufacture of elements having a micro pitch stripe pattern, such as the control gates of the NAND cell type EEPROM on.

【0002】 [0002]

【従来の技術】近年、電気的書替え可能でかつ高集積化可能なEEPROMとして、複数のメモリセルを直列接続してNANDセルを構成するものが知られている。 In recent years, as an electrical rewritable and highly integrable EEPROM, it is known what constitutes a NAND cell a plurality of memory cells connected in series. 図8はその様なEEPROMの1つのNANDセルを示す平面図であり、図9(a)(b)はそれぞれ図8のA− Figure 8 is a plan view showing one NAND cell of such EEPROM, FIG. 9 (a) (b) is, respectively, of FIG 8 A-
A′及びB−B′断面を示す。 It shows the A 'and B-B' cross section. p型シリコン基板(又はn型シリコン基板にp型ウェルが形成されたウェハ)1 p-type silicon substrate (or wafer p-type well is formed in the n-type silicon substrate) 1
の素子分離絶縁膜2で囲まれた領域にこの例では、8個のメモリセルM1〜M8と2つの選択ゲート・トランジスタS1,S2を持つNANDセルが配列形成されている。 In this example the region surrounded by the element isolation insulating film 2, NAND cells are arranged formed with eight memory cells M1~M8 and two select gate transistors S1, S2.

【0003】NANDセルを構成するメモリセルは、基板1上に熱酸化膜からなる第1ゲート絶縁膜3を介して第1層多結晶シリコン膜による浮遊ゲート4(4 1 ,4 [0003] Memory cells constituting the NAND cell is suspended by the first-layer polycrystalline silicon film through a first gate insulating film 3 made of a thermal oxide film on the substrate 1 a gate 4 (4 1, 4
2 ,…)が形成され、さらに酸化膜からなる第2ゲート絶縁膜5を介して第2層多結晶シリコン膜による制御ゲート6(6 1 ,6 2 ,…)が形成されている。 2, ...) are formed, and further the control gate 6 by the second layer polycrystalline silicon film via a second gate insulating film 5 made of oxide film (6 1, 6 2, ...) are formed. 選択ゲート・トランジスタS1,S2のゲート絶縁膜はゲート絶縁膜5と同時に形成され、それらのゲート電極8 1 ,8 The gate insulating film of the select gate transistors S1, S2 are formed simultaneously with the gate insulating film 5, these gate electrodes 81, 82
2は制御ゲート6と同時に形成されている。 2 is formed simultaneously with the control gate 6. 各メモリセルの制御ゲート6は行方向に連続的に形成されてワード線となる。 It is continuously formed on the control gate 6 the row direction of the memory cell in the word line. 各メモリセル間は、ソース,ドレインとなるn型拡散層7が形成されて、ソース,ドレインを隣接するもの同士で共用する直列接続されて、NANDセルが構成されている。 Between each memory cell, a source, n-type diffusion layer 7 serving as a drain is formed, the source, are serially connected is shared by adjacent ones of the drain, NAND cell is formed.

【0004】この様なNANDセルを形成するに当り、 [0004] per to form such a NAND cell,
浮遊ゲートと制御ゲートとは自己整合的にパターン形成される。 The floating gate and the control gate are self-aligned patterned. その工程を簡単に説明すれば、まず基板上に第1ゲート絶縁膜を介して第1層多結晶シリコン膜を堆積する。 To briefly explain the process, first, depositing a first layer polycrystalline silicon film through a first gate insulating film on the substrate. この第1層多結晶シリコン膜に、ワード線方向に並ぶメモリセルの浮遊ゲートを分離するため、素子領域に位置する分離溝を形成した後、その上に第2ゲート絶縁膜を介して第2層多結晶シリコン膜を堆積する。 This first-layer polycrystalline silicon film, in order to separate the floating gates of the memory cells arranged in the word line direction, after formation of the separation groove located in the element region, a through the second gate insulating film thereon 2 depositing a layer of polycrystalline silicon film. そしてPEP工程によりレジストパターンを形成して、これをマスクとして反応性イオンエッチング法により、第2 And by forming a resist pattern by PEP process, by reactive ion etching as a mask, the second
層多結晶シリコン膜、第2ゲート絶縁膜続いて第1層多結晶シリコン膜を順次選択エッチングして、制御ゲート及び浮遊ゲートを分離形成する。 Layer polycrystalline silicon film, are sequentially selected etching the second gate insulating film followed by the first-layer polycrystalline silicon film, to separate form the control gate and the floating gate.

【0005】このNANDセル型EEPROMの書込み、消去の動作は、基板1と浮遊ゲート4間のトンネル電流による電荷の授受により行われる。 [0005] Writing of the NAND cell type EEPROM, the operation of erasure is carried out by exchange of charge between the substrate 1 by a tunneling current between the floating gate 4. 例えば一括消去の方法は、全てのメモリセルの制御ゲート及び選択ゲートに高電位を印加し、NANDセルのドレインに繋がるビット線及びNANDセルの共通ソース線を接地する。 For example the method of collective erasing, a high potential is applied to the control gates and select gates of all the memory cells, grounding the common source line of leading to the drain of the NAND cell bit line and the NAND cell.
これにより、全てのメモリセルで基板から浮遊ゲートに電子が注入され、しきい値が正方向に移動した状態“1”が得られる。 Thus, electrons from the substrate in all of the memory cells in the floating gate are injected, the threshold is the state "1" which is moved in the positive direction is obtained. 書込みは、ソース側のメモリセルM Writing is on the source side memory cell M
8から順に行われる。 8 is made to order from.

【0006】まず、メモリセルM8の制御ゲートと共有ソース及びソース側選択ゲートを接地し、残りの制御ゲートとドレイン(即ちビット線)に光電位を印加する。 [0006] First, it grounded and the control gate of the memory cell M8 shared source and the source-side select gate, applying a light potential to the rest of the control gate and the drain (i.e. bit line).
これにより、ビット線の高電位はメモリセルM8のドレインまで伝達され、このメモリセルM8で浮遊ゲートの電子がドレイン拡散層に放出されてしきい値が負方向に移動する。 Thus, the high potential of the bit line is transmitted to the drain of the memory cell M8, the electrons in the floating gate in the memory cell M8 is released to the drain diffusion layer threshold is moved in the negative direction. つまり“0”書込みがなされる。 That is "0" writing is done. 以下、メモリセルM7,M6,…の順にデータ書き込みがなされる。 Below, the memory cell M7, M6, ... the data writing in the order of is made. データ読出しは、選択メモリセルの制御ゲート及び共通ソース線を接地し、残りの制御ゲートと選択ゲートに電源電位を与えて、電流の有無を検出することにより行われる。 Data read is grounded control gate and a common source line of the selected memory cell, giving power source potential to the selection gate and the rest of the control gate is performed by detecting the presence or absence of current.

【0007】このNANDセル型EEPROMは、従来のNOR型と比べるとコンタクト数が大幅に減少し、高集積化が可能であるという利点を有する。 [0007] The NAND cell type EEPROM, as compared to conventional NOR type number of contacts is significantly reduced, has the advantage of being highly integrated. しかしながら、これをさらに高集積化しようとする場合、まだ問題が残っている。 However, when trying to further high integration of this, there are still a problem. 即ち、制御ゲートと浮遊ゲートはメモリセル毎に独立にパターン形成されなければならない。 That is, the control gate and the floating gate must be patterned independently for each memory cell. 従って、メモリセル間には必ずスペースが必要であり、この部分に隣接するメモリセルで共用されるソース,ドレイン拡散層が形成される。 Thus, between the memory cell is always required space, a source that is shared by memory cells adjacent to this portion, the drain diffusion layer is formed. そして、従来の制御ゲートと浮遊ゲートのパターニング工程では、制御ゲート間ピッチはPEP用ステッパの露光技術により決定され、加工限界以上の微細ピッチを得ることができなかった。 Then, in the step of patterning the conventional control gate and a floating gate, a control gate pitch is determined by the exposure technique of PEP for stepper, it was not possible to obtain a processing limit or more fine pitch.

【0008】同様の問題は、制御ゲート型のEEPRO [0008] A similar problem, EEPRO of the control gate type
Mに限らず、MNOS型のメモリセルを用いたNAND Not limited to M, NAND using the MNOS type memory cell
セル型のEEPROMにもある。 There is also the cell type of EEPROM. また、EEPROMに限らず、チャネルイオン注入等により情報を固定的に書き込んだMOSトランジスタをメモリセルとする所謂マスクROMにおいても、NANDセル構成とする場合には同様の問題がある。 Further, not limited to the EEPROM, even in so-called mask ROM a MOS transistor of writing information in a fixed manner by the channel ion implantation or the like to the memory cell, in the case of a NAND cell structure have similar problems.

【0009】 [0009]

【発明が解決しようとする課題】このように、従来のN [Problems that the Invention is to Solve] In this way, the conventional N
ANDセル型EEPROMの製造工程では、制御ゲート間ピッチを十分小さくすることができず、これがさらなる高集積化を阻害しているという問題があった。 In the manufacturing process of the AND-cell type EEPROM, not a control gate pitch can be made sufficiently small that this is a problem that has inhibited further high integration. また、 Also,
上記の問題はEEPROMに限らず、狭いピッチのライン&スペース・パターンを有する各種の半導体装置の製造に関して同様に言えることである。 The above problem is not limited to the EEPROM, it is true as well for the production of various types of semiconductor devices having a line and space pattern of narrow pitches.

【0010】本発明は、上記事情を考慮してなされたもので、その目的とするところは、通常のリソグラフィ(PEP)で決まる最小ピッチよりも狭いピッチのライン&スペース・パターンを形成することができ、素子の微細化及び高集積化に寄与し得る半導体装置の製造方法を提供することにある。 [0010] The present invention has been made in view of these circumstances, it is an object to form a narrow pitch line and space patterns than the minimum pitch determined by the ordinary lithography (PEP) It can, is to provide a method of manufacturing a semiconductor device that can contribute to miniaturization and high integration of devices.

【0011】 [0011]

【課題を解決するための手段】上記課題を解決するために本発明は、次のような構成を採用している。 The present invention in order to solve the above problems SUMMARY OF THE INVENTION adopts the following configuration. 即ち本発明は、半導体基板上に複数本の平行なストライプ状の導電膜パターンを有する半導体装置の製造方法において、 That is, the present invention provides a method of manufacturing a semiconductor device having a plurality of parallel stripe-like conductive film pattern on a semiconductor substrate,
半導体基板上に導電膜を形成した後、この導電膜上に第1のマスク材料膜を形成し、次いで第1のマスク材料膜をストライプ状にパターン加工し、次いで導電膜及び第1のマスク材料膜上にこれらとは異なる第2のマスク材料膜を形成し、次いで第2のマスク材料膜を全面エッチングしストライプ状パターンの側壁部のみに残し、次いで第1のマスク材料膜を除去したのち、第2のマスク材料膜をマスクに導電膜を選択エッチングすることを特徴とする。 After forming a conductive film on a semiconductor substrate, the first mask material film is formed and then the first mask material layer is patterned in stripes, then conductive film and the first mask material on the conductive film After forming the different second mask material film to these on the membrane, then the second mask material film remains only on the sidewalls of the entire etched stripe pattern, and then removing the first mask material film, wherein the selective etching of the conductive film a second mask material layer as a mask.

【0012】また本発明は、半導体基板上に浮遊ゲートと制御ゲートを積層した不揮発性メモリセルを複数個直列接続してNANDセルを構成し、NANDセルを複数個列形成されて構成される半導体装置の製造方法において、半導体基板上に第1のゲート絶縁膜を介して浮遊ゲートとなる第1層多結晶シリコン膜を形成し、次いでこの第1層多結晶シリコン膜をワード線方向に隣接する素子間で分離するように加工し、次いで基板全面に第2のゲート絶縁膜を介して制御ゲートとなる第2層多結晶シリコン膜を形成し、次いで第2層多結晶シリコン膜上に第1のマスク材料膜を形成し、次いで第1のマスク材料膜をストライプ状にパターン加工し、次いで基板全面に第2層多結晶シリコン膜及び第1のマスク材料膜とは異なる材質の第2の [0012] The present invention is a non-volatile memory cells formed by laminating a floating gate and a control gate on a semiconductor substrate and a plurality of serially connected constitute a NAND cell, semiconductor composed of NAND cells is plural rows formed the method of manufacturing a device, the first-layer polycrystalline silicon film serving as a floating gate via a first gate insulating film formed on a semiconductor substrate, and then adjacent the first layer polycrystalline silicon film in the word line direction processed so as to separate between elements, then the first to the second layer polycrystalline silicon film is formed, and then on the second-layer polycrystalline silicon film serving as a control gate via a second gate insulating film on the entire surface of the substrate mask material film is formed and then the first mask material layer is patterned in stripes, followed by a second material different from the second layer polycrystalline silicon film and the first mask material film on the entire surface of the substrate of スク材料膜を形成し、次いで第2のマスク材料膜を全面エッチングしストライプ状パターンの側壁部のみに残し、次いで第1のマスク材料膜を除去したのち、第2のマスク材料膜をマスクに第2多結晶シリコン膜,第2ゲート絶縁膜,第1多結晶シリコン膜を順次エッチングすることを特徴とする。 After disk material film is formed and then the second mask material film remains only on the sidewalls of the entire etched stripe pattern, and then removing the first mask material layer, the second mask material layer as a mask 2 polycrystalline silicon film, a second gate insulating film, characterized by sequentially etching the first polysilicon film.

【0013】 [0013]

【作用】本発明によれば、第1のマスク材料膜の側壁に残す第2のマスク材料膜の幅は通常のPEPで決まる最小寸法よりも小さくすることができ、さらに隣接する第2のマスク材料膜間の距離もPEPで決まる最小寸法よりも小さくすることができる。 According to the present invention, the width of the second mask material film left on the side walls of the first mask material film can be made smaller than the minimum size determined by the ordinary PEP, the second mask further adjacent the distance between the material film can also be smaller than the minimum dimension determined by PEP. 従って、第2のマスク材料膜を用いた導電膜のエッチングにより、導電膜のライン&スペースのピッチを極めて狭くすることができ、これにより半導体装置の高集積化が可能となる。 Therefore, the etching of the conductive film using the second mask material film, it is possible to extremely narrow the pitch of the lines and spaces of the conductive film, thereby it is possible to highly integrated semiconductor device.

【0014】特に、NANDセル型EEPROMのゲート加工に適用した場合、ゲート間スペースをPEPによる加工限界以下の微細なものとすることができ、従ってNANDセル型EEPROMの高集積化をはかることが可能となる。 [0014] Particularly, when applied to the gate processing of a NAND cell type EEPROM, the gate space can be made working limit or less fine by PEP, therefore can achieve high integration of the NAND cell type EEPROM to become.

【0015】 [0015]

【実施例】以下、本発明の実施例を図面を参照して説明する。 EXAMPLES Hereinafter, an embodiment of the present invention with reference to the drawings. なお、以下の実施例ではEEPROMに適用した場合を説明するが、本発明はこれに限らず各種の半導体装置に適用できるのは勿論である。 As will be described an application of the EEPROM in the following examples, it is of course the present invention can be applied to various semiconductor devices is not limited thereto.

【0016】図1〜図6は、本発明の第1の実施例に係わるNANDセル型EEPROMの製造工程を示す図である。 [0016] Figures 1-6 are diagrams showing the manufacturing process of the NAND cell type EEPROM according to a first embodiment of the present invention. なお、これらの図において(a)は断面図、 In these figures (a) is a sectional view,
(b)は平面図である。 (B) is a plan view.

【0017】まず、図1(a)に示すように、シリコン基板11上の素子形成領域の表面に厚さ10nm程度の熱酸化膜(トンネル酸化膜)12を形成し、その上に浮遊ゲートとなる第1層多結晶シリコン膜13を堆積する。 [0017] First, as shown in FIG. 1 (a), a silicon substrate thermally oxidized film having a thickness of about 10nm on the surface of the element formation regions on the 11 (tunnel oxide film) 12 is formed, and a floating gate on its a first layer polycrystalline silicon film 13 of depositing. 第1層多結晶シリコン膜13には、ワード線方向のメモリセルの浮遊ゲートを分離形成するための分離溝を形成する。 The first-layer polycrystalline silicon film 13, to form a separation groove for separating form the floating gate of the word line direction of the memory cell. その後、シリコン熱酸化膜換算で25〜15 Then, 25 to 15 with a silicon thermal oxide film in terms of
nm程度の第2ゲート絶縁膜14を形成し、その上に制御ゲートとなる第2層多結晶シリコン膜15を堆積する。 A second gate insulating film 14 of about nm is formed, depositing a second layer polycrystalline silicon film 15 serving as a control gate thereon. さらにこの上にCVDシリコン酸化膜(又はCVD Further CVD silicon oxide film on the (or CVD
シリコン窒化膜)16を堆積形成し、レジストパターン17をマスクにCVDシリコン酸化膜16をストライプ状にパターン形成する。 The silicon nitride film) 16 is deposited on, patterning a CVD silicon oxide film 16 using the resist pattern 17 as a mask in stripes. このストライプ状パターンは、 The stripe-like pattern,
例えば線幅を0.3μm、線間隔を1.1μmとする。 For example, the line width 0.3 [mu] m, the line interval between 1.1 .mu.m.

【0018】なお、図1(b)は上記の酸化膜16のパターニング後にレジストパターン17を除去した状態を示している。 [0018] Incidentally, FIG. 1 (b) shows a state in which the resist pattern 17 is removed after patterning of the oxide film 16. また、図中の18は素子分離酸化膜で囲まれた素子領域を示している。 Also, 18 in the figure shows the element region surrounded by the isolation oxide film.

【0019】次いで、図2(a)に示すように、基板上の全面にCVDシリコン窒化膜(又CVDシリコン酸化膜)19を堆積する。 [0019] Then, as shown in FIG. 2 (a), depositing a CVD silicon nitride film (also CVD silicon oxide film) 19 on the entire surface of the substrate. その後、図2(b)に示すように、CVDシリコン酸化膜16のストライプパターンの両端部を覆うようにレジストを21を形成する。 Thereafter, as shown in FIG. 2 (b), a resist 21 to cover the both end portions of the stripe pattern of the CVD silicon oxide film 16. また、 Also,
この状態における図2(b)の矢視A−A′断面構造を図3に示す。 Showing the arrow A-A 'sectional structure shown in FIG. 2 (b) in the state in FIG. 図中の22は素子分離酸化膜である。 22 in the figure is a device isolation oxide film.

【0020】次いで、図4(a)に示すように、CVD [0020] Then, as shown in FIG. 4 (a), CVD
シリコン窒化膜19を反応性イオンエッチングにより全面エッチングして、CVDシリコン酸化膜16のストライプパターンの側壁にのみCVDシリコン窒化膜19を残す。 The silicon nitride film 19 is entirely etched by reactive ion etching, leaving a CVD silicon nitride film 19 only on the side wall of the stripe pattern of the CVD silicon oxide film 16. CVDシリコン酸化膜16の側壁に残ったCVD CVD remaining on the side wall of the CVD silicon oxide film 16
シリコン窒化膜19の幅は、例えば0.4μmとする。 The width of the silicon nitride film 19 is, for example, 0.4 .mu.m.
ここで、図4(b)に示すように、前記レジスト21により覆われた部分のCVDシリコン窒化膜19も残ることになる。 Here, as shown in FIG. 4 (b), it will remain even CVD silicon nitride film 19 of the portion covered by the resist 21.

【0021】次いで、CVDシリコン酸化膜16をエッチング除去したのち、図5(a)に示すように、全面にフォトレジスト23を塗布する。 [0021] Then, after the CVD silicon oxide film 16 is removed by etching, as shown in FIG. 5 (a), a photoresist 23 on the entire surface. そして、これを露光描画して、図5(b)に示すように、レジスト23に開口部24を形成する。 Then, this was exposed drawing, as shown in FIG. 5 (b), to form an opening 24 in the resist 23. 続いて、レジストの開口部24に露出したCVDシリコン窒化膜19をエッチングしたのち、レジスト23を除去する。 Subsequently, after the CVD silicon nitride film 19 exposed in the opening 24 of the resist is etched, the resist 23 is removed. なお、図中の25は制御ゲートのコンタクト領域である。 Incidentally, 25 in the figure is a contact region of the control gate.

【0022】図5において、CVDシリコン窒化膜19 [0022] In FIG. 5, CVD silicon nitride film 19
をレジスト23をマスクに用いて特定の箇所のみエッチングするのは次のためである。 The it is because follows to etch only specific locations using the resist 23 as a mask. 図においてCVDシリコン窒化膜19はCVDシリコン酸化膜16のストライプパターンの側壁に付いているが、CVDシリコン酸化膜16のパターンのエッジ部を経由し、側壁に付着したC Although CVD silicon nitride film 19 is attached to the side wall of the stripe pattern of the CVD silicon oxide film 16 in FIG., Via an edge portion of the pattern of the CVD silicon oxide film 16 was deposited on the side wall C
VDシリコン窒化膜19はCVDシリコン酸化膜16のパターンの両側で繋がっている。 VD silicon nitride film 19 is connected on both sides of the pattern of the CVD silicon oxide film 16. よってCVDシリコン窒化膜19をマスクにエッチングした第2層多結晶シリコン層(制御ゲートとして使用)も隣り合う線同士でショートする形となってしまう。 Therefore it becomes form of short CVD silicon nitride film 19 (used as a control gate) second-layer polycrystalline silicon layer is etched to mask at adjoining lines together. それを避けるために、レジスト23を用いてエッジ部のCVDシリコン窒化膜1 To avoid it, CVD silicon nitride film 1 of the edge portion using a resist 23
9のみエッチングする。 9 only etching.

【0023】次いで、図6(a)に示すように、CVD [0023] Then, as shown in FIG. 6 (a), CVD
シリコン窒化膜19をマスクとして用い、反応性イオンエッチングにより第2層多結晶シリコン膜15,第2ゲート絶縁膜14及び第1層多結晶シリコン膜13を同時にエッチングする。 A silicon nitride film 19 as a mask, simultaneously etching the second layer polycrystalline silicon film 15, the second gate insulating film 14 and the first layer polycrystalline silicon film 13 by reactive ion etching. これにより、NANDセル内の複数のメモリセルの制御ゲートと浮遊ゲートが自己整合で分離形成される。 Thus, the control gate and the floating gates of the memory cells in the NAND cell is formed separated in a self-aligned. なお、図6(b)には、上記工程により形成された第2層多結晶シリコン15からなる制御ゲートパターンを示している。 Incidentally, in FIG. 6 (b) shows a control gate pattern including the second-layer polycrystalline silicon 15 formed by the above process.

【0024】このように本実施例によれば、CVDシリコン酸化膜16のストライプパターンの側壁にCVDシリコン窒化膜19をセルフアラインで残し、このCVD According to this embodiment, leaving CVD silicon nitride film 19 by self-alignment on the side walls of the stripe pattern of the CVD silicon oxide film 16, the CVD
シリコン窒化膜19をマスクに多結晶シリコン膜15, Polycrystalline silicon film 15 of silicon nitride film 19 as a mask,
13を選択エッチングすることにより、多結晶シリコン膜15,13を従来よりも狭いピッチでパターニングすることができる。 By selective etching 13, a polycrystalline silicon film 15, 13 can be patterned with a small pitch than before.

【0025】具体的には、フォトレジスト17の線幅と間隔が0.3μmと1.1μmのピッチ1.4μmのリソグラフィ可能なステッパを用いて、ゲート長とゲート間の間隔がそれぞれ0.4μmと0.3μm、つまりピッチ0.7μmのゲートパターンが形成できる。 [0025] Specifically, the photo line width and spacing of the resist 17 by lithography capable stepper pitch 1.4μm in 0.3μm and 1.1 .mu.m, the spacing between the gate length and a gate respectively 0.4μm and 0.3 [mu] m, i.e. pitch 0.7μm gate pattern can be formed. 従って、EEPROMにおける制御ゲートと浮遊ゲートをP Thus, the control gate and the floating gate in EEPROM P
EPで決まる最小ピッチよりも狭いピッチに形成することができ、NANDセルを構成するメモリセル間隔を微細なものとして、EEPROMの高集積化を実現することができる。 Can be formed in a narrow pitch than the minimum pitch determined by the EP, the memory cell spacing constituting a NAND cell as fine, it is possible to realize a high integration of EEPROM.

【0026】なお、本発明は上述した各実施例に限定されるものではない。 [0026] The present invention is not limited to the embodiments described above. 実施例では、第1,2層多結晶シリコン膜13,15及び第2ゲート絶縁膜14のエッチング時のマスク材としてCVDシリコン窒化膜19を用いたが、この代わりにCVDシリコン酸化膜を用いてもよい。 In embodiment uses a CVD silicon nitride film 19 as a mask material in etching the first and second layer polycrystalline silicon films 13 and 15 and the second gate insulating film 14, using the CVD silicon oxide film in this place it may be. この場合、CVDシリコン酸化膜16をCVDシリコン窒化膜とすればよい。 In this case, it suffices to CVD silicon oxide film 16 and CVD silicon nitride film.

【0027】また、図7(a)に示すように、CVDシリコン窒化膜19の膜の下に耐エッチング性を有する他のマスク材31を予め形成しておき、CVDシリコン窒化膜19にてマスク材31をパターニングする。 Further, as shown in FIG. 7 (a), formed in advance another mask member 31 having an etching resistance under the film of the CVD silicon nitride film 19, a mask by a CVD silicon nitride film 19 patterning the wood 31. 次いで、図7(b)に示すように、CVDシリコン窒化膜1 Then, as shown in FIG. 7 (b), CVD silicon nitride film 1
9のみを除去したのち、マスク材31を用いて第1,2 9 only after removing the, first and second by using the mask material 31
多結晶シリコン膜13,15及び第2ゲート絶縁膜14 Polycrystalline silicon films 13 and 15 and the second gate insulating film 14
を選択エッチングするようにしてもよい。 The may be selectively etched.

【0028】また、実施例ではNANDセル型EEPR [0028] In addition, NAND cell type in the embodiment EEPR
OMのゲートパターン形成について説明したが、本発明は微細ピッチのライン&スペース・パターンを有する各種の半導体装置の製造に適用することができる。 Has been described gate pattern formation of OM, the present invention can be applied to the manufacture of various semiconductor devices having a line and space pattern of fine-pitch. その他、本発明の要旨を逸脱しない範囲で、種々変形して実施することができる。 Other, without departing from the scope of the present invention can be modified in various ways.

【0029】 [0029]

【発明の効果】以上詳述したように本発明によれば、ストライプ上に形成した第1のマスク材料膜の側壁に第2 According to the present invention as described in detail above, according to the present invention, first the sidewalls of the first mask material film formed on the stripe 2
のマスク材料膜をセルフアラインで残し、この第2のマスク材料膜をマスクとして導電膜を選択エッチングすることにより、通常のリソグラフィ(PEP)で決まる最小ピッチよりも狭いピッチのライン&スペース・パターンを形成することができ、素子の微細化及び高集積化に寄与することが可能となる。 Leaving the mask material film in self-alignment, by selective etching the conductive film of this second mask material film as a mask, the narrow pitch line and space patterns than the minimum pitch determined by the ordinary lithography (PEP) can be formed, it is possible to contribute to miniaturization and high integration of devices.

【0030】特に、NANDセル型EEPROMのゲートパターンの加工に利用することにより、NANDセルを構成するメモリセル間隔を微細なものとして、EEP [0030] In particular, by utilizing the processing of the gate pattern of a NAND cell type EEPROM, the memory cell spacing constituting a NAND cell as fine, EEP
ROMの高集積化を実現することが可能となる。 It becomes possible to realize high integration of ROM.

【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS

【図1】本発明の一実施例に係わるNANDセル部の製造工程を示す断面図と平面図。 Sectional and plan views showing the manufacturing process of the NAND cell unit according to an embodiment of the present invention; FIG.

【図2】本発明の一実施例に係わるNANDセル部の製造工程を示す断面図と平面図。 Sectional and plan views showing the manufacturing process of the NAND cell unit according to an embodiment of the present invention; FIG.

【図3】図2(b)の矢視A−A′断面図。 [Figure 3] arrow A-A 'sectional view of FIG. 2 (b).

【図4】本発明の一実施例に係わるNANDセル部の製造工程を示す断面図と平面図。 Sectional and plan views showing the manufacturing process of the NAND cell unit according to an embodiment of the present invention; FIG.

【図5】本発明の一実施例に係わるNANDセル部の製造工程を示す断面図と平面図。 Sectional and plan views showing the manufacturing process of the NAND cell unit according to an embodiment of the present invention; FIG.

【図6】本発明の他の実施例に係わるNANDセル部の製造工程を示す断面図。 Cross-sectional view showing the manufacturing process of the NAND cell unit according to another embodiment of the present invention; FIG.

【図7】本発明の他の実施例によるNANDセル部の製造工程を示す断面図 Cross-sectional view showing the manufacturing process of the NAND cell unit according to another embodiment of the present invention; FIG

【図8】EEPROMの1つのNANDセル構成を示す平面図。 Figure 8 is a plan view showing one NAND cell structure of EEPROM.

【図9】図8の矢視A−A′及びB−B′断面図。 [9] arrow A-A 'and B-B' sectional view of FIG.

【符号の説明】 DESCRIPTION OF SYMBOLS

11…シリコン基板 12…第2ゲート絶縁膜 13…第1層多結晶シリコン膜(浮遊ゲート) 14…第2ゲート絶縁膜 15…第2層多結晶シリコン膜(制御ゲート) 16…CVDシリコン酸化膜(第1のマスク材料膜) 17,21,23…フォトレジスト 18…素子領域 19…CVDシリコン窒化膜(第2のマスク材料膜) 22…素子分離酸化膜 24…レジストの開口部 25…コンタクト領域 31…マスク材 11 ... silicon substrate 12: second gate insulating film 13 ... first layer polycrystalline silicon film (floating gate) 14 ... second gate insulating film 15 ... second layer polycrystalline silicon film (control gate) 16 ... CVD silicon oxide film (first mask material film) 17,21,23 ... photoresist 18 ... device region 19 ... CVD silicon nitride film (second mask material film) 22 ... device isolation oxide film 24 ... resist openings 25 ... contact region 31 ... mask material

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl. 6識別記号 庁内整理番号 FI 技術表示箇所 H01L 27/115 ────────────────────────────────────────────────── ─── front page continued (51) Int.Cl. 6 in identification symbol Agency Docket No. FI art display portion H01L 27/115

Claims (2)

    【特許請求の範囲】 [The claims]
  1. 【請求項1】半導体基板上に複数本の平行なストライプ状の導電膜パターンを有する半導体装置の製造方法において、 半導体基板上に導電膜を形成する工程と、前記導電膜上に第1のマスク材料膜を形成する工程と、第1のマスク材料膜をストライプ状にパターン加工する工程と、前記導電膜及び第1のマスク材料膜上にこれらとは異なる第2のマスク材料膜を形成する工程と、第2のマスク材料膜を全面エッチングしてストライプ状パターンの側壁部のみに第2のマスク材料膜を残す工程と、第1のマスク材料膜を除去する工程と、第2のマスク材料膜をマスクに前記導電膜を選択エッチングする工程とを含むことを特徴とする半導体装置の製造方法。 1. A method of manufacturing a semiconductor device having a parallel stripe-like conductive film pattern plural on a semiconductor substrate, forming a conductive film on a semiconductor substrate, a first mask on the conductive layer forming a step of forming a material film, a step of patterning the first mask material film in stripes, the second mask material layer differ from these in the conductive film and the first mask material film When a step of leaving the second mask material film only on the sidewalls of the striped pattern by entirely etching the second mask material film, and removing the first mask material film, the second mask material film the method of manufacturing a semiconductor device, wherein a and a step of selective etching of the conductive film as a mask.
  2. 【請求項2】半導体基板上に浮遊ゲートと制御ゲートを積層した不揮発性メモリセルを複数個直列接続してNA Wherein the nonvolatile memory cell formed by laminating a floating gate and a control gate on a semiconductor substrate with each other in series connection NA
    NDセルを構成し、NANDセルを複数個配列して構成される半導体装置の製造方法において、 半導体基板上に第1のゲート絶縁膜を介して浮遊ゲートとなる第1層多結晶シリコン膜を形成する工程と、第1 Configure ND cell, method of manufacturing the NAND cell semiconductor device configured by arranging a plurality, forming a first-layer polycrystalline silicon film serving as a floating gate via a first gate insulating film on a semiconductor substrate a step of, first
    層多結晶シリコン膜をワード線方向に隣接する素子間で分離するように加工する工程と、次いで基板全面に第2 A step of processing the layer polycrystalline silicon film so as to separate between elements adjacent in the word line direction, then the second on the entire surface of the substrate
    のゲート絶縁膜を介して制御ゲートとなる第2層多結晶シリコン膜を形成する工程と、第2層多結晶シリコン膜上に第1のマスク材料膜を形成しこの第1のマスク材料膜をストライプ状にパターン加工する工程と、次いで基板全面に第2層多結晶シリコン膜及び第1のマスク材料膜とは異なる材質の第2のマスク材料膜を形成する工程と、第2のマスク材料膜を全面エッチングしてストライプ状パターンの側壁部のみに第2のマスク材料膜を残す工程と、次いで第1のマスク材料膜を除去する工程と、 Of forming a second-layer polycrystalline silicon film serving as a control gate via a gate insulating film, the first mask material film is formed first mask material film on the second layer polycrystalline silicon film a step of patterning in stripes, then forming a second mask material film different in material from the second layer polycrystalline silicon film and the first mask material film on the entire surface of the substrate, the second mask material film removing a step of leaving the second mask material film only on the sidewalls of the striped pattern by etching the entire surface, then the first mask material film,
    次いで第2のマスク材料膜をマスクとして第2多結晶シリコン膜,第2ゲート絶縁膜,第1多結晶シリコン膜を順次エッチングする工程とを含むことを特徴とする半導体装置の製造方法。 Then the second polycrystalline silicon film and the second mask material layer as a mask, the second gate insulating film, a method of manufacturing a semiconductor device which comprises the step of sequentially etching the first polysilicon film.
JP6191534A 1994-08-15 1994-08-15 Manufacture of semiconductor device Pending JPH0855920A (en)

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