JPH0846213A - Article containing a plurality of gate field-effect transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a product containing a plurality of gate polysilicon thin- film transistors for reducing leakage current even if a relatively large reverse- gate bias is applied. SOLUTION: A plurality of gate polysilicon thin-film transistors 10 have three gates 12A, 12B, and 12C, which are located on gate channel regions 14A, 14B, and 14C, respectively. The channel regions are divided by a lightly-doped channel section 16. The transistor 10 is lightly doped, where sections 16A and 16B are 5×10<15> -2×10<19> (an injection dopant per cm<3> ). By reducing doping as compared with that by a conventional technique in a channel section among the gate channel regions, leakage current that greatly affects the ON current of a device can be decreased.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to multiple gate transistors.

[0002]

2. Description of the Related Art Polysilicon thin film transistors (Poly-Si TFTs)
Are useful members of the general class of thin film transistors (TFTs). Polysilicon TFTs have been extensively studied because of their importance in applications such as active matrix displays, page wide scanning bars, and load transistors of static random access memory (SRAM). In many applications, such as pixel switches in active matrix displays, the leakage current must be very low. However, polysilicon TFTs tend to have higher leakage currents than single crystal TFTs.

One known technique for reducing leakage current is to use thin film transistors (LDD TFTs) with lightly doped drains. L
In DD thin film transistors, the channel region between the N ⁺ doped contact and the channel section modulated by the gate is lightly doped. The channel region between the N ⁺ doped contact and the channel section covered by the gate is lightly doped. This light doping reduces the electric field around the N ⁺ region and thereby the leakage current. However, doping a channel in a polysilicon LDD thin film transistor is rather difficult to control because the degree of activation of doping varies from sample to sample due to the presence of traps in the polysilicon layer. In addition, the length of the lightly doped region has a detrimental effect on the on and off currents. Controlling its length requires expensive photomasking processes and expensive sidewall spacer technology.

Another known technique for reducing leakage current is to use multiple gate structures. Multiple gate structures are described, for example, in Huang US Pat. No. 4,90.
7,041, U.S. Pat. No. 5,25 to Izawa.
0,835 and Oshima et al., U.S. Pat. No. 4,623,908. 1 in FIG.
Figure 2 shows a schematic diagram of a prior art prototype multi-gate polysilicon TFT 10 with three gates 2A, 12B and 12C, said three gates overlying the corresponding channel regions 14A, 14B and 14C. The gated channel regions 14A-14C are separated by channel sections 16A and 16B, and in the prior art sections 16A and 16B are heavy doped (N ⁺ doped with more than 10 ¹⁹ implanted dopants per cm ³ ). Multi-gate polysilicon TFTs have advantages over LDD thin film transistors in that the on and off currents in multi-gate structures are not affected by critical device dimensions.

Multiple gate polysilicon TFTs have less leakage current than single gate polysilicon TFTs, but the slope of the leakage current versus reverse gate bias voltage curve is not reduced. This is contrary to the original expectation that multi-gate TFTs have a reduced leakage current / V _gs slope. The initial expectation is that the drain bias (V _ds ) will be split between gated regions and that minority carriers generated in the drain high field region will recombine in the heavily doped region without reaching the source. Was based on that. Reducing the slope of the reverse gate bias leakage current characteristic is important in determining the range of gate voltages that can be applied to multiple nominally identical transistors and keeping the leakage current below a specified value. Is.

However, studies of double-gate devices have shown that when V _gs is more negative than V _gsmin (the gate bias at which the device current is minimum), the region of highest electric field is the drain edge of the gated region closest to the source. Was shown to move to. When the gated region closest to the drain becomes sufficiently conductive, the maximum potential drop in the thin film transistor occurs at the drain end of the source gated region. Minority carriers generated by tunneling in the first gated region flow to the source, increasing leakage current. As a result, the double gate thin film transistor has the same slope / reverse gate bias characteristics as the single gate thin film transistor. As the number of gates in a thin film transistor grows, the point of highest channel field always moves to the drain edge of the gated region closest to the source, thus having the same leakage current slope as a single gate device. .

In some applications, prior art multi-gate thin film transistors operated with relatively large reverse gate bias (V _gs ) produce excessively high leakage currents. Therefore, a multiple gate thin film transistor that reduces leakage current even when a relatively large reverse gate bias is applied is desirable.

[0008]

SUMMARY OF THE INVENTION The principle of the present invention is to provide a multi-gate thin film transistor that reduces leakage current even when a high reverse gate bias is applied. This is achieved by reducing the doping (compared to corresponding prior art devices) in the channel section (s) between the gated channel regions. Reducing the doping reduces the peak electric field in the device, which reduces the device leakage current.

An aspect of claim 1 of the present invention is an article comprising a multi-gate field effect transistor; the multi-gate field effect transistor comprising: a substrate; two doped source / drain regions and the source. A channel having a series of at least two gated regions between the drain / drain regions, each of the adjacent pairs of the series of gated regions separated by a doped section, and the doping in the doped section. Is at least one of the source / drain regions
Including at least two gates, each gate being an adjacent one of the gated regions; and including a gate bias circuit connected to the gate of a transistor, the gate bias circuit comprising: Connect the gates together so that they are all at the same voltage,
The gate bias circuit also operates to bias the gate with a reverse gate bias voltage, the reverse gate bias voltage having a polarity opposite to that of the "on" gate bias in which the channel conducts the drive current, and the source bias. "Off" where the minimum current flows through the channel between the drain and drain regions
Greater than the gate bias; leakage caused when the doping in the doped section is sufficiently smaller than the doping in the source / drain regions so that the doping in the doped section equals the doping in the source / drain regions The leakage current density between the source / drain regions of the reverse gate bias voltage is greatly reduced as compared with the current density.

A second aspect of the present invention is the above-mentioned first aspect.
In the above aspect, the transistor is a thin film transistor.

A third aspect of the present invention is the above-mentioned second aspect.
In the above aspect, the transistor is a polysilicon thin film transistor.

[0012]

The present invention achieves the advantages of LDD thin film transistors and multi-gate thin film transistors, while significantly reducing their respective disadvantages.
One embodiment of the present invention is the multi-gate polysilicon thin film transistor 10 shown in FIG. As previously indicated, transistor 10 has three gates, 12A,
12B and 12C, which overlie gated channel regions 14A, 14B, and 14C, respectively. Those channel regions are channel section 1
6 [heavy doping (N ⁺ ) in the prior art]. Electrical input to the channel regions and sections is provided by N ⁺ contacts 18A and 18B and Al contacts 20A and 20B. Separating the gate from the channel is a thin layer of SiO ₂ . Above the gate and SiO ₂ layer and surrounding the Al contact is a layer of low temperature oxide (LTO). All of the above items are beneficially manufactured on a quartz or glass substrate 22.

The transistor 10 shown schematically is a
Actions 16A and 16B are 5 × 10^Fifteen~ 2 x 10
¹⁹(1 cm³(Implanted dopant per hit)
This is different from the conventional transistor. The present invention
Another example of the doping range within 1 cm is 1 cm³This
10¹⁶-10¹⁹Dopant of 1 cm³Per 10¹⁷~ 1
0 ¹⁹Dopant, and 1 cm³Per 10¹⁸-10¹⁹of
Dopants and the like are included. This allows the device
Current leakage is reduced without significant impact on
Is done. However, if the doping is too low (eg
About 2 x 10¹⁷Smaller than) is critical to the "on" current
It will be adversely affected. Device performance depends on doping level
Reliance on the subject is the subject of future experiments
Should pay attention to.

The advantages of the present invention over prior art multi-gate TFTs are readily apparent from FIG. In particular, FIG. 2 shows the results of a numerical simulation of a graph of current density versus gate bias voltage for two typical devices. Curve 100 is the T doped according to the present invention.
FT (5 × 10 ¹⁷ dopants per cm ³ ) is shown and curve 102 is a TFT (1 cm ³ ) doped according to the prior art.
2 × 10 ¹⁹ dopants per ³ ). It will be readily seen that the leakage current density of prior art devices is significantly higher than that of devices doped according to the present invention. It should be noted that the drive current of the transistor of the present invention is substantially the same as the drive current of prior art devices.

From the foregoing, many modifications and variations of the principles of the present invention will be apparent to those skilled in the art. In particular, although the present application describes a polysilicon TFT, the present invention is also applicable to a wide variety of insulated gate field effect transistors, such as SOI [silicon on insulator (silicon on insulator)], SOQ (silicon-on-quartz),
And SOS (silicon on sapphire), and bulk single crystal MOS field effect transistors, but are not limited thereto.

[0016]

According to the present invention, a relatively large reverse gate bias is achieved by reducing the doping (compared to corresponding prior art devices) in the channel section (s) between the gated channel regions. A multi-gate thin film transistor that reduces leakage current when applied is provided, and leakage current of the device can be reduced.

[Brief description of drawings]

FIG. 1 illustrates one embodiment of a multi-gate thin film transistor suitable for carrying out the principles of the present invention.

FIG. 2 shows a power-voltage curve for a thin film transistor of the present invention and a power-voltage curve for a thin film transistor according to the prior art.

[Explanation of symbols]

10 multi-gate polysilicon thin film transistor 12A, 12B, 12C gate 14A, 14B, 14C gated channel region 16A, 16B channel section 18A, 18B N ⁺ contact 22 substrate

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor E-Weu California 94024 Los Altos Miguel Avenue 1201

Claims (3)

[Claims] 1. An article comprising a multi-gate field effect transistor, wherein the multi-gate field effect transistor comprises a substrate; two doped source / drain regions and a series of source / drain regions between the doped source / drain regions. A channel having at least two gated regions; each of the adjacent pairs of the series of gated regions is separated by a doped section, the doping in the doped section of the source / drain regions being Lower than the doping in at least one of the gates, including at least two gates; each gate being an adjacent one of the gated regions, including a gate bias circuit connected to the gate of a transistor; The bias circuit puts the gates together so that they are all at the same voltage. And the gate bias circuit operates to bias the gate with a reverse gate bias voltage, the reverse gate bias voltage having a polarity opposite to the "on" gate bias through which the channel conducts drive current. And is greater than the “off” gate bias with minimal current flowing through the channel between the source / drain regions, and the doping in the doped section is significantly less than the doping in the source / drain regions, A plurality of leakage current densities between the source / drain regions of the reverse gate bias voltage are significantly reduced as compared to the leakage current densities occurring when the doping in the doped section is equal to the doping in the source / drain regions. Gate field effect transistor Products containing. 2. The article of claim 1, wherein the transistor is a thin film transistor. 3. The article of claim 2, wherein the transistor is a polysilicon thin film transistor.