JPH0845950A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent a polycrystalline silicon located under the shoulder of a side wall from being exposed by a method wherein an opening is provided to a base emitter forming region taking advantage of a specific side wall. CONSTITUTION:An oxidation-resistant film 209 is formed on side walls 207a and 207b thick enough to fill up a recess 208, and side walls 209a and 209b and buried films 209c and 209d filled into the recess 208 are formed of the oxidation-resistant film 209. Then, a first oxide film 202 is selectively removed from a base emitter forming region 210 taking advantage of a base emitter region forming window 205, the side walls 209a and 209b formed on the side wall, and the buried films 209c and 209d to provide an opening to the base emitter forming region 210. Then, a third semiconductor layer 211 is formed in the base emitter forming region 210, and a fourth region 213 is formed in a region which extends to the third semiconductor layer 211.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor integrated circuit device.

[0002]

2. Description of the Related Art Conventionally, as prior arts in such a field, there have been the followings, for example. 3A to 3D are cross-sectional views of manufacturing steps of a conventional semiconductor integrated circuit device. (1) First, as shown in FIG.
After forming an element isolation oxide film on No. 1, about 1500Å on the entire surface
The thermal oxide film 102 is formed, then the polycrystalline silicon film 103 of about 3000 Å is formed, and then the surface is thermally oxidized (not shown) to form the silicon nitride film 104.

(2) Next, as shown in FIG. 3B, the silicon nitride film 104 and the polycrystalline silicon film 103 are removed by using a known photolithography / etching technique to form a base-emitter formation region window 105. Form. (3) Next, as shown in FIG. 3C, a nitride film 106 of about 1500Å is formed on the entire surface, and sidewalls 106a and 106b are formed by dry anisotropic etching. After that, for example, the thermal oxide film 102 is selectively removed using the buffer emitter hydrofluoric acid having an etching rate of about 500 Å / min to form the base emitter forming region window 105 and the side walls 106a and 106b. A region 107 is formed.

(4) Next, as shown in FIG.
On the base-emitter formation region 107, for example, 800
Silicon is selectively grown using SiH ₂ Cl ₂ and H ₂ gas at 20 ° C. and 20 Torr. At this time, single crystal silicon grows from the semiconductor substrate 101, and polycrystalline silicon grows from the polycrystalline silicon film 103, and both are continuously connected. At this time, during vapor phase growth, for example,
By mixing an appropriate amount of B ₂ H ₆ (diborane),
Boron is mixed in at a high concentration of about 10 ¹⁸ to 10 ¹⁹ / cm ³ during the film formation, and the base region 108 of the P ⁺ type epitaxial film is grown to about 750 Å to 1000 Å.

[0005]

However, the above-described conventional method for manufacturing a semiconductor integrated circuit device has the following problems. When the base region 108 is formed by selective epitaxial growth, the sidewall 106 of the nitride film that prevents abnormal growth of polycrystalline silicon in the lateral direction is formed.
Since a and 106b are composite films of two-stage nitride film and are formed by time control, their shapes are unstable,
At the shoulders of the sidewalls 106a and 106b, there was a possibility that the underlying polycrystalline silicon would be exposed.

When the base region 108 is formed by the epitaxial film, the epitaxial film is formed in a portion where the lower polycrystalline silicon is exposed. When forming the emitter, the emitter polycrystalline silicon and the base region by the epitaxial film are short-circuited. I was afraid to do it. In order to eliminate the above-mentioned problems, the present invention does not expose the underlying polycrystalline silicon at the shoulder portion of the sidewall, and at the time of forming the emitter, the base region formed by the emitter polycrystalline silicon and the epitaxial film is formed. It is an object of the present invention to provide a method for manufacturing a semiconductor device in which no short circuit occurs.

[0007]

In order to achieve the above object, the present invention provides (1) a method of manufacturing a semiconductor element, comprising a semiconductor substrate (2
01) a step of forming a first conductivity type island region surrounded by an isolation oxide film on one main surface, and a first oxide film (202) is formed on the entire surface of the substrate including the first conductivity type island region. Forming a first semiconductor layer (203) thereon, and further forming a first oxidation resistant film (204) thereon, and the first oxidation resistant film (204) and the first oxidation resistant film (204). Forming a window (205) on the semiconductor layer (203) for opening a base-emitter formation region, and the base-emitter region formation window (20)
The second semiconductor layer (206) and the second anti-oxidation film (207) are formed on the side wall of (5) to form the side walls (207a, 207a).
b) and forming a recess (208), and forming a third oxidation resistant film (209) on the sidewalls (207a, 207b) to the extent that the recess (208) is embedded, The oxidation resistant film (209) of the side walls (209a, 209b) and the recess (208).
To form the buried films (209c, 209d), the base-emitter region forming window (205), and sidewalls (209a, 209) formed on the side walls thereof.
b) and the buried film (209c,
209d), the base-emitter formation region (21
0) to selectively remove the first oxide film (202) to open the base-emitter formation region (210), and to form a third semiconductor layer (211) in the base-emitter formation region (210). And the third semiconductor layer (2
11) and a step of forming a fourth semiconductor layer (213) in the region extending to 11).

Further, a step of forming a first conductivity type island region surrounded by an isolation oxide film on one main surface of the semiconductor substrate (301), and a step of forming a first conductivity type island region on the entire surface of the substrate including the first conductivity type island region. 1 oxide film (302) is formed, a first semiconductor layer (303) is formed thereon, and a first oxidation resistant film (30) is formed thereon.
4), and the first oxidation resistant film (304)
And forming a window on the first semiconductor layer (303) for opening a base-emitter formation region, and a second semiconductor layer (306) on a side wall of the base-emitter region formation window.
And the second oxidation resistant film (307) allows the sidewall (3
07a, 307b) to form a recess (308), and exposing the exposed portions (306a, 306b, 306c, 306d) of the second semiconductor layer (306) to a third oxidation resistant film (309a, 309b). , 309c, 309d)
And a step of converting the third oxidation resistant film (309a, 3a).
09b, 309c, 309d) and the base-emitter forming region (310) are used to form the base-emitter forming region (3
10) a step of selectively removing the first oxide film (302), and in the base-emitter formation region (310), a base-emitter formation region window and sidewalls (307a, 307b) formed on the side walls thereof, and Third oxidation resistant film (3
09a, 309b, 309c, 309d),
Forming a third semiconductor layer (311) in the base-emitter formation region (310), and forming a second oxide film (312) on the third semiconductor layer (311), By the oxide film (312), the side wall (312
a, 312b) and a step of forming a buried film (312c, 312d) in the recess (308), and a fourth semiconductor layer (315) is formed in a region extending to the third semiconductor layer (311). The process is applied.

[0009]

According to the present invention, as described above, (1) the step of forming the sidewalls (209a, 209b) and the buried films (209c, 209d) of the recess (208), and the base-emitter region forming window (20
5) and the side wall (209) formed on the side wall thereof.
a, 209b) and the buried films (209c, 209d) in the recesses (208), the first oxide film (202) in the base-emitter formation region (210) is selectively removed to form a base-emitter formation region. A step of opening (210), and a third step in the base-emitter formation region (210).
Forming the semiconductor layer (210) of the second semiconductor layer (210), and forming a fourth semiconductor layer (2) in the region extending to the third semiconductor layer (211).
13) is performed.

(2) A second layer is formed on the third semiconductor layer (311).
Oxide film (312) of the second oxide film (31
2) by the side walls (312a, 312b) and the buried films (312c, 312) in the depressions (308).
d) forming the third semiconductor layer (311)
Since the step of forming the fourth semiconductor layer (315) is performed in the region extending to the side, the polycrystalline silicon under the side wall is not exposed at the shoulder portion of the sidewall, and the emitter formation is not performed. At this time, it is possible to prevent a short circuit between the emitter polycrystalline silicon and the base region due to the epitaxial film.

[0011]

Embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a sectional view of a manufacturing process of a semiconductor integrated circuit device showing the first embodiment of the present invention (Part 1), FIG.
Is a sectional view of the manufacturing process of the semiconductor integrated circuit device (No. 2)
Is. (1) First, as shown in FIG. 1A, after forming an element isolation oxide film on the semiconductor substrate 201, as in the conventional example,
A thermal oxide film 202 of about 1500Å is formed on the entire surface, and then a polycrystalline silicon film 203 of about 3000Å is formed,
After that, a silicon nitride film 204 of about 2000 Å is formed, and subsequently, the silicon nitride film 204 and the polycrystalline silicon film 203 are removed by using a known photolithography / etching technique to form a base-emitter region forming window 205.

(2) Next, as shown in FIG. 1B, a polycrystalline silicon film 206 and a silicon nitride film 207 are formed by, for example, the CVD method. (3) Then, as shown in FIG. 1C, the silicon nitride film 207 and the polycrystalline silicon film 206 are removed by anisotropic etching to form sidewalls 207a and 207b.
To form. At this time, the polycrystal silicon film 206 is over-etched to form a recess 208.

(4) Then, as shown in FIG.
For example, the silicon nitride film 209 is formed by the CVD method. At this time, the recess 208 when the polycrystalline silicon film 206 is etched is completely filled. (5) Subsequently, as shown in FIG. 2B, the silicon nitride film 209 is etched by a known anisotropic etching technique to form the sidewalls 209a and 209b and the recess 20.
8 filling films 209c and 209d are formed. After that, buffer base hydrofluoric acid is used to form the base-emitter region forming window 2
The thermal oxide film 202 around 05 is removed, and the base-emitter formation region 210 is opened. For example, when etching is performed for about 4 minutes using buffer hydrofluoric acid having an etching rate of about 500 Å / min, the base-emitter formation region 21
The width of 0 is about 1 μm.

(6) Then, as shown in FIG.
In the base emitter region forming window 205, for example, 800
SiH ₂ Cl ₂ , H _{2 in} an atmosphere of 20 ° C. and 20 Torr
A gas is used to selectively grow silicon. At this time, single crystal silicon grows on the semiconductor substrate 201, and polycrystalline silicon grows from the polycrystalline silicon film 203, and both are continuously connected. At this time, during vapor deposition, for example, by mixing an appropriate amount of B ₂ H ₆ (diborane), boron is added at 10 ¹⁸ to 10 ¹⁹ / cm ³ during film formation.
The base region 211 made of a P ⁺ -type epitaxial film is grown to a high concentration of about 750 Å to 1000 Å.

(7) After that, as shown in FIG.
A polycrystalline silicon film 212 is grown and then, for example,
Arsenic (As) 50 keV, 2 × 10 ¹⁶ ions / cm
Ion implantation is performed under the condition of ² by using a known ion implantation technique, and then heat treatment is performed at 900 ° C. for 20 minutes, for example, to form the emitter region 213. FIG. 4 is a manufacturing process sectional view (No. 1) of a semiconductor integrated circuit device showing a second embodiment of the present invention, and FIG. 5 is a manufacturing process sectional view (No. 2) of the semiconductor integrated circuit device.

(1) First, FIG. 1 of the first embodiment described above.
Similar to the steps (A) to (C), as shown in FIG. 4A, after forming an element isolation oxide film on the semiconductor substrate 301, a thermal oxide film 302 of about 1500 Å is formed on the entire surface. After that, a polycrystalline silicon film 303 of about 3000 Å is formed, then a silicon nitride film 304 of about 2000 Å is formed, and subsequently, a silicon nitride film 304 and a polycrystalline silicon film 303 are formed by using a known photolithography / etching technique. Are removed to form a base emitter region forming window. Next, the polycrystalline silicon film 306 and the silicon nitride film 307
Are generated by, for example, the CVD method. Next, the silicon nitride film 307 and the polycrystalline silicon film 306 are removed by anisotropic etching to remove the sidewalls 307a, 3
07b is formed. At this time, the depression 308 is generated by over-etching the polycrystalline silicon film 306. Here, 306a and 306b are exposed portions of the polycrystalline silicon film 306 in the depression 308, and 306c and 3
06d is an exposed portion of the lower side surface of the polycrystalline silicon film 306.

(2) Next, as shown in FIG. 4B, the exposed portion of the polycrystalline silicon film 306 in the depression 308 is subjected to heat treatment at 1100 ° C. for 30 seconds in an N ₂ O atmosphere, for example. 306a and 306b are formed of polycrystalline silicon 30 on the silicon nitride films 309a and 309b.
The exposed portions 306c and 306d of the lower side surface of 6 are converted into silicon nitride films 309c and 309d.

(3) After that, as shown in FIG.
The thermal oxide film 302 is selectively removed using buffered hydrofluoric acid to open the base-emitter formation region 310. (4) Subsequently, as shown in FIG. 5A, an epitaxial film 311 is formed only in the base-emitter formation region 310 by using the same method as the conventional technique, and then, the CVD film is formed.
The oxide film 312 is formed using the method. At this time, the depression 30
8 is filled with the oxide film 312.

(5) Next, as shown in FIG. 5B, the oxide film 312 is etched using a known anisotropic etching technique to remove the oxide film 312 from the sidewalls 312a and 312b and the recess 308. Embedded film 31
2c and 312d are formed. Then, in the base emitter region formation window, for example, SiH ₂ Cl ₂ and H ₂ gas are used to selectively grow silicon in an atmosphere of 800 ° C. and 20 Torr. At this time, single crystal silicon grows on the semiconductor substrate 301, and the polycrystalline silicon film 306 is formed.
From that, polycrystalline silicon grows, and both are continuously connected. At this time, during vapor phase growth, for example, an appropriate amount of B ₂ H
By mixing ₆ (diborane), boron is mixed at a high concentration of about 10 ¹⁸ to 10 ¹⁹ / cm ³ during film formation,
A base region 313 made of a P ⁺ type epitaxial film is formed,
Grow about 750Å to 1000Å.

(6) Next, as shown in FIG. 5C, a polycrystalline silicon film 314 is formed. And, for example, A
s (arsenic) 50 keV, 2 × 10 ¹⁶ ions / cm ²
Under the conditions described above, ion implantation is performed using a known ion implantation technique. Then, the emitter region 315 is formed by applying a heat treatment at 900 ° C. for 20 minutes, for example.
The present invention is not limited to the above embodiment,
Various modifications are possible based on the spirit of the present invention, and these are not excluded from the scope of the present invention.

[0021]

As described in detail above, according to the present invention, the following effects can be obtained. (1) According to the first aspect of the invention, after the base-emitter region forming window is opened, when a sidewall is formed on the side wall of the opening by the polycrystalline silicon film and the silicon nitride film, the silicon nitride film is formed. The sidewalls are stably formed using polycrystalline silicon as a stopper and the polycrystalline silicon using a nitride film as a stopper.

Further, by molding the sidewalls of polycrystalline silicon, it is possible to secure a margin of the connection surface with respect to the base contact. Furthermore, when the same base contact as in the conventional technique is required, the base growth region can be narrowed, and the collector-base junction capacitance C _TC , which is one factor that hinders the speedup of the transistor, can be reduced. Becomes

(2) According to the second aspect of the invention, only one step is required to generate a nitride film serving as a mask for polycrystalline silicon by thermal nitriding when the selective epitaxial film is grown. The process is further simplified as compared with the first embodiment. In addition, the thickness of the insulating film between the emitter and the base must be set to an optimum value for diffusion during the formation of the emitter, and the oxide film thickness can be made thicker than that in the first embodiment. It is possible to reduce the junction capacitance _CTE of the.

[Brief description of drawings]

FIG. 1 is a manufacturing process sectional view (1) of a semiconductor integrated circuit device showing a first embodiment of the present invention.

FIG. 2 is a manufacturing process sectional view (2) of the semiconductor integrated circuit device showing the first embodiment of the present invention;

FIG. 3 is a sectional view of a manufacturing process of a conventional semiconductor integrated circuit device.

FIG. 4 is a manufacturing process sectional view (1) of a semiconductor integrated circuit device showing a second embodiment of the present invention.

FIG. 5 is a manufacturing process sectional view (No. 2) of the semiconductor integrated circuit device showing the second embodiment of the present invention;

[Explanation of symbols]

201, 301 Semiconductor substrate 202, 302 Thermal oxide film 203, 206, 212, 303, 306, 314
Polycrystalline silicon film 204, 207, 209, 304, 307, 309a,
309b, 309c, 309d Silicon nitride film 205 Base emitter region forming windows 207a, 207b, 209a, 209b, 307a,
307b, 312a, 312b Side wall 208, 308 Depression 209c, 209d, 312c, 312d Buried film 210, 310 Base emitter formation region 211, 313 Base region 213, 315 Emitter region 306a, 306b Exposed portion of polycrystalline silicon film in depression 306c, 306d Exposed part of lower side surface of polycrystalline silicon film 311 Epitaxial film 312 Oxide film

Claims (2)

[Claims] 1. A step of: (a) forming a first conductivity type island region surrounded by an isolation oxide film on one main surface of a semiconductor substrate;
(B) A step of forming a first oxide film on the entire surface of the substrate including the first conductivity type island region, forming a first semiconductor layer thereon, and further forming a first oxidation resistant film thereon. And (c) a step of forming a window for opening a base-emitter formation region on the first oxidation resistant film and the first semiconductor layer, and (d) a second side wall of the base-emitter region formation window. Forming a side wall with the semiconductor layer and the second oxidation resistant film, and (e) forming a third oxidation resistant film on the side wall to such an extent that the recess is buried, A step of forming a sidewall and a buried film of the recess with the oxidation resistant film of (5), (f) utilizing the base emitter region forming window and the sidewall and the recess buried film formed on the side wall thereof, First oxide film in base emitter formation region A step of selectively removing and opening a base emitter forming region; (g) forming a third semiconductor layer in the base emitter forming region; and (h) a region extending to the third semiconductor layer. And a step of forming a fourth semiconductor layer are performed. 2. A step of: (a) forming a first conductivity type island region surrounded by an isolation oxide film on one main surface of a semiconductor substrate;
(B) A step of forming a first oxide film on the entire surface of the substrate including the first conductivity type island region, forming a first semiconductor layer thereon, and further forming a first oxidation resistant film thereon. And (c) a step of forming a window for opening a base-emitter formation region on the first oxidation resistant film and the first semiconductor layer, and (d) a second side wall of the base-emitter region formation window. Forming a side wall with the semiconductor layer and the second oxidation resistant film to form a recess, and (e) converting the exposed portion of the second semiconductor layer into a third oxidation resistant film. f) selectively removing the first oxide film in the base-emitter formation region using the third oxidation resistant film and the base-emitter formation region, and (g) forming a base emitter in the base-emitter formation region. Forming area window, sidewall formed on its side wall, and third acid resistance A step of forming a third semiconductor layer in the base-emitter formation region using a film, and (h) forming a second oxide film on the third semiconductor layer, and using the second oxide film. Manufacturing of a semiconductor device characterized by performing a step of forming a buried film of a sidewall and the recess and (i) a step of forming a fourth semiconductor layer in a region extending to the third semiconductor layer. Method.