JPH08330868A - Variable gain circuit - Google Patents

Variable gain circuit

Info

Publication number
JPH08330868A
JPH08330868A JP15695195A JP15695195A JPH08330868A JP H08330868 A JPH08330868 A JP H08330868A JP 15695195 A JP15695195 A JP 15695195A JP 15695195 A JP15695195 A JP 15695195A JP H08330868 A JPH08330868 A JP H08330868A
Authority
JP
Japan
Prior art keywords
circuit
gain
phase compensation
operational amplifier
variable gain
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15695195A
Other languages
Japanese (ja)
Inventor
Akihiro Ouchi
朗弘 大内
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP15695195A priority Critical patent/JPH08330868A/en
Publication of JPH08330868A publication Critical patent/JPH08330868A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To provide a variable gain circuit whereby a sufficient frequency band is obtained even when high gain is set. CONSTITUTION: The variable gain circuit is provided with an operational amplifier circuit 10, an internal phase compensating circuit 20, a phase compensation adjusting circuit 30 connected to the internal phase compensating circuit 20 in parallel, a gain setting circuit connected between the inverting input terminal 2 and the output terminal 3 of the operational amplifier circuit 10 and a gain setting control means 50 controlling the synchronization of the gain setting circuit 40 with the phase compensation adjusting circuit 30. The phase compensation adjusting circuit 30 is linked with high gain when the gain setting control means 50 set high gain so as to executes an operation for reducing phase compensation. When low gain is set, it is linked with low gain so as to executes the operation for enlarging phase compensation and executes the operation for obtaining the sufficient frequency and while holding the stable operation from low gain to the high one.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、周波数帯域を広くとれ
る可変利得回路に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a variable gain circuit capable of widening a frequency band.

【0002】[0002]

【従来の技術】図4は演算増幅回路を用いた従来の可変
利得回路の構成を示すブロック図である。図5は従来の
可変利得回路の構成を具体的に示す回路図である。
2. Description of the Related Art FIG. 4 is a block diagram showing a configuration of a conventional variable gain circuit using an operational amplifier circuit. FIG. 5 is a circuit diagram specifically showing the configuration of a conventional variable gain circuit.

【0003】従来の可変利得回路は演算増幅回路10
a、利得設定回路40aなどから構成されている。
A conventional variable gain circuit is an operational amplifier circuit 10.
a, a gain setting circuit 40a, and the like.

【0004】演算増幅回路10aでは、定電流源である
MOSFET15aのドレインに共通にソースが接続さ
れたMOSFET11a、12aは差動入力対を形成
し、MOSFET13a、14aは差動入力対の能動負
荷を形成する。MOSFET16aのゲートはMOSF
ET12a、14aのドレイン共通接続点に接続され、
ソースは接地端子101aに接続され、ドレインは定電
流源であるMOSFET17aのドレインと出力端子3
aに接続されている。
In the operational amplifier circuit 10a, MOSFETs 11a and 12a whose sources are commonly connected to the drain of the MOSFET 15a which is a constant current source form a differential input pair, and the MOSFETs 13a and 14a form an active load of the differential input pair. To do. The gate of the MOSFET 16a is MOSF
Connected to the common drain connection point of ET12a, 14a,
The source is connected to the ground terminal 101a, and the drain is the drain of the MOSFET 17a, which is a constant current source, and the output terminal 3.
connected to a.

【0005】ここで、1aは非反転入力端子、2aは反
転入力端子、61aは定電流設定用バイアス端子、22
aは位相補償容量、21aは電源端子100aにゲート
が接続されたゼロ点調整用のMOSFETである。演算
増幅回路10aは全体として2段構成のCMOS演算増
幅器を形成する。
Here, 1a is a non-inverting input terminal, 2a is an inverting input terminal, 61a is a constant current setting bias terminal, and 22 is a constant current setting bias terminal.
Reference numeral a is a phase compensation capacitance, and reference numeral 21a is a zero point adjusting MOSFET having a gate connected to the power supply terminal 100a. The operational amplifier circuit 10a forms a two-stage CMOS operational amplifier as a whole.

【0006】また、利得設定回路40aでは、45a〜
49aは利得設定用抵抗器、41a〜44aは抵抗接続
切換用スイッチ手段、50aは抵抗切換用スイッチ制御
手段である。
Further, in the gain setting circuit 40a, 45a ...
Reference numeral 49a is a gain setting resistor, 41a to 44a are resistance connection switching switch means, and 50a is a resistance switching switch control means.

【0007】このような構成を有する従来の可変利得回
路では、抵抗切換用スイッチ制御手段50aにより抵抗
接続切換用スイッチ41a〜44aを切り換えることに
よって演算増幅回路10aの利得を制御する。
In the conventional variable gain circuit having such a structure, the gain of the operational amplifier circuit 10a is controlled by switching the resistance connection switching switches 41a to 44a by the resistance switching switch control means 50a.

【0008】[0008]

【発明が解決しようとする課題】しかしながら、上記従
来の可変利得回路では、位相補償容量22aおよびMO
SFET21aからなる位相補償回路は可変利得回路の
利得が値1の場合に安定動作が得られるように設定され
るので、可変利得回路の利得が高利得に設定された場合
に十分な周波数帯域が得られないという問題があった。
However, in the above-mentioned conventional variable gain circuit, the phase compensating capacitors 22a and MO are provided.
Since the phase compensation circuit including the SFET 21a is set so that stable operation is obtained when the gain of the variable gain circuit is 1, a sufficient frequency band is obtained when the gain of the variable gain circuit is set to high gain. There was a problem that I could not.

【0009】本発明は高利得に設定された場合でも十分
な周波数帯域が得られる可変利得回路を提供することを
目的とする。
An object of the present invention is to provide a variable gain circuit which can obtain a sufficient frequency band even when it is set to a high gain.

【0010】[0010]

【課題を解決するための手段】上記目的を達成するため
に、本発明の請求項1に係る可変利得回路は、入力端子
を介して入力される信号の演算増幅を行う演算増幅回路
と、該演算増幅回路の反転入力端子と出力端子との間に
接続され、前記演算増幅の利得を設定する利得設定回路
と、前記演算増幅が行われる信号の位相補償を行う位相
補償回路とを備えた可変利得回路において、前記位相補
償回路と並列に接続され、前記設定された利得に応じて
前記位相補償を調整する位相補償調整回路と、該位相補
償の調整と前記利得の設定とを同期させる利得設定制御
手段とを備える。
To achieve the above object, a variable gain circuit according to claim 1 of the present invention comprises an operational amplifier circuit for performing operational amplification of a signal input through an input terminal, A variable variable amplifier including a gain setting circuit connected between the inverting input terminal and the output terminal of the operational amplifier circuit, for setting the gain of the operational amplifier, and a phase compensation circuit for compensating the phase of the signal subjected to the operational amplifier. In a gain circuit, a phase compensation adjustment circuit that is connected in parallel with the phase compensation circuit and adjusts the phase compensation according to the set gain, and a gain setting that synchronizes the adjustment of the phase compensation and the gain setting. And control means.

【0011】[0011]

【作用】本発明の請求項1に係る可変利得回路では、演
算増幅回路により入力端子を介して入力される信号の演
算増幅を行い、該演算増幅回路の反転入力端子と出力端
子との間に接続された利得設定回路により前記演算増幅
の利得を設定し、位相補償回路により前記演算増幅が行
われる信号の位相補償を行う際に、前記位相補償回路と
並列に接続された位相補償調整回路により前記設定され
た利得に応じて前記位相補償を調整し、利得設定制御手
段により該位相補償の調整と前記利得の設定とを同期さ
せる。
In the variable gain circuit according to claim 1 of the present invention, the operational amplifier circuit performs operational amplification of a signal input through the input terminal, and the signal is provided between the inverting input terminal and the output terminal of the operational amplifier circuit. When the gain of the operational amplification is set by the connected gain setting circuit and the phase compensation circuit performs the phase compensation of the signal for which the operational amplification is performed, the phase compensation adjustment circuit connected in parallel with the phase compensation circuit The phase compensation is adjusted according to the set gain, and the gain setting control means synchronizes the adjustment of the phase compensation with the setting of the gain.

【0012】[0012]

【実施例】図1は実施例の可変利得回路の構成を示すブ
ロック図である。図において、10は演算増幅回路、2
0は内部位相補償回路、30は内部位相補償回路20に
並列に接続される位相補償調整回路、40は演算増幅回
路10の反転入力端子2と出力端子3との間に接続され
る利得設定回路、50は利得設定回路40と位相補償調
整回路30とを同期して制御する利得設定制御手段であ
る。
1 is a block diagram showing the configuration of a variable gain circuit according to an embodiment. In the figure, 10 is an operational amplifier circuit, 2
Reference numeral 0 is an internal phase compensation circuit, 30 is a phase compensation adjustment circuit connected in parallel to the internal phase compensation circuit 20, and 40 is a gain setting circuit connected between the inverting input terminal 2 and the output terminal 3 of the operational amplifier circuit 10. , 50 are gain setting control means for synchronously controlling the gain setting circuit 40 and the phase compensation adjusting circuit 30.

【0013】上記構成において、位相補償調整回路30
は利得設定制御手段50により高利得に設定された場合
にはそれに連動して位相補償を小さくするよう動作し、
低利得に設定された場合にはそれに連動して位相補償を
大きくするよう動作して低利得から高利得まで安定動作
を保ちつつ、十分な周波数帯域が得られるよう動作す
る。
In the above configuration, the phase compensation adjustment circuit 30
Operates when the gain setting control means 50 is set to a high gain so as to reduce the phase compensation in conjunction with it.
When the gain is set to a low gain, the phase compensation works in conjunction with it to operate so that a sufficient frequency band can be obtained while maintaining stable operation from low gain to high gain.

【0014】図2は可変利得回路の構成を具体的に示す
回路図である。演算増幅回路10は、定電流源であるP
チャネルMOSFET15を介して電源端子100に接
続された共通のソースを有するPチャネルMOSFET
11、12からなる差動入力対と、PチャネルMOSF
ET11のドレインにドレインとゲートとが接続されソ
ースが接地端子101に接続されたNチャネルMOSF
ET13と、ゲートがNチャネルMOSFET13のゲ
ートと共通に接続され、ドレインがPチャネルMOSF
ET12のドレインと共通に接続され、ソースが接地端
子101に接続されたNチャネルMOSFET14と、
ゲートがPチャネルMOSFET12およびNチャネル
MOSFET14のドレイン共通接続点と接続され、ド
レインが定電流源であるPチャネルMOSFET17を
介して電源端子100に接続され、ソースが接地端子1
01に接続されたNチャネルMOSFET16とから構
成される。
FIG. 2 is a circuit diagram specifically showing the configuration of the variable gain circuit. The operational amplifier circuit 10 has a constant current source P
P-channel MOSFET having a common source connected to the power supply terminal 100 via the channel MOSFET 15.
A differential input pair consisting of 11, 12 and a P-channel MOSF
N-channel MOSF in which the drain and gate are connected to the drain of ET11 and the source is connected to the ground terminal 101
ET13 and the gate are commonly connected to the gate of the N-channel MOSFET 13, and the drain is a P-channel MOSF
An N-channel MOSFET 14 which is commonly connected to the drain of the ET 12 and whose source is connected to the ground terminal 101;
The gate is connected to the common drain connection point of the P-channel MOSFET 12 and the N-channel MOSFET 14, the drain is connected to the power supply terminal 100 via the P-channel MOSFET 17 which is a constant current source, and the source is the ground terminal 1.
And an N-channel MOSFET 16 connected to 01.

【0015】内部位相補償回路20は、ソースがPチャ
ネルMOSFET12およびNチャネルMOSFET1
4のドレイン共通接続点に接続され、ゲートが電源端子
100に接続され、ドレインが位相補償容量22の一方
の端子と接続されたNチャネルMOSFET21と、N
チャネルMOSFET21と接続されない他方の端子が
NチャネルMOSFET16のドレインに接続された位
相補償容量22とから構成される。
In the internal phase compensation circuit 20, the sources have P-channel MOSFET 12 and N-channel MOSFET 1.
An N-channel MOSFET 21 connected to the drain common connection point of No. 4, a gate connected to the power supply terminal 100, and a drain connected to one terminal of the phase compensation capacitance 22;
The other terminal not connected to the channel MOSFET 21 is composed of a phase compensation capacitor 22 connected to the drain of the N-channel MOSFET 16.

【0016】位相補償調整回路30は、一方の端子がN
チャネルMOSFET16のドレインに接続された位相
補償調整用容量35、36、37、38と、Nチャネル
MOSFET16のドレインと接続されない他方の端子
とドレインが接続され、ソースが共通にNチャネルMO
SFET16のゲートに接続され、ゲートが利得設定制
御手段50に接続されたNチャネルMOSFET31、
32、33、34とから構成される。
The phase compensation adjustment circuit 30 has one terminal of N terminal.
The phase compensation adjustment capacitors 35, 36, 37, 38 connected to the drain of the channel MOSFET 16 and the other terminal not connected to the drain of the N-channel MOSFET 16 are connected to the drain, and the sources are commonly connected to the N-channel MO.
An N-channel MOSFET 31, which is connected to the gate of the SFET 16 and whose gate is connected to the gain setting control means 50,
32, 33, 34.

【0017】利得設定回路40は、演算増幅回路10の
反転入力端子2と出力端子3との間に接続された帰還抵
抗器45と、利得設定制御手段50で開閉を制御される
スイッチ手段41、42、43、44と、該スイッチ手
段41、42、43、44により反転入力端子2に接続
され、他端を共通に基準電源端子62に接続された利得
設定用抵抗器41、42、43、44とから構成され
る。
The gain setting circuit 40 includes a feedback resistor 45 connected between the inverting input terminal 2 and the output terminal 3 of the operational amplifier circuit 10 and a switch means 41 whose opening and closing is controlled by the gain setting control means 50. 42, 43, 44, and gain setting resistors 41, 42, 43, which are connected to the inverting input terminal 2 by the switch means 41, 42, 43, 44 and whose other end is commonly connected to the reference power supply terminal 62. And 44.

【0018】上記具体的構成を有する利得設定回路40
の動作について説明する。設定された利得は、利得設定
制御手段50によって制御されるスイッチ手段41〜4
4が全てOFFのとき最低の値1となり、全てONのと
き最高の利得となる。
A gain setting circuit 40 having the above-mentioned specific configuration.
The operation of will be described. The set gains are switched by the gain setting control means 50.
When all 4 are OFF, the lowest value is 1, and when all are ON, the highest gain is obtained.

【0019】位相補償調整回路30のNチャネルMOS
FET31〜34は利得設定制御手段50によって制御
されるスイッチとなっており、利得設定回路40内のス
イッチ手段41〜44のON/OFFに連動してそれぞ
れOFF/ONとなる。
N-channel MOS of the phase compensation adjustment circuit 30
The FETs 31 to 34 are switches controlled by the gain setting control means 50, and are turned OFF / ON in conjunction with ON / OFF of the switch means 41 to 44 in the gain setting circuit 40.

【0020】即ち、スイッチ手段41〜44が全てON
で最高利得に設定された場合にはNチャネルMOSFE
T31〜34はOFFとなり、位相補償調整回路30は
演算増幅回路10から切り離される。一方、スイッチ手
段41〜44が全てOFFの最低利得の場合にはNチャ
ネルMOSFET31〜34はONになり、位相補償調
整回路30は演算増幅回路10に接続される。
That is, all the switch means 41 to 44 are turned on.
N channel MOSFE when the maximum gain is set by
T31 to 34 are turned off, and the phase compensation adjustment circuit 30 is separated from the operational amplifier circuit 10. On the other hand, when the switch means 41 to 44 are all OFF and the minimum gain, the N-channel MOSFETs 31 to 34 are turned ON and the phase compensation adjustment circuit 30 is connected to the operational amplifier circuit 10.

【0021】従って、内部位相補償回路20は最高利得
の場合において補償を行えばよく、位相補償容量22を
小さくできるので、周波数帯域が広く取れる。また、利
得設定抵抗器46〜49の重み付けに対応して位相補償
調整回路30を構成する位相補償容量35〜38に重み
付けをすれば、設定された各利得において十分広い周波
数帯域を得ることができる。 [変形例]図3は変形例の可変利得回路の構成を具体的
に示す回路図である。変形例の可変利得回路は、内部位
相補償回路20を構成するNチャネルMOSFET21
および位相補償調整回路30を構成するNチャネルMO
SFET31〜34をPチャネルMOSFETに入れ替
えて構成されている。このような入れ替えを行っても極
性が変わるだけで本質的な違いは生じない。
Therefore, the internal phase compensation circuit 20 only needs to perform compensation in the case of the highest gain, and the phase compensation capacitance 22 can be made small, so that a wide frequency band can be taken. Further, if the phase compensation capacitors 35 to 38 forming the phase compensation adjustment circuit 30 are weighted corresponding to the weighting of the gain setting resistors 46 to 49, a sufficiently wide frequency band can be obtained at each set gain. . [Modification] FIG. 3 is a circuit diagram specifically showing the configuration of a variable gain circuit of a modification. The variable gain circuit of the modified example includes an N-channel MOSFET 21 that constitutes the internal phase compensation circuit 20.
And an N-channel MO that constitutes the phase compensation adjustment circuit 30.
It is configured by replacing the SFETs 31 to 34 with P-channel MOSFETs. Even if such replacement is performed, the polarity is changed and no essential difference occurs.

【0022】[0022]

【発明の効果】本発明の請求項1に係る可変利得回路に
よれば、演算増幅回路により入力端子を介して入力され
る信号の演算増幅を行い、該演算増幅回路の反転入力端
子と出力端子との間に接続された利得設定回路により前
記演算増幅の利得を設定し、位相補償回路により前記演
算増幅が行われる信号の位相補償を行う際に、前記位相
補償回路と並列に接続された位相補償調整回路により前
記設定された利得に応じて前記位相補償を調整し、利得
設定制御手段により該位相補償の調整と前記利得の設定
とを同期させるので、高利得に設定された場合でも広い
周波数帯域を確保できる。
According to the variable gain circuit of the first aspect of the present invention, the operational amplifier circuit performs operational amplification of the signal input through the input terminal, and the inverting input terminal and the output terminal of the operational amplifier circuit. And a phase connected in parallel with the phase compensation circuit when the gain of the operational amplification is set by the gain setting circuit connected between the phase compensation circuit and the phase compensation circuit for phase compensation of the signal for which the operational amplification is performed. The compensation adjustment circuit adjusts the phase compensation according to the set gain, and the gain setting control means synchronizes the adjustment of the phase compensation with the setting of the gain. Therefore, even when the high gain is set, a wide frequency range is set. Bandwidth can be secured.

【図面の簡単な説明】[Brief description of drawings]

【図1】実施例の可変利得回路の構成を示すブロック図
である。
FIG. 1 is a block diagram showing a configuration of a variable gain circuit of an embodiment.

【図2】可変利得回路の構成を具体的に示す回路図であ
る。
FIG. 2 is a circuit diagram specifically showing a configuration of a variable gain circuit.

【図3】変形例の可変利得回路の構成を具体的に示す回
路図である。
FIG. 3 is a circuit diagram specifically showing a configuration of a variable gain circuit of a modified example.

【図4】演算増幅回路を用いた従来の可変利得回路の構
成を示すブロック図である。
FIG. 4 is a block diagram showing a configuration of a conventional variable gain circuit using an operational amplifier circuit.

【図5】従来の可変利得回路の構成を具体的に示す回路
図である。
FIG. 5 is a circuit diagram specifically showing a configuration of a conventional variable gain circuit.

【符号の説明】[Explanation of symbols]

10 演算増幅回路 20 内部位相補償回路 30 位相補償調整回路 40 利得設定回路 50 利得設定制御手段 10 operational amplifier circuit 20 internal phase compensation circuit 30 phase compensation adjustment circuit 40 gain setting circuit 50 gain setting control means

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 入力端子を介して入力される信号の演算
増幅を行う演算増幅回路と、 該演算増幅回路の反転入力端子と出力端子との間に接続
され、前記演算増幅の利得を設定する利得設定回路と、 前記演算増幅が行われる信号の位相補償を行う位相補償
回路とを備えた可変利得回路において、 前記位相補償回路と並列に接続され、前記設定された利
得に応じて前記位相補償を調整する位相補償調整回路
と、 該位相補償の調整と前記利得の設定とを同期させる利得
設定制御手段とを備えたことを特徴とする可変利得回
路。
1. An operational amplifier circuit for performing operational amplification of a signal input through an input terminal, and an operational amplifier circuit connected between an inverting input terminal and an output terminal of the operational amplifier circuit for setting the gain of the operational amplifier. A variable gain circuit comprising a gain setting circuit and a phase compensating circuit for compensating the phase of a signal for which the operational amplification is performed, the variable gain circuit being connected in parallel with the phase compensating circuit, the phase compensating circuit according to the set gain. And a gain setting control means for synchronizing the adjustment of the phase compensation and the setting of the gain.
JP15695195A 1995-05-31 1995-05-31 Variable gain circuit Pending JPH08330868A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15695195A JPH08330868A (en) 1995-05-31 1995-05-31 Variable gain circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15695195A JPH08330868A (en) 1995-05-31 1995-05-31 Variable gain circuit

Publications (1)

Publication Number Publication Date
JPH08330868A true JPH08330868A (en) 1996-12-13

Family

ID=15638904

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15695195A Pending JPH08330868A (en) 1995-05-31 1995-05-31 Variable gain circuit

Country Status (1)

Country Link
JP (1) JPH08330868A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003536343A (en) * 2000-06-19 2003-12-02 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド Programmable gain amplifier for use in data networks
GB2345619B (en) * 1998-10-21 2004-03-03 Nec Corp Phase correction circuit for radio communication apparatus
JP2010232749A (en) * 2009-03-26 2010-10-14 Tdk Corp Amplifier circuit, and optical pickup having the same
US7825728B2 (en) 2008-08-21 2010-11-02 Sharp Kabushiki Kaisha Variable gain circuit

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2345619B (en) * 1998-10-21 2004-03-03 Nec Corp Phase correction circuit for radio communication apparatus
US6721370B1 (en) 1998-10-21 2004-04-13 Nec Corporation Phase correction circuit for radio communication apparatus
JP2003536343A (en) * 2000-06-19 2003-12-02 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド Programmable gain amplifier for use in data networks
US7825728B2 (en) 2008-08-21 2010-11-02 Sharp Kabushiki Kaisha Variable gain circuit
JP2010232749A (en) * 2009-03-26 2010-10-14 Tdk Corp Amplifier circuit, and optical pickup having the same

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