JPH08330715A - Method of soldering printed-substrate and chip - Google Patents

Method of soldering printed-substrate and chip

Info

Publication number
JPH08330715A
JPH08330715A JP13644695A JP13644695A JPH08330715A JP H08330715 A JPH08330715 A JP H08330715A JP 13644695 A JP13644695 A JP 13644695A JP 13644695 A JP13644695 A JP 13644695A JP H08330715 A JPH08330715 A JP H08330715A
Authority
JP
Japan
Prior art keywords
land
solder
chip
opening
circuit board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13644695A
Other languages
Japanese (ja)
Inventor
Seiji Sakami
省二 酒見
Tadahiko Sakai
忠彦 境
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP13644695A priority Critical patent/JPH08330715A/en
Publication of JPH08330715A publication Critical patent/JPH08330715A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3421Leaded components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3452Solder masks

Abstract

PURPOSE: To provide a method of soldering printed-substrate and chip capable of soldering the lead of the chip having a float bending upward onto the land of the printed-substrate without fail. CONSTITUTION: A solder resist film 4 is formed on the surface of a substrate with the land 3 of a circuit pattern formed thereon. Next, an aperture part 5 is formed in the solder resist film 4 on the land 3. This aperture part is provided with narrow width parts 5a and wide width part 5b. When the land 3 exposed in the aperture part 5 is coated with cream solder to be heated for melting down, the solder is absorbed in the wide width part 5b by surface tension to form a swelled part. Accordingly, the floating lead landing on the swelled part can be soldered without fail.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、電子機器に組み込まれ
るプリント基板およびチップの半田付け方法に関するも
のである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed circuit board and a chip soldering method incorporated in an electronic device.

【0002】[0002]

【従来の技術】プリント基板の表面には回路パターンが
形成されており、チップのリードは回路パターンのラン
ドに半田付けされる。ところでチップのリードには、形
成上の誤差や保管運搬時の変形等のために浮き(上方へ
の屈曲)が生じやすい。浮きが生じると、リードはラン
ド上の半田部に接地できず、半田付け不良となる。
2. Description of the Related Art A circuit pattern is formed on the surface of a printed circuit board, and leads of a chip are soldered to lands of the circuit pattern. By the way, the lead of the chip is apt to be lifted (bent upward) due to an error in formation or a deformation during storage and transportation. If floating occurs, the lead cannot be grounded to the solder portion on the land, resulting in poor soldering.

【0003】そこで本出願人は、先に、リードの浮きに
よる半田付け不良を解消できるプリント基板を提案した
(特開平6−77632号公報)。このものは、プリン
ト基板のランドの平面形状を幅狭部と幅広部を有する形
状としたものであり、これにより加熱溶融した半田部は
幅広部へ吸い寄せられて盛り上り部が生じ、したがって
リードに多少の浮きがあっても、リードはこの盛り上り
部に接地して半田付けされるものである。
Therefore, the applicant of the present invention has previously proposed a printed circuit board capable of eliminating soldering failure due to floating of leads (Japanese Patent Laid-Open No. 6-77632). In this product, the planar shape of the land of the printed circuit board is a shape having a narrow portion and a wide portion. As a result, the solder portion heated and melted is attracted to the wide portion and a bulge portion is generated, and therefore the lead Even if there is some floating, the lead is grounded and soldered to this raised portion.

【0004】[0004]

【発明が解決しようとする課題】近年、チップのリード
は益々狭ピッチ化しており、これにともないランドの寸
法も次第に小さくなってきている。ランドはエッチング
などにより形成されるが、このようにランドの寸法が小
さくなると、幅狭部と幅広部を有する複雑な形状のラン
ドは加工技術上形成が困難である。
In recent years, the pitch of the leads of the chip has become narrower and narrower, and the size of the land has become smaller accordingly. Although the land is formed by etching or the like, when the size of the land is reduced in this way, it is difficult to form a land having a complicated shape having a narrow portion and a wide portion in terms of processing technology.

【0005】そこで本発明は、チップのリードの狭ピッ
チ化に対応し、浮きを有するリードを確実に半田付けで
きるプリント基板およびチップの半田付け方法を提供す
ることを目的とする。
Therefore, an object of the present invention is to provide a printed circuit board and a method for soldering a chip, which can cope with a reduction in the pitch of the leads of the chip and can reliably solder a lead having a float.

【0006】[0006]

【課題を解決するための手段】このために本発明は、基
材の表面にランドとこのランドを覆うソルダーレジスト
膜を形成して成り、前記ソルダーレジスト膜に前記ラン
ドを部分的に露呈させる開口部を形成し、この開口部が
幅狭部と幅広部を有する形状としたものである。またこ
の開口部に露呈する前記ランドの上面に半田部を形成し
たものである。
To this end, the present invention is formed by forming a land and a solder resist film covering the land on the surface of a base material, and an opening for partially exposing the land to the solder resist film. A portion is formed, and the opening has a shape having a narrow portion and a wide portion. Further, a solder portion is formed on the upper surface of the land exposed in the opening.

【0007】またランドを部分的に露呈させる幅狭部と
幅広部を有する開口部を形成したソルダーレジスト膜が
コーティングされたプリント基板にチップを半田付けす
るチップの半田付け方法であって、前記開口部に露呈す
る前記ランドの表面に半田部を形成し、チップのリード
をこの半田部上に位置させてチップを前記プリント基板
に搭載した後、前記半田部を加熱して溶融させることに
より、溶融した半田を前記幅広部に吸い寄せて盛り上が
らせ、次いで溶融した半田部を固化させることにより前
記リードを前記ランドに半田付けするようにした。
Further, there is provided a chip soldering method for soldering a chip to a printed circuit board coated with a solder resist film having an opening having a narrow portion and a wide portion for partially exposing the land, wherein the opening is provided. The solder is formed on the surface of the land exposed to the part, the leads of the chip are positioned on the solder part, the chip is mounted on the printed circuit board, and the solder part is heated and melted to melt. The solder was sucked up to the wide portion and raised, and then the molten solder portion was solidified to solder the lead to the land.

【0008】[0008]

【作用】上記構成において、ランド上の半田部を加熱し
て溶融させると、溶融した半田は開口部の幅広部に吸い
寄せられて局所的に盛り上りを生じる。したがってリー
ドに多少の浮きがあっても、リードを盛り上り部に接地
させて確実に半田付けできる。
In the above structure, when the solder portion on the land is heated and melted, the melted solder is attracted to the wide portion of the opening and locally rises. Therefore, even if there is some floating in the lead, the lead can be grounded to the raised portion and reliably soldered.

【0009】[0009]

【実施例】次に、本発明の実施例を図面を参照しながら
説明する。図1は本発明の第一実施例のプリント基板の
平面図、図2は同プリント基板の部分斜視図、図3は同
プリント基板の製造工程の説明図、図4は同チップの実
装工程の説明図である。
Embodiments of the present invention will now be described with reference to the drawings. 1 is a plan view of a printed circuit board according to a first embodiment of the present invention, FIG. 2 is a partial perspective view of the printed circuit board, FIG. 3 is an explanatory view of a manufacturing process of the printed circuit board, and FIG. 4 is a mounting process of the chip. FIG.

【0010】図1および図2において、プリント基板1
の基材2の表面には回路パターンのランド3が形成され
ている。基材2としては、ガラスエポキシ樹脂やセラミ
ックなどが多用されている。基材2の表面にはソルダー
レジスト膜4がランド3を覆うように薄くコーティング
されている。ランド3上のソルダーレジスト膜4には開
口部5が形成されており、ランド3は開口部5から部分
的に露呈している。開口部5は角形の幅狭部5aと円形
の幅広部5bを有している。後述するように、開口部5
に幅狭部5aと幅広部5bを形成することにより、ラン
ド3上の半田を溶融させると、溶融した半田は幅広部5
bに吸い寄せられて盛り上る。
1 and 2, the printed circuit board 1
A land 3 having a circuit pattern is formed on the surface of the substrate 2. As the base material 2, glass epoxy resin, ceramics, etc. are often used. A solder resist film 4 is thinly coated on the surface of the base material 2 so as to cover the lands 3. An opening 5 is formed in the solder resist film 4 on the land 3, and the land 3 is partially exposed from the opening 5. The opening 5 has a rectangular narrow portion 5a and a circular wide portion 5b. As will be described later, the opening 5
When the solder on the land 3 is melted by forming the narrow portion 5a and the wide portion 5b on the land, the melted solder is
It is attracted to b and rises.

【0011】次に図3を参照して、プリント基板1の製
造方法を説明する。まず図3(a)に示すように、基材
2の表面に銅箔3’を形成する。次にその表面にエッチ
ング用レジスト膜6をコーティングし(図3(b))、
次に露光・現像を行ってエッチング用レジスト膜6の不
要部を除去する(図3(c))。
Next, a method of manufacturing the printed circuit board 1 will be described with reference to FIG. First, as shown in FIG. 3A, a copper foil 3 ′ is formed on the surface of the base material 2. Next, the surface is coated with an etching resist film 6 (FIG. 3B),
Next, exposure and development are performed to remove unnecessary portions of the etching resist film 6 (FIG. 3C).

【0012】次に銅箔エッチングを行って銅箔3’の不
要部を除去し(図3(d))、エッチング用レジスト膜
6を剥離する(図3(e))。次いで基材2の表面全面
にソルダーレジスト膜4’をコーティングし(図3
(f))、露光・現像を行って不要部を除去すれば、図
1に示すプリント基板1が完成する(図3(g))。
Next, copper foil etching is performed to remove unnecessary portions of the copper foil 3 '(FIG. 3 (d)), and the etching resist film 6 is peeled off (FIG. 3 (e)). Next, the entire surface of the base material 2 is coated with a solder resist film 4 '(see FIG.
(F)), if the unnecessary portion is removed by performing exposure and development, the printed circuit board 1 shown in FIG. 1 is completed (FIG. 3 (g)).

【0013】この後、スクリーン印刷機により開口部5
に露呈するランド3上にクリーム半田7’を塗布する
(図3(h))。そしてこのプリント基板1を加熱炉で
加熱し、クリーム半田7’を溶融させた後、固化させれ
ば半田部7が出来上る(図3(i))。この場合、溶融
したクリーム半田7’は表面張力によって幅広部5bへ
吸い寄せられて盛り上り部7aが生じる。
Thereafter, the opening 5 is formed by a screen printing machine.
The cream solder 7'is applied onto the land 3 exposed to the outside (FIG. 3 (h)). Then, the printed circuit board 1 is heated in a heating furnace to melt the cream solder 7'and then solidify the soldered portion 7 (FIG. 3 (i)). In this case, the melted cream solder 7'is attracted to the wide portion 5b by the surface tension and the raised portion 7a is generated.

【0014】上記方法によれば、上記特開平6−776
32号公報に記載した従来方法、すなわちランド自体に
幅狭部と幅広部を形成する方法と実質的に同じ効果を得
ることができる。そして、例えば化学的エッチングによ
ってランド自体に幅狭部や幅広部を形成する従来方法よ
りも、ランド3を比較的大形に形成し、その上面のソル
ダーレジスト膜4’に光学的手段によって幅狭部5aと
幅広部5bを有する開口部5を形成する上記方法の方
が、プリント基板を精密に製造できる。
According to the above method, the above-mentioned Japanese Unexamined Patent Publication No. 6-776.
It is possible to obtain substantially the same effect as the conventional method described in Japanese Patent No. 32,32, that is, the method of forming the narrow portion and the wide portion on the land itself. Then, the land 3 is formed in a relatively large size as compared with the conventional method of forming a narrow portion or a wide portion on the land itself by, for example, chemical etching, and the solder resist film 4 ′ on the upper surface is narrowed by an optical means. The above method of forming the opening 5 having the portion 5a and the wide portion 5b allows the printed circuit board to be manufactured more accurately.

【0015】次に、図4を参照してチップの半田付け方
法を説明する。図4(a)において、8はチップであ
り、多数本のリード9を有している。図において、右側
のリード9の形状は正常であるが、左側のリード9は上
方へ屈曲して浮いている。
Next, a method of soldering the chip will be described with reference to FIG. In FIG. 4A, 8 is a chip, which has a large number of leads 9. In the drawing, the shape of the lead 9 on the right side is normal, but the lead 9 on the left side is bent upward and floats.

【0016】さて図3(a)〜(g)の工程により製造
されたプリント基板1のランド3上に、図3(h)の工
程によりクリーム半田7’を塗布する。図4(a)は、
このクリーム半田7’上にリード9を位置させて、チッ
プ8をプリント基板1に搭載した状態を示している。な
おチップ8はマウンタによりプリント基板1に自動搭載
される。この場合、左側のリード9は浮きがあるため、
クリーム半田7’に接地できずに浮き上っている(図3
(h)のリード9も参照)。
Now, the cream solder 7'is applied on the land 3 of the printed board 1 manufactured by the steps of FIGS. 3A to 3G by the step of FIG. 3H. Figure 4 (a)
The state where the lead 9 is positioned on the cream solder 7 ′ and the chip 8 is mounted on the printed circuit board 1 is shown. The chip 8 is automatically mounted on the printed board 1 by a mounter. In this case, the lead 9 on the left side has a floating
It cannot be grounded to the cream solder 7'and it is floating (Fig. 3).
(See also lead 9 in (h)).

【0017】次にプリント基板1は加熱炉へ送られて加
熱される。するとクリーム半田7’は溶融するが、溶融
したクリーム半田7’は図3(i)に示すように幅広部
5bに吸い寄せられて盛り上り部7aを生じる。したが
ってリード9に浮きがあっても、リード9はこの盛り上
り部7aに接地し(図3(i)のリード9を参照)、溶
融してリード9の下面に接地する盛り上り部7aは、リ
ード9の下面に吸い寄せられ、図4(b)に示すように
半田付けされる。
Next, the printed board 1 is sent to a heating furnace and heated. Then, the cream solder 7 ′ is melted, but the melted cream solder 7 ′ is attracted to the wide portion 5 b as shown in FIG. Therefore, even if the lead 9 floats, the lead 9 is grounded to the raised portion 7a (see the lead 9 in FIG. 3 (i)), and the raised portion 7a that is melted and grounded to the lower surface of the lead 9 is It is attracted to the lower surface of the lead 9 and soldered as shown in FIG.

【0018】図5は本発明の第二実施例のプリント基板
の部分平面図である。この例では相隣る幅広部5bは千
鳥状に形成されており、このようにすることにより相隣
る幅広部5b同士を引き離して、これらの間において半
田ブリッジが生じるのをより効果的に防止できる。
FIG. 5 is a partial plan view of a printed circuit board according to the second embodiment of the present invention. In this example, the adjacent wide portions 5b are formed in a zigzag shape, and by doing so, it is possible to more effectively prevent the adjacent wide portions 5b from being separated from each other and to form a solder bridge between them. it can.

【0019】本発明は上記実施例に限定されないのであ
って、例えばランド上には、クリーム半田にかえて、半
田メッキ手段や半田レベラ手段などの他の手段により半
田部を形成してもよいものである。また開口部の具体的
形状も上記実施例に限定されないのは勿論であって、要
は幅狭部と幅広部を有する形状にして、溶融した半田が
幅広部へ吸い寄せられて盛り上り部が生じるようにすれ
ばよい。
The present invention is not limited to the above-described embodiment. For example, instead of cream solder, a solder portion may be formed on the land by other means such as solder plating means or solder leveler means. Is. Further, the specific shape of the opening is not limited to the above-described embodiment, of course, the point is to have a shape having a narrow portion and a wide portion, and melted solder is attracted to the wide portion to generate a bulge portion. You can do it like this.

【0020】[0020]

【発明の効果】本発明は、ソルダーレジスト膜に幅狭部
と幅広部を有する開口部を形成し、この開口部からラン
ドを部分的に露呈させるようにしているので、ランド上
で溶融した半田は幅広部へ吸い寄せられて盛り上り部を
生じることとなり、したがってリードに多少の浮きがあ
っても、リードを半田に接地させて確実に半田付けでき
る。またランド自体に幅狭部や幅広部を形成する従来方
法よりもプリント基板の製造が容易であり、リードの狭
ピッチ化に容易に対応することができる。
According to the present invention, an opening having a narrow portion and a wide portion is formed in the solder resist film, and the land is partially exposed from the opening. Will be attracted to the wide portion to form a raised portion, and therefore, even if the lead has some floating, the lead can be grounded to the solder and reliably soldered. Further, the printed circuit board can be manufactured more easily than the conventional method of forming the narrow width portion or the wide width portion on the land itself, and the lead pitch can be easily reduced.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の第一実施例のプリント基板の平面図FIG. 1 is a plan view of a printed circuit board according to a first embodiment of the present invention.

【図2】本発明の第一実施例のプリント基板の部分斜視
FIG. 2 is a partial perspective view of a printed circuit board according to a first embodiment of the present invention.

【図3】本発明の第一実施例のプリント基板の製造工程
の説明図
FIG. 3 is an explanatory diagram of a manufacturing process of the printed circuit board according to the first embodiment of the present invention.

【図4】本発明の第一実施例のチップの実装工程の説明
FIG. 4 is an explanatory diagram of a chip mounting process according to the first embodiment of the present invention.

【図5】本発明の第二実施例のプリント基板の部分平面
FIG. 5 is a partial plan view of a printed circuit board according to a second embodiment of the present invention.

【符号の説明】[Explanation of symbols]

1 プリント基板 2 基材 3 ランド 4 ソルダーレジスト膜 5 開口部 5a 幅狭部 5b 幅広部 6 銅箔 7 半田部 7a 盛り上り部 8 チップ 9 リード 1 Printed Circuit Board 2 Base Material 3 Land 4 Solder Resist Film 5 Opening 5a Narrow Part 5b Wide Part 6 Copper Foil 7 Solder Part 7a Rise Part 8 Chip 9 Lead

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】基材の表面にランドとこのランドを覆うソ
ルダーレジスト膜を形成して成り、前記ソルダーレジス
ト膜に前記ランドを部分的に露呈させる開口部を形成
し、この開口部が幅狭部と幅広部を有することを特徴と
するプリント基板。
1. A land and a solder resist film covering the land are formed on a surface of a base material, and an opening is formed in the solder resist film to partially expose the land, and the opening is narrow. A printed circuit board having a wide portion and a wide portion.
【請求項2】基材の表面にランドとこのランドを覆うソ
ルダーレジスト膜を形成して成り、前記ソルダーレジス
ト膜に前記ランドを部分的に露呈させる開口部を形成
し、この開口部が幅狭部と幅広部を有し、かつこの開口
部に露呈する前記ランドの上面に半田部を形成したこと
を特徴とするプリント基板。
2. A land and a solder resist film covering the land are formed on the surface of a base material, and an opening is formed in the solder resist film to partially expose the land, and the opening is narrow. A printed circuit board having a portion and a wide portion, and a solder portion is formed on an upper surface of the land exposed at the opening.
【請求項3】ランドを部分的に露呈させる幅狭部と幅広
部を有する開口部を形成したソルダーレジスト膜がコー
ティングされたプリント基板にチップを半田付けするチ
ップの半田付け方法であって、前記開口部に露呈する前
記ランドの表面に半田部を形成し、チップのリードをこ
の半田部上に位置させてチップを前記プリント基板に搭
載した後、前記半田部を加熱して溶融させることによ
り、溶融した半田を前記幅広部に吸い寄せて盛り上がら
せ、次いで溶融した半田部を固化させることにより前記
リードを前記ランドに半田付けすることを特徴とするチ
ップの半田付け方法。
3. A chip soldering method for soldering a chip to a printed circuit board coated with a solder resist film having an opening having a narrow portion and a wide portion for partially exposing a land. By forming a solder portion on the surface of the land exposed in the opening, the lead of the chip is located on the solder portion and the chip is mounted on the printed circuit board, by heating and melting the solder portion, A method for soldering a chip, characterized in that molten solder is attracted to the wide portion to be raised, and then the molten solder portion is solidified to solder the lead to the land.
JP13644695A 1995-06-02 1995-06-02 Method of soldering printed-substrate and chip Pending JPH08330715A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13644695A JPH08330715A (en) 1995-06-02 1995-06-02 Method of soldering printed-substrate and chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13644695A JPH08330715A (en) 1995-06-02 1995-06-02 Method of soldering printed-substrate and chip

Publications (1)

Publication Number Publication Date
JPH08330715A true JPH08330715A (en) 1996-12-13

Family

ID=15175310

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13644695A Pending JPH08330715A (en) 1995-06-02 1995-06-02 Method of soldering printed-substrate and chip

Country Status (1)

Country Link
JP (1) JPH08330715A (en)

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