JPH08328999A - Method and device for transferring data - Google Patents

Abstract

PURPOSE: To provide the device and method for transferring data with which the reliability of data transfer through a high-speed internal common bus can be improved and the effective transfer speed of data can be prevented from being decelerated. CONSTITUTION: A function block 11 is provided with two transmission buffers 14 and 15, and the data transfer speed of the transmission buffer 15 on the side of an internal common bus 19 is set higher than the data transfer speed of the other transmission buffer 14. While the next data are received from the transmission buffer 14 to the transmission buffer 15, the data in the transmission buffer 15 are transmitted to the transmission destination plural times, inside the function block 11 of the transmission destination, the received data are stored in a reception buffer 13 and error detection is performed by an error detection circuit 12. Until it is recognized that the normal data are received, the error detection and data abandonment are repeated to the same data received plural times.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer method in a data processing device for transferring data using an internal common bus and its device.

[0002]

2. Description of the Related Art FIG. 2 is a block diagram showing a configuration example of a conventional data processing device. A data processing device such as a personal computer is composed of many functional blocks, and these are connected to each other via an internal common bus.

These functional blocks have configurations and names according to their functions. For example, in FIG. 2, 1 is a microprocessor (hereinafter, CPU), 2 is a memory, 3 is a data processing block, and 4 is external to the apparatus. Data input / output blocks (I / O), 5 are bus control circuits, 6 is a functional block such as a DMA controller (DMAC), and 7 is an internal common bus.

The above functional block may be mounted on the motherboard in an on-board form, or may be mounted as an add-in board in a slot. In many data processing devices, predetermined data processing is performed by transferring data between many functional blocks such as the CPU, memory, and data processing blocks shown in FIG. 2 via an internal common bus. For example, data transfer is performed between the data processing block 3 and the I / O block 4, or between the CPU 1 and the memory 2 via the internal common bus 7.

If the I / O block 4 is connected to an external storage device such as an external hard disk (HDD), the data sent from the external storage device is sent to the data processing block 3 through the internal common bus 7, for example. After the transfer and the completion of predetermined data processing such as data compression / expansion, the operation such as transfer and storage in the memory 2 via the internal common bus 7 is performed.

Further, a buffer composed of a FIFO memory or the like is often provided for speed matching between these functional blocks. For example, as shown in FIG. 2, the memory 2, data processing 3, I / O block 4, etc. It is often installed in
It may be provided in another functional block. The transferred data will be buffered by these buffers and then taken into the functional block.

Regarding the reliability of data transfer on the internal common bus in such a data processor, there is known a system in which a bus parity is provided to improve the reliability by a parity check. For example, in the PCI bus which has been used in many personal computers recently, a "PAR" signal is defined as a bus parity bit, and a parity function may be provided in a functional block (agent) connected to the PCI bus. Specified (“Details of PCI Bus and Steps to Application”, published by CQ Publisher).

Error handling in the PCI bus is performed based on this bus parity check, and the functional block that sends data generates even parity for the sum of the address data bus line and the bus command line to represent the parity bit.
Parity data is asserted on the "PAR" signal line. This "PAR" signal is checked by the functional block that receives the data, and if a parity error is detected, the "PERR #" signal line indicating error detection is activated. The block (initiator) that controls data transfer is
When it detects that the PERR # ”signal is asserted,
After trying to recover an error such as data retransmission, the system is notified and thereafter the system enters an error processing routine.

As described above, in the internal common bus configuration of the conventional data processor, the error check is performed by the parity check or the like, but the error recovery method is mainly the method of retransmitting the data. Include, for example, parity generation and error signals (eg, "PERR").
A number of steps, that is, a number of steps such as taking several clocks for asserting the # "signal and taking the same number of clocks as the previous time for setting the resending cycle, have led to a significant decrease in the effective data transfer rate.

On the other hand, in such a data processing device, there is often a large difference between the data transfer speed between the external device via the external interface and the transfer speed of the internal common bus. For example, if the I / O block is connected to an external storage device such as a hard disk (HDD) or a magneto-optical disk (MO), SCSI
Alternatively, an interface known as IDE is often used for connection, and in these interface standards, for example, even if the maximum value in the standard is 5M with SCSI-1,
Even with B / s and SCSI-2, there is only a data transfer rate of about 10 MB / s, and the internal data transfer rate of HDDs, MOs, etc. is actually slower, and the effective data transfer rate is due to the overhead due to the transfer process. Is also said to be about a fraction of the standard value.

On the other hand, the transfer speed of the internal common bus is I
It has been said that several MB / s is used for the SA bus and the like, but a maximum data transfer rate of 132 MB / s has been obtained for the EISA bus, the VL bus, and the PCI bus that have recently become widespread for high-speed transfer. In order to fill this transfer speed gap, a large-capacity buffer is provided especially in the I / O block connected to the external storage device, and the data in the buffer is sent to the bus at high speed to improve the effective transfer speed. It has been known.

The location of this buffer may be, for example, on the HDD device side or on the functional block as the SCSI board. In any case, the buffer installation in the conventional functional block is stored in the buffer. It was the method of use mainly for the high-speed transmission of the collected data.

[0013]

However, as described above, in the data transfer on the internal common bus of the conventional data transfer apparatus, the error check method by the parity bit check is mainly used to recover the data when an error occurs. In order to do so, it is often the case that a data recovery method using data is used instead of correcting received data. Since this data retransmission takes a lot of time, there is a problem in that it effectively lowers the data transfer rate.

In view of the above problems, an object of the present invention is to improve the reliability of data transfer on a high-speed internal common bus and prevent a decrease in effective data transfer rate, and a data transfer method. To provide.

[0015]

In order to achieve the above object, the present invention provides, in claim 1, a data transfer method for performing data transfer between functional blocks via a bus. Is provided with at least two transmission data buffers connected in series, the data transfer speed of the transmission data buffer of the final stage is set to be higher than the data transfer speeds of other transmission data buffers, and While the next data is received from the transmission data buffer of the previous stage, the data in the transmission data buffer of the final stage is transmitted to the destination multiple times while receiving the data in the functional block that is the transmission destination. The receiving unit detects an error in the received data received from the data transmitting unit, and when the received data is recognized as normal, the data is When notifying the data transmitting unit that it is always the same and discarding the same data thereafter and recognizing that the received data is abnormal, until the received data is discarded and it is recognized that normal data is received thereafter. A data transfer method is proposed in which error detection and data discard are repeated for the same data received a plurality of times.

According to a second aspect of the present invention, in the data transfer method according to the first aspect, when it is recognized that all of the same data received a plurality of times are abnormal, a data transfer for notifying that a data reception error has occurred. Suggest a method.

According to a third aspect of the present invention, in a data transfer device for performing a data transfer process between functional blocks via a bus, the same data stored inside is transmitted to a transmission destination in a data transmission section in the functional block. To the last stage transmission data buffer, and at least one transmission that is connected to the last stage transmission data buffer and is set at a speed lower than the data transfer rate of the last stage transmission data buffer. A data buffer is provided, and in the data receiving section in the functional block, a receiving buffer for accumulating data received from the transmission source, and an error in the received data is detected, and the same data transmitted a plurality of times by the transmitting means. There is proposed a data transfer device provided with an error detecting means for making the data that can be normally received among the received data the received data.

[0018]

According to the data transfer method of the first aspect of the present invention, at least two transmission data buffers connected in series are provided in the data transmission unit in the functional block, and the data of the transmission data buffer at the final stage is provided. The transfer rate is set to be higher than the data transfer rates of other transmission data buffers. Further, the data in the final stage transmission data buffer is transmitted to the destination a plurality of times while the final stage transmission data buffer receives the next data from the previous stage transmission data buffer.

On the other hand, in the data receiving section in the functional block which is the transmission destination, error detection of the received data received from the data transmitting section is performed, and when the received data is recognized as normal, the data is received. The normality is notified to the data transmitting unit, and the same data thereafter is discarded. Further, when the received data is recognized as abnormal, the received data is discarded, and thereafter, error detection and data discard are performed on the same data received a plurality of times until it is recognized that normal data is received. Repeated.

A functional block according to the present invention has a buffer structure according to its function, and the functional block becomes a master block (receiving data) or a target block (transmitting data), or its Different buffer configurations are implemented depending on whether they have both functions.

For example, when considering the case where a certain functional block becomes a master block and data is taken in from an external interface through a functional block that becomes a target block, the target block is provided with, for example, a two-stage transmission data buffer, Based on the instruction from the master block, data transfer via the buffer is started in the target block.

First, in the target block, data is taken into the target block from an external storage device or the like through a low-speed external interface, and the data is buffered in the first transmission data buffer through the functional circuit section. Then, the data is transferred from the first transmission data buffer to the final second transmission data buffer.

The second transmission data buffer is connected to the internal common bus side, which is a high-speed interface, and sends the data in the buffer to the internal common bus at high speed. SC
Since the data transfer rate from the external storage device connected by the interface such as SI or IDE is significantly smaller than the data transfer rate of the high speed internal common bus such as PCI bus, the second transmission data buffer sends the data. After that, a large waiting time occurs until the first transmission data buffer accumulates data. Therefore, in the second transmission data buffer, N (= 2, 3, ...) times of data are accumulated until the data is accumulated in the first transmission data buffer and the data is transferred to the second transmission data buffer again. Can be sent to the bus.

On the other hand, the master block for receiving data is provided with a receiving buffer and an error detecting means for detecting an error such as a parity check. For N times of data transmitted from the target block, first, after receiving the first data in the reception buffer, for example, a parity check is performed, and when it is recognized as a normal signal, a normal end signal is sent to the target block. At the same time, the received data is transferred to the memory unit, and subsequent received data is ignored.

When an error is detected by the parity check, the data is discarded from the reception buffer, the next data is received in the reception buffer, and the parity check is performed again.

Until normal data is input, or N
The above inspection cycle is repeated until the data reception is completed. This makes it possible to recover from an accidental data error without retransmitting the data. If normal data cannot be obtained even after N times of data inspection, it is considered that a fatal error exists. Therefore, it is possible to quickly deal with the problem by reporting it to the system or the like.

When the first transmission data buffer has accumulated a predetermined amount of data and the second transmission data buffer has transmitted N times of data, the first transmission data buffer becomes the second transmission data buffer. The data is transferred to, and then the above cycle is repeated until the transfer of all data is completed.

As described above, by providing at least a two-stage transmission data buffer in the functional block on the data transmitting side and providing the receiving buffer and the error detecting means in the corresponding functional block on the data receiving side, a high-speed internal common bus can be provided. It enables data transfer with high reliability.

According to the data transfer method of the second aspect, when it is recognized that all of the same data received a plurality of times are abnormal, a data reception error is notified to the system or the like.

According to another aspect of the data transfer device of the present invention, the data transmission section in the functional block is provided with at least two transmission data buffers connected in series.
The data transfer rate of the final stage transmission data buffer is set to be higher than the data transfer rates of the other transmission data buffers. Also, the same data in the last-stage transmission data buffer is transmitted to the destination a plurality of times.

Further, in the data receiving section in the functional block, the data received from the transmission source is accumulated in the reception buffer, an error in the received data is detected by the error detecting means, and the transmission data at the final stage is also detected. Of the same data transmitted from the buffer a plurality of times, the data that has been successfully received is the received data.

[0032]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a configuration diagram showing functional blocks in this embodiment. The configuration of the data processing device including this functional block is the same as that of the conventional example shown in FIG.

As shown in FIG. 2, for example, the conventional data processing apparatus is composed of many functional blocks such as a CPU 1, a memory 2, and a data processing block 3, and these functional blocks are connected via an internal common bus 7. Predetermined data processing is performed by performing data transfer by performing data transfer.

These functional blocks may be on-board devices such as memories and caches, but in many cases, they may also be data input / output interface boards with external devices such as SCSI boards and LAN boards as add-in boards. In the case of these external data input / output interfaces, a buffer memory such as a small-capacity FIFO is often mounted in the interface section with the internal common bus 7 to perform speed matching, etc. It was not functional. Although FIG. 2 shows an example in which the memory 2, the data processing block 3, and the I / O block 4 are provided with buffers, other functional blocks may be provided with buffers.

Arbitrary functional blocks in this embodiment are
For example, as shown in FIG. 1, it has a buffer configuration in which two stages are connected in series. That is, the arbitrary functional block 11 is
Different buffers are used when operating in the read mode for sending data to the internal common bus 19 and operating in the write mode for receiving data from the internal common bus 19. In the read mode operation, the first transmission buffer 14 involved in data transfer is the functional circuit unit 16 in the block.
And the second transmission buffer 15 is connected to the internal common bus 1
9 is connected. The data output from the functional circuit unit 16 passes through the first transmission buffer 14 and then is output from the second transmission buffer 15 to the internal common bus 19.

On the other hand, in the write mode operation, after the data from the internal common bus 19 is received by the reception buffer 13, the error detection circuit 12 performs an error check such as a parity check on the received data, and the received data functions. It is delivered to the circuit unit 16.

When the functional block 11 is connected to the external storage device, the functional circuit section 16 is connected to the external storage device via the external interface 17. Although the configuration of FIG. 1 shows the case where the functional block 11 realizes both the read mode and the write mode, it goes without saying that if the mode function is dedicated, only the appropriate configuration need be provided. Further, the buffer may be provided in three or more stages.

FIG. 3 is a diagram for explaining a data transfer process between functional blocks according to the present invention. In FIG. 3, 2
1 is a master block, 22 is a receive buffer in the master block, 23 is an error detection circuit in the master block, 2
Reference numeral 4 is a memory section, and 25 is a control signal such as a normal end signal. Further, 26 is a target block, 27 is a first transmission buffer in the target block, 28 is a second transmission buffer, 29 is a functional circuit section in the target block, 30 is control signals for the target block, Reference numeral 31 denotes an external interface between the target block and an external device, and 32 denotes an internal common bus.

Here, the master block 21 is a functional block for receiving data, and the target block 26 is a functional block for transmitting data. Further, the target block 26 receives data from the external interface 31 and sends the data to the memory unit 2 of the master block 21.
4 shall be transferred. The functional blocks such as the master block 21 and the target block 26 have the configuration shown in FIG.

The definitions of the master block 21 and the target block 26 are only related to the reception and transmission of data. For example, under the control of the master block 21, the master block 21 itself may fetch data from the target block 26. If so, target block 2
Data may be transmitted from the target block 26 to the master block 21 under the control of 6. Data may be transmitted and received under the control of another functional block, for example, the DMAC block.

Next, the operation of this embodiment having the above configuration will be described. For example, in order for the master block 21 to perform data processing such as arithmetic processing and accumulation processing on the data stored in the external storage device, the master block 21 fetches the data into the memory unit 24 in the block itself, and therefore an external interface connected to the external connection device. Target block 2 with 31
Consider the case where data is transferred to the master block 21 via 6.

First, the master block 21 transmits a control signal related to data transfer to the target block 26 via the internal common bus 32. The target block 26 is
Based on the instruction, predetermined data is input to the functional circuit unit 29 from the external storage device via the external interface 31, and then transferred to the first transmission buffer 27. The first data is immediately transferred to the second transmission buffer 28 and output to the high speed internal common bus 32 toward the master block 21.

Interfaces such as SCSI and IDE are known as the external interface 31. Generally, the data transfer rate of these interfaces is significantly lower than the data transfer rate of the internal common bus 32. After the transmission buffer 28 outputs the data to the internal common bus 32, a large waiting time occurs until the next data is input all together. Therefore, the second transmission buffer 28 uses the time until the data is transferred to the second buffer 28 again after a predetermined time has elapsed after the data is accumulated in the first transmission buffer 27. Then, the data of a predetermined N (= 2, 3, ...) Times is sent to the internal common bus 32.

On the other hand, the master block 2 which receives data
1 includes a reception buffer 22 and an error detection circuit 23 that performs an error check such as a parity check.
For N times transmitted data from the target block 26, after first receiving the first data in the reception buffer 22, an error check is performed by the error detection circuit 23, and when it is recognized as a normal signal, control of normal end is performed. The signal is sent to the target block 26, the received data is transferred to the memory unit 24, and the subsequent received data is ignored. The transmission of this normal end signal and the continuous transmission of data from the target block 26 are performed asynchronously.

When an error is detected by the error check of the error detection circuit 23, the data is discarded from the receive buffer 22, the second received data is received by the receive buffer 22, and the error check is performed again. .

The above inspection cycle is repeated until the data recognized as normal is input or the data reception of N times is completed. As a result, in the event of a data error that occurs accidentally, it is possible to recover the error without performing data retransmission control, and it is possible to perform data transfer with high reliability and a high effective transfer rate.

If normal received data cannot be obtained even after N data inspections, it is considered that a fatal error has occurred. Therefore, by immediately reporting the error to the system or the like, it is possible to quickly deal with it.

In the target block 26, when the second transmission buffer 28 finishes sending the data N times, the first transmission buffer 27 transfers the data to the second transmission buffer 28, and then from the external storage device. By repeating the above cycle until the transfer of all the data is completed, it becomes possible to construct a highly reliable data transfer method.

In the above description, the function block receives data from the external storage device. However, even when the data is sent from one function block to the external storage device through the external interface of another function block, for example. There is no change in the transfer operation. In this case, the functional block that sends data to the internal common bus 32 is provided with a two-stage buffer, and the functional block connected to the external interface is provided with a reception buffer and the like.

Further, the number of times of data transfer (N times) is not necessarily limited to the number of times which is uniformly determined from the time when the data is stored in the first transmission buffer 27, and the margin is estimated according to the request of the system. There is a degree of freedom such as setting the number of times or setting a large number of times to increase the reliability of data. A fixed number of times may be set in advance, and it may be set for each functional block, or may be set dynamically by monitoring the data transfer rate.

By thus providing the two-stage buffer in the functional block on the data transmitting side and providing the error detecting function in the corresponding functional block on the data receiving side,
It is possible to transfer data with high reliability on a high-speed internal common bus.

Although the parity signal (PAR) is delayed by one clock as a general-purpose bus such as a PCI bus, the generation of the parity signal only causes a delay of one clock in this case. There is no significant problem in the effect of data transfer according to the present invention.

In the above description, the functional block that receives data is defined as the master block, and the functional block that sends data is defined as the target block.
This is a definition for the sake of convenience focusing only on transmission / reception of data, and is not a definition related to “master / target / slave” in controlling data transfer defined in the bus standard or the like. The master block in the text merely indicates a functional block that receives data.

Regarding the control of data transfer, as described above, the master block or the target block may control each case, and another functional block such as the DMAC block may control, but the buffer configuration for data transfer changes. is not.

[0055]

As described above, according to the data transfer method of the first aspect of the present invention, the functional block on the data transmission side is provided with the transmission data buffer having at least two stages,
The corresponding data receiving side functional block is equipped with a receiving buffer and error detection means, and correct data is selected from multiple times of the same received data, so highly reliable data transfer is possible on a high-speed internal common bus. It will be possible.

Further, according to claim 2, in addition to the above effect, when it is recognized that all of the same data received a plurality of times are abnormal, the system or the like is notified as a data reception error. The reliability can be improved.

According to the data transfer device of the third aspect, the functional block for transmitting data is provided with a transmission data buffer having at least two stages, and the final stage is set during data accumulation in the transmission data buffer immediately before the final stage. The same data is sent multiple times from the transmission buffers of the stages, and the functional block that receives the data is provided with a reception buffer that receives the same data multiple times and an error detection unit that detects an error in the received data. Since correct data is selected from the same received data, highly reliable data transfer on a high-speed internal common bus becomes possible.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing functional blocks in an embodiment of the present invention.

FIG. 2 is a configuration diagram showing a data processing device including functional blocks of a conventional example.

FIG. 3 is a diagram illustrating a data transfer operation according to an embodiment of the present invention.

[Explanation of symbols]

1 ... Function block (CPU), 2 ... Function block (memory), 3 ... Function block (data processing), 4 ... Function block (I / O), 5 ... Function block (bus control circuit),
6 ... Functional block (DMAC), 7 ... Internal common bus, 1
DESCRIPTION OF SYMBOLS 1 ... Functional block, 12 ... Error detection circuit, 13 ... Reception buffer, 14 ... 1st transmission buffer, 15 ... 2nd transmission buffer, 16 ... Functional circuit part, 17 ... External interface, 18 ... Control signals, 19 ... Internal Common bus, 21 ... Master block, 22 ... Reception buffer, 23 ... Error detection circuit, 24 ... Functional circuit section (memory section), 25 ... Control signals, 26 ... Target block, 27 ... First transmission buffer, 28 ... 2 transmission buffer, 29 ... Functional circuit section, 30
... control signals, 31 ... external interface, 32 ... internal common bus.

Claims (3)

[Claims] 1. A data transfer method for performing a data transfer process between functional blocks via a bus, wherein a data transmission unit in the functional block is provided with at least two transmission data buffers connected in series, and a final stage is provided. While setting the data transfer rate of the transmission data buffer of the above to be higher than the data transfer rate of the other transmission data buffer, and while receiving the next data from the transmission data buffer of the previous stage in the transmission data buffer of the last stage The data in the transmission data buffer of the stage is transmitted to the destination a plurality of times, and in the data receiving unit in the functional block that is the destination,
The error detection of the received data received from the data transmission unit is performed, and when the received data is recognized to be normal, the data transmission unit is notified that the data is normal and the subsequent same data is discarded, When it is recognized that the received data is abnormal, the received data is discarded, and thereafter, error detection and data discard are repeated for the same data received a plurality of times until it is recognized that normal data is received. Data transfer method. 2. The data transfer method according to claim 1, further comprising notifying that a data reception error has occurred when recognizing that all of the same data received a plurality of times are abnormal. 3. A data transfer device for performing a data transfer process between functional blocks via a bus, wherein the same data stored inside is sent to a destination a plurality of times in a data transmission unit in the functional block. A final stage transmission data buffer for transmission and at least one transmission data buffer that is connected to a stage preceding the final stage transmission data buffer and is set at a speed lower than the data transfer rate of the final stage transmission data buffer are provided. Together with the data receiving unit in the functional block, a receiving buffer for accumulating the data received from the transmission source, an error in the received data is detected, and the same data of a plurality of times of the same data transmitted by the transmitting unit is normally detected. A data transfer device comprising: an error detection unit that uses received data as received data.