JPH08321178A - Static random access memory - Google Patents

Abstract

PURPOSE: To obtain a static random access memory which prevents a malfunction when the storage information of a nonselective memory cell is inverted by not using a column word line and constituting a circuit in such a way that sources of two N-channel transistors are grounded. CONSTITUTION: A memory cell 1 is constituted of N-channel transistors(Trs) Q1 to Q4, high-resistance elements R1, R2, storage terminals N1, N2, and digit lines D, the inverse of D. In the memory cell 1, a column word line is not used, and sources of the Trs Q1, Q2 are grounded. An FF circuit is constituted of the Trs, Q1, Q2 and the high-resistance elements R1, R2, and memory information is stored in the terminals N1, N2 as a complementary signal. In addition, the digit lines D, the inverse of D are prevented from being varied greatly negatively by N-channel transistors Trs Q31, Q32 which are connected to a terminal 5 for receiving a first bias voltage together with a drain. A second bias voltage source 7 is constituted by dividing the Vdd by means of a resistor divider, and a voltage which is lower than the threshold voltage of the Trs Q31, Q32 is supplied.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated memory, and more particularly to a static random access memory capable of preventing malfunction due to parasitic capacitance between digit lines.

[0002]

2. Description of the Related Art Recently, static random access memories (hereinafter referred to as SRAMs) have been rapidly increased in capacity as well as in speed, and along with this, word lines and digit lines are significantly lengthened. Further, the distance between the word lines and the distance between the digit lines have become smaller with the miniaturization of the process, and the parasitic capacitance per unit length has increased. Therefore, since the parasitic capacitance between the word lines and between the digit lines is rapidly increasing, noise jumps in through the parasitic capacitance, and a malfunction tends to occur. For these reasons, it is desired to provide an SRAM that operates stably by preventing malfunction due to crosstalk between wirings.

FIG. 7 shows a circuit of a memory cell of a conventional SRAM of this type. In the figure, N-channel transistors Q1 and Q2 have their drains and gates cross-connected to each other, and their sources are grounded. The high resistance elements R1 and R2 are N-channel transistors Q serving as terminals for storing memory information.
It is an element that supplies a holding current to the drains N1 and N2 of 1 and Q2, and constitutes a flip-flop together with the N-channel transistors Q1 and Q2. Q3 and Q4, whose gates are connected to the word line W, are used for inputting / outputting stored information to / from the terminals N1 and N2 and the digit lines D and D bar, respectively.

Normally, the voltage of the word line W is at low level, and the stored information of the memory cell is stored in the terminals N1 and N2 as complementary signals. During the read operation of the stored information, the voltage of the word line W is raised from the low level to the high level, the N-channel transistors Q3 and Q4 are made conductive, and the stored information stored in the storage terminals N1 and N2 is transferred to the digit lines D and D bars. Read to. When rewriting the stored information, the complementary voltage opposite to the stored voltage at the terminals N1 and N2 is applied to the digit lines D and D bar while the N-channel transistor is conducting, and the stored voltage is inverted. As described above, since the memory cell is composed of the flip-flop, unlike the dynamic memory, the stored information can be stably accumulated.

Generally, an SRAM is formed by arranging the memory cells of FIG. 7 in a matrix in the row and column directions. FIG. 8 shows a circuit configuration in which two cells in the row direction and two cells in the column direction are extracted from the memory cell group arranged in a matrix. 9 shows that after writing "1" information (high level) in the memory cell 1 of FIG. 8 for a certain period of time,
The signal waveform of the operation of rewriting to "0" information (low level) is shown. At time t0, the voltage of the word line W1 is at low level, the storage terminal N1 of the memory cell 1 is "1", the storage terminal N2 is "0", the storage terminal N3 of the memory cell 2 is "0", and the storage terminal N4. Is "1", the storage terminal N5 of the memory cell 3 is "1", and the storage terminal N6 is "0". At this time, the N-channel transistors Q2, Q5, Q10 are rendered conductive, and the N-channel transistors Q1, Q3, Q4, Q6, Q7, Q8, Q9, Q
11, Q12 are in a non-conducting state. Also, normal SRA
In M, since the voltage of the digit line pair is clamped to the high level before the read and write operations, the voltage of the digit lines D1, D1 bar, D2 and D2 bar is at the high level.

Now, assume that writing is performed on the word line W1 at time t1 and further writing is changed on the same word line W1 at time t2. Word line W at time t1
1 becomes high level, the digit line D1 bar is set to low level between the time t1 and the time t2, and the digit line D1
When a high level is applied to the writing circuit 4 by the write circuit 4, the N-channel transistors Q3, Q4, Q7, and Q8 become conductive,
The memory terminal N1 of the memory cell 1 is inverted from "1" to "0", and the memory terminal N2 is inverted from "0" to "1". Further, since the storage terminal N3 storing "0" of the memory cell 2 and the digit line D2 are electrically connected, assuming that the time between the time t1 and the time t2 is sufficiently long, the voltage of the digit line D2 is at the high level (V
from dd) to low level (GND).
In the SRAM, the minimum value is specified with respect to the timing from the writing to the next reading or writing, but the maximum value is not specified, so that the non-selected digit line may drop from Vdd to 0V. Can happen.

It is assumed that information opposite to the information stored in the memory cell 1 is written at time t2. At this time, the voltage of the word line W1 is held at the high level, and the memory 1
Of the column selection signal YL1 to high level and the column selection signal YL2 to low level to make both N-channel transistors Q101 and Q102 conductive.
When both 103 and Q104 are made non-conductive and a high level is applied to the digit line D1 bar and a low level is applied to the digit line D1 from the write circuit 4, the storage terminal N1 of the memory 1 changes from "0" to "1" and the storage terminal N2. Is inverted from "1" to "0". Moreover, since the voltage of the digit line D1 is drastically lowered from the high level (Vdd) to the low level (GND), the voltage of the digit line D2 is equal to or lower than the voltage (-Δ1) due to the parasitic capacitance Cdd between the digit lines D1 and D2. ).

N-channel transistor Q of memory cell 3
When the threshold voltage of 11 is Vt, and the absolute value of the voltage of the digit line D2 at this time | -Δ1 | is larger than Vt (| -Δ1 |> Vt), the N-channel transistor Q11 becomes conductive and Q11 The storage information of the storage terminal N5 connected to is inverted from "1" to "0",
The channel transistor Q10 becomes non-conductive, and the voltage of the storage terminal N6 rises from low level to high level due to the current supplied through the resistor R6. Therefore, after that, the problem that the stored information in the memory cell 3 cannot be correctly read occurs.

In order to solve the above problem, Japanese Patent Laid-Open No. 62-62
-9593, a new SRA as shown in FIG.
M cells have been proposed. The static memory cell of FIG. 10 has the same flip-flop as that of the conventional memory cell, but uses two types of word lines, a row word line and a column word line which is not available in the conventional example. Is high level and the column word line is low level, the read or write is performed to the target memory cell. FIG. 11 shows a driving circuit for the column word line W4, which includes an N-channel transistor Q2.
1, Q22 are used for setting the high level of the column word line W4, and the N-channel transistor Q23 is used for setting the voltage of the column word line W4 to the low level.
The clock signal Φ1 applied to the gate of the N-channel transistor Q23 becomes low level when the column word line W4 is not selected, and the N-channel transistor Q23 becomes non-conductive. Therefore, N-channel transistors Q21 and Q22
If the threshold voltage of Vt is Vt, the word line W
The voltage of 4 is clamped at 2Vt. On the other hand, when the column word line W4 is selected, the clock signal Φ1 becomes high level, the N-channel transistor Q23 becomes conductive, and the voltage of the column word line becomes the GND voltage.

In the memory cell of FIG. 10, if the voltage of the row word line W3 is set to the high level W3 (H) and the voltage of the column word line W4 is set to the low level, the N-channel transistors Q3 and Q4.
Both become conductive, the memory cell is brought into a selected state, and reading and writing are performed as in the conventional memory cell.
Next, while keeping the voltage of the row word line W3 at the high level, the voltage of the column word line W4 is set to the high level W4 (H), and the threshold voltage of the N-channel transistors Q1, Q2, Q3, Q4 is set to Vt. W3 (H) -V
If the relationship of t <W4 (H) is satisfied, the N-channel transistors Q3 and Q4 are rendered non-conductive and the memory cell is in a non-selected state. Therefore, unlike a conventional memory cell, a memory cell connected to only a selected row word line or column word line is in a non-selected state, and neither reading nor writing is performed. Therefore, malfunction due to the coupling capacitance between the digit lines due to the reading of the adjacent memory cell can be prevented.

[0011]

In the conventional SRAM shown in FIGS. 10 and 11, three N-channel transistors are required for each digit line pair, and a circuit for generating a selection signal Φ1 for a column word line is required. Will be needed. Furthermore, the column word line must be newly provided, and for these reasons, the chip area increases considerably.

Therefore, it is an object of the present invention to use a conventional SRAM.
It is an object of the present invention to provide an SRAM that suppresses an increase in chip area by adding a minimum number of elements to prevent malfunction due to coupling capacitance between digit lines and operates stably.

[0013]

Therefore, a static random access memory according to the present invention includes first and second N-channel transistors having drains and gates cross-connected to each other and sources both connected to a ground potential.
A load current element that supplies a holding current to the drains of the first and second N-channel transistors, a gate connected to the word line, a source connected to the drain of the first N-channel transistor, and a drain connected to the first A third N-channel transistor connected to each digit line,
The gate is connected to the word line, the source is connected to the drain of the second N-channel transistor, and the drain is connected to the second
A fourth N-channel transistor connected to each of the digit lines and a source respectively connected to the first and second
Second and sixth N-channel transistors each having a drain connected to a first bias voltage source, the gates of the fifth and sixth N-channel transistors being the fifth and the sixth N-channel transistors. It is characterized in that it is connected to a second positive bias voltage source lower than the threshold voltage of the sixth N-channel transistor.

[0014]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of a static random access memory according to the first embodiment of the present invention. N-channel transistors Q1, Q2, Q3, Q shown in FIG.
4, the memory cell 1 including the high resistance elements R1 and R2, the storage terminals N1 and N2, and the digit lines D and D bar has the same circuit configuration as the conventional example shown in FIG. In this embodiment, the column word line used in the conventional example is not used and N
It has a basic circuit configuration in which the sources of the channel transistors Q1 and Q2 are GND (ground). N-channel transistors Q1 and Q2 and high resistance elements R1 and R2 form a flip-flop circuit, and memory information is stored in storage terminals N1 and N2 as complementary signals. Further, by N-channel transistors Q31 and Q32 whose drains are both connected to the terminal 5 which receives the first bias voltage and whose sources are respectively connected to the digit lines D and D bar,
It prevents the digit lines D and D bar from swinging deeply in the negative. The second bias voltage source 7 is Vd as shown in FIG.
d is formed by resistance division, and an N-channel transistor Q3
1, a positive voltage lower than the threshold voltage of Q32 is supplied from the terminal 6 to the gates of Q31 and Q32. Although the terminal 5 receives the positive voltage from the first bias voltage source in FIG. 1, it may receive the bias voltage from Vdd or the second bias voltage source or GND, or the SRAM chip separately from these voltage sources. The bias voltage may be received from an overlying voltage source.

Next, the write operation of the present invention will be described with reference to FIG. 2 in which two memory cells 1 of FIG. 1 are arranged in a matrix in a row direction and two memory cells 1 in a column direction, and FIG. Explain. Now, at time t0, word lines W1 and W
The voltages of 2 are both low level, the storage terminal N1 of the memory cell 1 is "1", the storage terminal N2 is "0", the storage terminal N3 of the memory cell 2 is "0", and the storage terminal N5 of the memory cell 3 is "1" is stored in the storage terminal N6 and "0" is stored in the storage terminal N6. At this time, the N-channel transistors Q2, Q5, Q10 are rendered conductive, and the N-channel transistors Q1, Q3, Q4, Q6, Q7, Q8, Q9, Q1.
1 and Q12 are in a non-conducting state. In addition, normal SRAM
Then, as described above, the digit lines D1 and D1 bar,
The voltage of D2 and D2 bar is kept at high level.

As described in the operation of the conventional example, it is assumed that the word line W1 is written at time t1 and the same word line W1 is changed at time t2. At time t1, the voltage of the word line W1 becomes high level, the column selection signal YL1 of the memory cell 1 is made high level between time t1 and time t2 to make both the N-channel transistors Q101 and Q102 conductive, and the digit line D1 bar. When a low level is applied to the digit line D1 and a high level is applied to the digit line D1 by the write circuit 4, the N-channel transistors Q3, Q4, Q7 and Q8 are rendered conductive, and the storage terminal N1 of the memory cell 1 is stored from "1" to "0". The terminal N2 is inverted from "0" to "1". In addition, the storage terminal N3 storing "0" of the memory cell 2 and the digit line D
2 becomes conductive, the voltage of the digit line D2 is at a high level (Vdd) if the time t1 and the time t2 are sufficiently long.
To low level (GND).

It is assumed that information opposite to the information stored in the memory cell 1 is written at time t2. At this time, the voltage of the word line W1 is maintained at the high level, and the memory 1
When the column selection signal YL1 is set to a high level to make Q101 and Q102 both conductive and a high level is applied to the digit line D1 bar and a low level is applied to the digit line D1 by the write circuit 4, the storage terminal N1 of the memory 1 is set to "0".
To "1", the storage terminal N2 is inverted from "1" to "0". In addition, the voltage of the digit line D1 is high level (Vd
Since the voltage is drastically lowered from d) to the low level (GND), the voltage of the digit line D2 is reduced to a voltage (-Δ2) below GND due to the parasitic capacitance Cdd between the digit lines D1 and D2. Here, the threshold voltage of the N-channel transistors Q33 and Q34 is Vt, and the voltage of the terminal 6 that receives the output from the second bias voltage source is Va.
Then, Δ2 = | Va−Vt | ... (1). Therefore, if the threshold voltages of the N-channel transistor Q11 and the N-channel transistor Q33 are the same, the threshold voltage of the N-channel transistor Q11 is larger than Δ2, and therefore the digit line D
When the voltage of 2 increases in the negative direction, the N-channel transistor Q33 first conducts and a current flows from the terminal 5 receiving the first bias voltage to the digit line D2 via the N-channel transistor Q33, and the digit line D2 The voltage is clamped at -Δ2 and Q11 does not conduct. Therefore, the problem that the storage terminal N5 is inverted from "1" to "0" to cause a malfunction does not occur.

Next, a second embodiment of the present invention will be described with reference to FIGS.

With the recent increase in the size of SRAM, a redundant memory cell array 42 is provided in advance near the memory cell array 41 as shown in FIG. 4, and a defective memory cell is replaced with a redundant memory cell to replace the defective memory cell. A method for relieving a chip has been widely put into practical use. In this case, the GND wiring supplied to the redundant memory cell is connected to the redundant memory cell via the point A to the point B, but the GND wiring supplied to the peripheral circuit 43 in order to reduce the chip area of the entire memory chip. A layout is also performed in which the line is shared and the point C is further extended from the point B to connect to the peripheral circuit. In this case, let R be the wiring impedance at points A and B,
Assuming that the current flowing between points B is I, the voltage at point B rises by I · R above point A. When R = 10Ω and I = 30 mA, the voltage rises to 0.3 V, resulting in raising the voltage of the spare word line forming the redundant memory cell by that amount. Therefore, when the spare digit line swings to a negative voltage, the N-channel transistor connected to the spare word line is likely to become conductive, and the information in the non-selected redundant memory cell is inverted to cause a malfunction. .

In the present embodiment, as shown in FIG. 5, the circuit configuration of the redundant memory cell 51 is the same as that of the conventional circuit, but the sources are connected to the spare digit lines DX and DX bar respectively, and the drains are both connected to the first digit line. N-channel transistor Q3 connected to the terminal 5 for receiving the bias voltage of and its gate both connected to the terminal 6 for receiving the second bias voltage.
1 and Q32 are newly added. The voltage of terminal 6 is set to Va and N-channel transistors Q31 and Q32
If the threshold voltage of Vt is set to Vt, even if the spare digit lines DX and DX bar try to swing strongly negatively,
The voltage of the spare digit line is clamped to-| Vt-Va |, and N-channel transistors Q3 and Q4 do not conduct. In addition, N-channel transistors Q31 and Q32
Gate voltage Va is set lower than the threshold voltage Vt of N-channel transistors Q31 and Q32, and N-channel transistors Q31 and Q32 do not conduct during normal operation. Does not occur. According to the present invention, even if the power supply for the redundant memory cell array and the power supply for other peripheral circuits are made common in order to reduce the area of the entire memory chip, the problem that the stored information of the non-selected memory cells is inverted does not occur, so that it is stable. It is possible to read and write data as well as to reduce the chip area.

Next, a third embodiment of the present invention will be described with reference to FIG. The circuit configuration of the memory cell 1 is similar to that of the first embodiment, and the digit lines D and D bar are clamped by the diodes D1 and D2. The diodes D1 and D2 use the source diffusion layer of the P-channel transistor for the anode and the N-well diffusion layer for the cathode,
It can be easily formed on the same substrate as the memory cell without adding an additional step to the CMOS process.

The anode voltage of the diodes D1 and D2 is biased to a voltage (about 0.2V to 0.5V) lower than the forward voltage of D1 and D2 (about 0.7V). Now, the forward voltage VF of the diodes D1 and D2
Is 0.7V and the voltage obtained by dividing Vdd by the resistors r1 and r2 is 0.4V, even if the voltage on the digit lines D and D bar becomes negative, the voltage is 0.4V-0.7V due to the diodes D1 and D2. = -0.3V clamps the voltage on digit lines D and D-bar. Since the forward voltage VF of the diodes D1 and D2 is stable regardless of the manufacturing process, the digit lines D and D bar can be clamped at a stable voltage. Also, the diode D
Since 1 and D2 have a large current driving capability per unit area, the digit lines D and D bar can be clamped with a small area, and the area of the memory chip can be reduced.

[0024]

As described above, in the static random access memory according to the present invention, even if the non-selected digit line changes from 0V to a negative voltage due to the coupling capacitance between the digit lines, the stored information of the non-selected memory cell is stored. Is not inverted, so that stable read and write operations can be performed. Further, the number of elements required for each digit line pair is reduced from three elements to two elements as compared with the conventional example, and the clock generation circuit for driving the column word lines is not required. Further, since the column word line is unnecessary, the chip area can be significantly reduced.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a memory cell array in which two memory cells shown in FIG. 1 are arranged in each of a row direction and a column direction.

FIG. 3 is a signal waveform diagram in a write operation of the memory cell array shown in FIG.

FIG. 4 is a schematic diagram of an SRAM chip showing a second embodiment of the present invention.

FIG. 5 is a circuit diagram showing a second embodiment of the present invention.

FIG. 6 is a circuit diagram showing a third embodiment of the present invention.

FIG. 7 is a memory cell of a conventional basic SRAM.

8 is a memory cell array in which two memory cells shown in FIG. 7 are arranged in each of a row direction and a column direction.

9 is a signal waveform diagram in a write operation of the memory cell array shown in FIG.

FIG. 10 is a circuit diagram of a conventional SRAM in which malfunction due to coupling capacitance between digit lines is improved.

11 is a drive circuit diagram for driving a column word line of the SRAM shown in FIG.

[Explanation of symbols]

1 to 3 memory cells 4 write circuit 5 terminal for receiving first bias voltage 6 terminal for receiving second bias voltage 7 second bias voltage source 41 memory cell array 42 redundant memory cell array 43 peripheral circuit 44 word driver 45 word decoder 46 Column driver 47 Column decoder 51 Redundant memory cell A, B, C GND wiring connection point W, W1, W2, W3 Word line WX Spare word line W4 Column word line N1 to N6 Storage terminals Q1 to Q12, Q21 to Q23, Q31 to Q34, Q1
01-Q104 N-channel transistor D1, D2 Diode R1-R6 High resistance element r1, r2 Resistance element Cdd Coupling capacitance Φ1 Clock signal YL1, YL2 Column selection signal

Claims (3)

[Claims] 1. A first and second N in which drains and gates are cross-connected to each other and sources are both connected to a ground potential.
A channel transistor and the first and second N
A load current element that supplies a holding current to the drain of the channel transistor, and a third gate whose gate is connected to the word line, whose source is connected to the drain of the first N-channel transistor, and whose drain is connected to the first digit line. N
A channel transistor, a fourth N-channel transistor having a gate connected to the word line, a source connected to a drain of the second N-channel transistor and a drain connected to a second digit line, and a source respectively And fifth and sixth N-channel transistors having drains connected to a first bias voltage source and drains connected to the first and second digit lines, and gates of the fifth and sixth N-channel transistors. A static random access memory, wherein the static random access memory is connected to a second positive bias voltage source which is lower than the threshold voltages of the fifth and sixth N-channel transistors. 2. A static random access memory having a redundant memory cell, a spare digit line and a spare word line which are replaced when a defect occurs in the memory cell or digit line or word line, wherein the spare memory cells are mutually drained. A first and a second N-channel transistor whose gates are cross-connected and whose sources are both connected to the ground potential; and a load current element which supplies a holding current to the drains of the first and the second N-channel transistors, A third N-channel transistor having a gate connected to the spare word line, a source connected to the drain of the first N-channel transistor, and a drain connected to the first spare digit line, and a gate connected to the spare word line. Connected to the source of the second N
A fourth N-channel transistor connected to the drain of the channel transistor and connected to the second spare digit line, and a source connected to the first and second spare digit lines, respectively, and a drain to the first spare digit line. Fifth and sixth N-channel transistors connected to a bias voltage source of
Static random access memory characterized in that the gate of the N-channel transistor is connected to a second positive bias voltage source which is lower than the threshold voltages of the fifth and sixth N-channel transistors. 3. A holding current is supplied to the drains of the first and second N-channel transistors and the drains of the first and second N-channel transistors whose drains and gates are cross-connected to each other and whose sources are both connected to the ground potential. Load current element, a third N-channel transistor having a gate connected to the word line, a source connected to the drain of the first N-channel transistor and a drain connected to the first digit line, and a gate connected to the word line. A fourth N-channel transistor having a source connected to the drain of the second N-channel transistor and a drain connected to the second digit line, and a first N-channel transistor having cathodes connected to the first and second digit lines, respectively. A second diode, wherein the anodes of the first and second diodes are connected to the first diode. And a static random access memory connected to a positive bias voltage source lower than the forward voltage between the anode and the cathode of the second diode.