JPH08316633A - Method for manufacturing thin-film multilayer wiring board - Google Patents

Abstract

PURPOSE: To improve an etching method and the selectivity of an etching material by using a metal film as an etching mask and at the same time improving lamination accuracy and working efficiency by a collective etching of a plurality of layers. CONSTITUTION: A thin-film multilayer interconnection 7 is formed on a pad 3 for leading wire formed on a ceramic substrate 2. When forming the wire, organic insulation films 6 and 8 are left on an airtight sealing metallization pattern 4. After laminating a wiring pattern, a nickel film 9 for LSI-connecting pad at the uppermost layer which is a substrate-constituting material is used as an etching mask, thus collectively eliminating the organic insulation films 6 and 8.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a thin film multilayer wiring board in which a thin film multilayer wiring consisting of an organic insulating film and a metal wiring pattern is formed on a ceramic substrate having a sintered metallization.

[0002]

2. Description of the Related Art In a multi-layer wiring electronic component for high-density packaging, which has a thin-film multi-layer wiring consisting of an organic insulating film and a metal wiring pattern on a substrate, thin-film multi-layer wiring is formed by etching each organic insulating film and metal wiring film It is performed by coating with a material, patterning, and then selectively etching.

Conventionally, an organic film such as a photoresist is used as the above-mentioned etching mask material, and generally a method of sequentially etching each layer is adopted.
As a related conventional technique of this type, for example, there is a method of manufacturing a multilayer wiring substrate in which a surface of a ceramic substrate with through holes is flattened, which is described in Japanese Patent Laid-Open No. 4-98893.

[0004]

In the above-mentioned prior art, since the photoresist, which is an organic film, is used as an etching mask when etching the organic insulating film and the metal wiring film forming the thin-film multi-layered wiring, the dry etching resistance is used. In addition, there is a problem in that the property is small, and in wet etching, selection of a material for obtaining etching resistance and control of the film thickness are restricted.

Further, since the formation and processing of the organic insulating film and the metal wiring film constituting the thin film multi-layered wiring are sequentially performed in each layer, in addition to the etching resistance of the etching mask, the lower layer film is damaged by the work to be etched. With less
Strict control of the alignment accuracy of each layer pattern is required.

The object of the present invention is to improve the etching method and the selectivity of the etching material by using a metal film as an etching mask, and to improve the stacking accuracy and work efficiency by batch etching of a plurality of layers. It is to provide a method for manufacturing a substrate.

[0007]

In order to achieve the above object, the present invention provides a method for producing a thin film multilayer wiring board, wherein thin film multilayer wiring comprising an organic insulating film and a metal wiring pattern is formed on the substrate. When the insulating film is etched, the region excluding the organic insulating film is masked with a metal film.

Further, the metal film used as the etching mask is a metal film forming a part of the multilayer wiring.

Further, the etching is a batch etching of organic insulating films made of different materials.

[0010]

In the present invention, the etching method and the selectivity of the etching material are improved by using a metal film having high etching resistance as the etching mask. In addition, it enables batch etching by using a metal film with high etching resistance as an etching mask under the etching conditions that can simultaneously etch layers to be etched composed of multiple types of materials, and it is possible to combine layers of layers to be etched. It enables improvement of accuracy and work efficiency. Furthermore, when the metal wiring film forming the thin-film multilayer wiring can be used as an etching mask, it is not necessary to newly form the metal film.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be specifically described below with reference to the drawings. FIG. 1 is a cross-sectional view in an intermediate step of the thin film multilayer wiring board according to this embodiment. The substrate of the present embodiment is a ceramic substrate 2 having a sintered metallization 1,
After the wiring drawing pad 3, the hermetically sealed metallized pattern 4 and the external connection pad 5 are formed by the printed pattern of the tungsten paste, the thin film multilayer wiring is formed,
Using the nickel film 9 for LSI connection pad as an etching mask, the organic insulating layers 6 and 8 on the hermetically sealed metallized pattern 4 are collectively removed. As a result of such collective removal, the stacking accuracy of the stacking end face 18 can be improved.

The embodiments of the present invention will be described in detail below.
FIG. 2 shows a ceramic substrate 2 having a sintered metallization (copper, tungsten, etc.) 1 which is an initial material of this embodiment.
Indicates. This substrate comprises a wiring drawing pad 3 formed by a printed pattern of a tungsten paste on a ceramic substrate 2, a hermetically sealed metallized pattern 4 and an external connection pad 5, and a nickel plating layer is formed on the tungsten printed pattern. Are formed.

During formation of the thin film multilayer wiring on the ceramic substrate 2 of FIG. 2, it is necessary to protect the external connection pads 5 on the back surface of the substrate where the thin film multilayer wiring is not formed. That is, in FIG. 3, first, a PIQ (registered trademark of Hitachi Chemical Co., Ltd.) film 10 as a protective film using an organic insulating film on the back surface of the ceramic substrate 2 is heat-treated at 400 ° C. and then has a thickness of about 8 μm. To form. Furthermore, a Photo-PIQ (registered trademark of the same company) film 11 that is a photosensitive organic insulating film
Is similarly heat-treated at 400 ° C. and then formed to have a thickness of about 24 μm.

In FIG. 3, Photo-P is provided on the back surface of the substrate.
The purpose of forming the IQ film 11 is to prevent the PIQ film 10, which is the protective film on the back surface, from being etched by the etching liquid when forming the pattern of the PIQ, which is the organic insulating film of the thin film multilayer wiring on the front surface.

Next, as shown in FIG. 4, a PIQ film, which is an organic insulating film in the thin film multi-layer wiring, is formed on the surface of the substrate at 400 ° C.
After the heat treatment, the film is formed to have a thickness of 13 μm, and etching is performed using the negative resist film 12 as an etching mask to form a PIQ insulating layer 6 having a contact hole with the wiring drawing pad 3. For etching the PIQ insulating layer 6, a hydrazine solution heated to about 30 ° C. is used. At this time, the PIQ insulating layer 6 on the hermetically sealed metallized pattern 4 to be finally exposed on the surface of the substrate is not removed but is left as it is collectively removed as described later. This is because the stacking accuracy of the stacking end faces (18 in FIG. 1) is more improved when the batchwise removal is performed than when the layers are sequentially removed. After etching, the negative resist film 12 is
It is removed by a resist stripping solution treatment.

Next, as shown in FIG. 5, the P formed previously is formed.
A is formed on the entire surface of the IQ insulating layer 6 by a sputtering method.
The positive resist film 1 is formed by forming an I film with a thickness of 4 μm.
Etching is performed using 3 as an etching mask, and Al
The wiring pattern 7 is formed. For etching the Al film,
72.3% phosphoric acid: 9.5% acetic acid: 2.0% nitric acid: water =
An etching solution having a composition of 15: 3: 1: 1 is used. At this time, the Al film on the hermetically sealed metallized pattern 4 is also completely removed, and the PIQ insulating layer 6 is exposed. After etching, the positive resist film 13 is removed by a resist stripping solution treatment.

Next, referring to FIG. 6, Ph on the substrate of FIG.
After the photo-PIQ is heat-treated at 85 ° C., a film is formed to have a thickness of 16 μm, and a Photo-PIQ insulating layer 8 having a contact hole is formed by an exposure / development process. Also at this time, similarly to the PIQ insulating layer 6 described above, the PIQ insulating layer 8 on the hermetically sealed metallized pattern 4 is not removed but left. After forming contact holes, 400
An insulating layer of about 8 μm is formed by heat treatment at a temperature of C.

Formation of the aforementioned Al wiring pattern 7 and Ph
The formation of the auto-PIQ insulating layer 8 is sequentially repeated to form a thin film multilayer wiring. Then, as shown in FIG. 7, a nickel film 9 for LSI connection pad is formed on the uppermost layer. The nickel film 9 for LSI connection pad has a thickness of 0.0
It is composed of a laminated film of a chromium film of 5 μm and a nickel film of 0.5 μm, and a chromium film and a nickel film are successively formed by a sputtering method.

In FIG. 7, the chromium film and the nickel film formed on the entire surface of the substrate by the sputtering method are etched by using the positive resist film 14 as an etching mask. The etching solution having the composition used for etching the Al wiring is used for etching the nickel film. Also,
Aluminum chloride hexahydrate: 72 for etching chromium film
% Phosphoric acid: water = 3500 g: 7 liter: 6 liter An etching solution having a composition is used. FIG. 8 is a diagram in which the nickel and chromium films on the hermetically sealed metallized pattern 4 are removed by etching.

In FIG. 8, the underlying PIQ insulating layer 6 and the Photo-P are used as an etching mask with the nickel film 9 for LSI connection pad which is a constituent material of the thin film multilayer wiring.
The IQ insulating layer 8 is collectively removed by exposing it to oxygen plasma (dry etching). At this time, the positive resist film 14 is also removed at the same time. Using this nickel film 9 for LSI connection pad as an etching mask, the underlying PIQ
The diagram after the insulating layers 6 and 8 are collectively removed is FIG. 1 described above.

Next, in FIG. 1, in order to form an LSI connection pad, as shown in FIG. 9, a negative resist film 1 is formed.
5 is formed. Further, a negative resist film 16 is formed on the hermetically sealed metallized pattern 4 so that the hermetically sealed metallized pattern 4 is not corroded by the etching solution.

In FIG. 9, the nickel film 9 for LSI connection pad is used with the negative resist film 15 as an etching mask.
Is etched (for etching, an etching solution having the same composition as described above is used), and as shown in FIG.
The I connection pad 17 is formed.

In FIG. 10, after the LSI connection pad 17 is formed, the PIQ film 10 and the photo film which are the back surface protective film are formed.
After removing the o-PIQ film 11 by exposing it to oxygen plasma, the negative resist film 1 is processed by a resist stripping solution treatment.
5 and 16 are removed, and as a result, a thin film multilayer wiring board as shown in FIG. 11 is completed.

FIG. 12 shows an electronic component using the substrate of the present invention. That is, an LSI chip is mounted on the LSI connection pad 17 via a solder bump, and the ceramic package and the hermetically sealed metallized pattern 4 are connected by solder, whereby the electronic component is completed.

The above-mentioned PIQ insulating layer 6 and Photo
Each of the o-PIQ insulating layers 8 is soluble in a hydrazine solution, but since the etching rates of the insulating layers 6 and 8 are significantly different, wet etching using a resist as an etching mask ensures that the stacking accuracy of the end faces is secured and the layers are collectively processed. Since it is difficult to remove, dry etching using a metal film is adopted in the present invention.

[0026]

As described above, according to the present invention, since the metal film is used as the etching mask, the etching resistance of both the dry etching and the wet etching is improved, and the restriction of the etching conditions is greatly reduced. It

Further, since a metal film having a high etching resistance is selected with respect to the etching conditions capable of simultaneously etching the lower layer film made of a plurality of materials, it is not necessary to consider the damage to the base and the matching accuracy. .

Further, when the metal film forming the thin film multi-layer wiring can be used as an etching mask for the lower layer film, it is not necessary to form the metal film again.

[Brief description of drawings]

FIG. 1 is a cross-sectional view in a manufacturing process of a thin-film multilayer wiring board according to this embodiment.

FIG. 2 is a cross-sectional view of a ceramic substrate having a sintered metallization which is an initial material of this example.

[Fig. 3] PIQ film and Photo on the back surface of the ceramic substrate
FIG. 6 is a diagram in which a PIQ film is formed.

FIG. 4 is a diagram in which a PIQ insulating layer and a negative resist film are formed on the surface of a ceramic substrate.

FIG. 5 is a diagram in which an Al wiring pattern is formed on a PIQ insulating layer.

FIG. 6 is a view in which a Photo-PIQ insulating layer having a contact hole is formed on the PIQ insulating layer.

FIG. 7 is a diagram in which a nickel film for an LSI connection pad is formed on the uppermost layer.

FIG. 8 is a view in which the nickel and chromium films on the hermetically sealed metallized pattern are removed by etching.

FIG. 9 is a diagram for forming an LSI connection pad.

FIG. 10 is a diagram in which an LSI connection pad is formed.

FIG. 11 is a completed sectional view of a thin-film multilayer wiring board manufactured by the manufacturing method of the present invention.

FIG. 12 shows an electronic component using the thin film multilayer wiring board of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Sintered metallization 2 Ceramic substrate 3 Wiring extraction pad 4 Hermetically sealed metallization pattern 5 External connection pad 6 PIQ insulating layer 7 Al wiring pattern 8 Photo-PIQ insulating layer 9 Nickel film for LSI connection pad 10 PIQ film 11 Photo- PIQ film 12, 15, 16 Negative resist film 13, 14 Positive resist film 17 LSI connection pad 18 End surface

Claims (3)

[Claims] 1. A method of manufacturing a thin-film multilayer wiring board, wherein a thin-film multilayer wiring comprising an organic insulating film and a metal wiring pattern is formed on a substrate, and when etching the organic insulating film, a region excluding the organic insulating film is metal. A method for manufacturing a thin-film multilayer wiring board, which comprises masking with a film. 2. The method of manufacturing a thin-film multilayer wiring board according to claim 1, wherein the metal film used as the etching mask is a metal film forming a part of the multilayer wiring. 3. The method of manufacturing a thin-film multilayer wiring board according to claim 1, wherein the etching is batch etching of organic insulating films made of different laminated materials.