JPH08316486A - Thin-film semiconductor element - Google Patents

Abstract

PURPOSE: To obtain a thin-film semiconductor element of a structure, wherein a drain current in an off-state of the element is reduced and at the same time, an even reduction in an off-state current is possible in case of a large quantity production of the element. CONSTITUTION: Source and drain regions 2 and 3 of a thin-film transistor respectively have a laminated structure, wherein a doped amorphous semiconductor layer 2a consisting of a high-resistance a-Si film is formed in the side of the upper layer of the region 2 and a doped polycrystalline semiconductor layer 2b consisting of a low-resistance impurity-doped a-Si film is formed in the side of the lower layer of the region 2, and a laminated structure, wherein a doped amorphous semiconductor layer 3a consisting of a high-resistance a-Si film is formed in the side of the upper layer of the region 3 and a doped polycrystalline semiconductor layer 3b consisting of a low-resistance doped a-Si film is formed in the side of the lower layer of the region 3. The thickness of the layers 2a and 3a is formed in such a way as to become thicker than that of a channel of the transistor.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film semiconductor device, and more particularly to a device structure for reducing off current in a thin film semiconductor device such as a thin film transistor which constitutes a driving circuit of a liquid crystal display or the like.

[0002]

2. Description of the Related Art For example, in a display device such as a liquid crystal display, a driving circuit for driving the pixel is integrally formed on a glass substrate on which display pixels are formed to reduce the size and performance of the device. Technology development is under way. In this case, a polycrystalline silicon thin film transistor (hereinafter referred to as poly-SiTFT) is generally used as a switching element forming a drive circuit. This poly-SiTF
T has a structure for forming an element active region in a polycrystalline silicon thin film, and is therefore suitable for forming on a glass substrate or the like.

However, the conventional poly-Si TFT has a problem that the off current during the off operation is large. This is because when the TFT is turned off, a strong electric field is applied between the channel and the drain, and as a result, a field emission current is generated. Therefore, in order to reduce the off-current of the TFT, some structures have been conventionally proposed. As an example thereof, there is one in which the structure of the drain region of the TFT is a so-called LDD (Lightly Doped Drain) structure. FIG. 17 is a sectional structural view of a TFT having this LDD structure. Generally, the TFT is formed on an insulating substrate 41, and includes a gate electrode 46, a gate insulating layer 45, and a pair of source / drain regions 42, 4.
It consists of three. In each of the source / drain regions 42 and 43, low-concentration impurity regions 42a and 43a are formed on the channel formation region 44 side, and the high-concentration impurity region 4 is further separated from the channel formation region 44.
It has a so-called LDD structure in which 2b and 43b are formed. In one drain region 42 of this LDD structure, a high-concentration impurity region 42b, that is, a low-concentration, high-resistance impurity region 42a is interposed between the low-resistance impurity region 42b and the channel 44a. The generation of a strong electric field is relaxed. This reduces the generation of field emission current.

Now, the manufacturing process of the TFT having the LDD structure shown in FIG. 17 will be described. First, as shown in FIG. 18, a channel layer 50 made of polycrystalline silicon is formed on an insulating substrate 41. Furthermore, on its surface,
A gate insulating layer material and a gate electrode material are formed and patterned to form a gate insulating layer 45 and a gate electrode 46.

Next, as shown in FIG. 19, the gate electrode 4
6 is used as a mask, high-concentration impurity 51 is ion-implanted,
High concentration impurity regions 42c and 43c in the channel layer 50
To form.

Further, as shown in FIG. 20, the gate insulating layer 45 and the gate electrode 46 are side-etched to reduce the width in the gate length direction. Further, as shown in FIG. 21, low-concentration impurity 52 is ion-implanted into the channel layer 50 using the side-etched gate electrode 46 as a mask to set the low-concentration impurity regions 42a and 43a to a predetermined high concentration. The high concentration impurity regions 42b and 43b thus formed are formed, and the source / drain regions 42 and 43 of the LDD structure are formed.

Further, as shown in FIG. 22, after covering the entire surface with a protective insulating layer 47, contact holes are formed on the high-concentration impurity regions 42b and 43b of the source / drain regions, and electrode layers 48 and 48 are further formed. Connecting. Through these steps, a TFT having an LDD structure is manufactured.

Further, as another structure for reducing the conventional off current, a TFT using an offset structure has been proposed. FIG. 23 shows a T having this offset structure.
It is a section construction drawing of FT. In this TFT, a pair of source / drain regions 42 and 43 are formed in a positional relationship offset from the gate electrode 46 in the gate length direction.
For this reason, generation of a strong electric field at the time of off is relaxed in the offset portion near the drain region, and the off current is reduced.

[0009]

In a switching element for a liquid crystal display, if the off-current between the elements becomes non-uniform, the displayed image becomes non-uniform. For this reason, in many TFTs used in a liquid crystal display, it is necessary to control the OFF current between the respective elements to be uniform. Therefore, in the TFT to which the conventional LDD structure is applied, it is necessary to uniformly form the widths of the low-concentration impurity regions 42a and 43a in the submicron order. However, as described above, the low concentration impurity regions 42a, 4a
The width of 3a is defined by the side etching amounts of the gate insulating layer 45 and the gate electrode 46. Then, for example, a large number of Ts formed on a substrate having a large area of 10 cm square or more.
It is difficult to uniformly side-etch the gate electrode 46 and the gate insulating layer 45 with respect to the FT, which makes it difficult to improve the quality of a displayed image. Also in the TFT having the offset structure, similarly, it is necessary to form the offset width uniformly in the submicron order. However, in the conventional offset structure, the offset portion cannot be formed in a self-aligned manner with respect to the gate electrode 46.
It was difficult to suppress the variation in the length of the offset portion between the FTs.

As described above, in the conventional off-current reduction structure, a large number of TFTs are formed on the same substrate, and each TFT is
There is a problem that it is difficult to uniformly control the off current of the.

An object of the present invention is to provide a thin film semiconductor device capable of reducing the off current and being suitable for uniformly controlling the reduction of the off current when a large number of them are formed.

[0012]

A thin-film semiconductor device according to the present invention comprises a semiconductor layer having a main surface formed on a substrate, and a pair of semiconductor layers formed in the semiconductor layer with a certain distance in the direction of the main surface of the semiconductor layer. A source / drain region between the pair of source / drain regions, and a channel forming region located near the main surface of the semiconductor layer where a channel is formed when a predetermined gate voltage is applied, and a channel of the semiconductor layer. A gate insulating layer formed on the formation region and a gate electrode formed on the gate insulating layer are provided, and at least one of the pair of source / drain regions is arranged in order from the main surface of the semiconductor layer in the thickness direction of the semiconductor layer. It has at least a first impurity region having a relatively high resistance and a second impurity region having a relatively low resistance that are stacked, and the thickness of the first impurity region is
It is characterized in that it is formed to be thicker than the thickness of the channel.

A thin film semiconductor device according to another aspect of the present invention includes a gate electrode formed on a substrate, a gate insulating layer formed on the gate electrode, and a semiconductor layer formed on the gate insulating layer. , A pair of source / drain regions formed in the semiconductor layer at regular intervals along the main surface of the semiconductor layer in contact with the gate insulating layer, and located near the main surface of the semiconductor layer between the pair of source / drain regions. A channel formation region in which a channel is formed when a predetermined gate voltage is applied, and at least one of the pair of source / drain regions is sequentially stacked from the main surface of the semiconductor layer in the thickness direction of the semiconductor layer. Further, it has at least a first impurity region having a relatively high resistance and a second impurity region having a relatively low resistance, and the thickness of the first impurity region is larger than the thickness of the channel. It is characterized in that it is formed so that.

In the thin film semiconductor device according to the limited aspect of the present invention, the first impurity region is formed of an amorphous semiconductor. A thin film semiconductor element according to a more limited aspect of the present invention is characterized in that the first impurity region is formed of amorphous silicon and the second impurity region is formed of polycrystalline silicon.

[0015]

FIG. 8 is a sectional structural view showing an operating state in the vicinity of the channel of the thin film semiconductor element during the off operation. FIG.
When the source / drain region is formed to have a laminated structure of the high-resistance first impurity region 2a and the low-resistance second impurity region 2b, the drain current flows through the low-resistance second impurity region 2b as shown in FIG. , The current flows so as to pass through the high-resistance first impurity region and the channel 4a.
Therefore, the high-resistance first impurity region 2a acts as a series resistance of the drain current, and as a result, the drain current decreases.

The resistance value of the first impurity region can be defined by the thickness of the first impurity region. Then, this thickness is controlled with high accuracy by adjusting, for example, ion doping conditions, as compared with the case where the width of the low concentration impurity region is controlled by using an etching process or the like as in the conventional LDD structure. can do. Therefore, when a large number of thin film semiconductor elements are formed on the same substrate, by uniformly controlling the thickness of the high-resistance impurity region of each element, an element having uniform off-current characteristics is formed over the entire device. be able to.

[0017]

Embodiments of the present invention will now be described in detail with reference to the drawings. First Embodiment FIG. 1 is a sectional structural view of a coplanar thin film transistor (TFT) according to a first embodiment of the present invention. As shown in FIG. 1, the TFT is formed on the surface of an insulating substrate 1 such as glass. The TFT has a pair of source / drain regions 2 and 3 formed in the channel layer 10.
And a gate insulating layer 5 and a gate electrode 6.

Each of the source / drain regions 2 and 3 has a two-layer structure in which the amorphous semiconductor doped layers 2a and 3a and the polycrystalline semiconductor doped layers 2b and 3b are laminated in the vertical direction of the paper. The amorphous semiconductor doped layers 2a and 3a formed on the upper layer side of the channel layer 10 are formed of a-Si, and the thickness of the channel layer 10 along the thickness direction is 50 to 50.
It is formed to 200 nm.

Further, the polycrystalline semiconductor doped layers 2b and 3b
Is formed under the amorphous semiconductor doped layers 2a and 3a and is made of impurity-doped polycrystalline silicon. For example, in the case of a p-channel TFT, B
(Boron) is doped at about 5 × 10 ¹⁹ to 2 × 10 ²¹ / cm ³ , and in the case of an n-channel TFT, P (phosphorus) is used.
Is about 5 × 10 ¹⁹ to 1 × 10 ²¹ / cm ³ , or As
(Arsenic) is doped at about 5 × 10 ¹⁹ to 1 × 10 ²¹ / cm ³ . As a result, the resistance is lower than that of the upper amorphous semiconductor doped layers 2a and 3a.

The gate insulating layer 5 is made of an insulating film such as SiO ₂ or SiN _x and has a thickness of 1000 to 30.
It is formed to a film thickness of 00Å. The gate electrode 6 is made of polycrystalline silicon or a metal such as Mo, Pa, or Ti, and has a film thickness of 3000 to 5000 Å.

The surface of the TFT is covered with a protective insulating film 7 such as SiO ₂ . Then, electrode layers 8 and 8 made of Al (aluminum) or the like are connected to the source / drain regions 2 and 3 through contact holes 9 and 9 formed in the protective insulating film 7. The electrode layers 8 and 8 preferably penetrate the amorphous semiconductor doped layers 2a and 3a and are directly connected to the low resistance polycrystalline semiconductor doped layers 2b and 3b. It may be connected to 3a.

Next, a manufacturing process of the thin film transistor having the above structure will be described with reference to FIGS. First, as shown in FIG. 2, a semiconductor layer is formed on an insulating substrate 1 such as glass and patterned into an island shape to form a channel layer 10. In a specific example of this step, LP
An a-Si film is formed to a thickness of 100 nm by using the CVD method. Next, an excimer laser beam 1 is applied to the surface of the a-Si film.
1 to melt and recrystallize the a-Si film,
A (polycrystalline Si) film is obtained. After that, patterning is performed using a normal photolithography process, and the channel layer 1 of polycrystalline Si is formed.
Form 0.

Next, as shown in FIG. 3, an insulating film and a metal film such as polycrystalline Si or Ti are sequentially formed and patterned by a photolithography process to form a gate insulating layer 5 and a gate electrode 6. In the specific example, the gate insulating film 5
Is a 100 nm-thick S film formed by using a sputtering method or the like.
It consists iO ₂ film, a gate electrode 6 is comprised of Ti layer formed by sputtering or the like.

Further, as shown in FIG. 4, using the patterned gate electrode 6 as a mask, impurities for imparting conductivity to the channel layer 10 are implanted by an ion doping method or the like, and then the surface side of the channel layer 10 is implanted. Amorphous semiconductor doped layers 2a and 3a are formed.

In a specific example, in the case of an n-channel TFT, phosphorus is added at a dose of 1 × 10 ¹⁶ / cm ² and an acceleration voltage of 30 keV.
Is implanted into the channel layer 10. By this ion doping, the channel layer 10 is amorphized to a depth of about 50 nm from the surface thereof, and a-Si amorphous semiconductor doped layers 2a and 3a are formed. Then, after that, thermal activation treatment is performed at 450 ° C. for 1 hour to activate the implanted impurities.

This step will be described with reference to the schematic sectional views of the channel layer shown in FIGS. Before the impurity ion doping, the channel layer 10 is a polycrystalline silicon film as shown in FIG. 6, but as shown in FIG. 7, after the impurity ion doping, for example, the surface region doped with phosphorus is not formed. Amorphous semiconductor doped layer 2a is formed by crystallization, and a polycrystalline silicon film as a starting film remains on the lower layer side. When the low temperature thermal activation process is performed in this state, the upper amorphous semiconductor-doped layer 2a maintains the amorphous state, and the lower polycrystalline semiconductor-doped layer 2b diffuses impurities and has low resistance. It becomes an area.

In the above-mentioned ion doping method, the thickness of the amorphous semiconductor doped layer 2a can be controlled by adjusting the acceleration voltage of impurity ions. For example,
When phosphorus is implanted at a dose of 1 × 10 ¹⁶ / cm ² as an impurity, 2 from the surface when the acceleration voltage is 10 keV.
Amorphized to the position of 0 nm, and the acceleration voltage is 50k.
When it is set to eV, about 80 nm from the surface is amorphized.

In the case of an n-channel TFT, As can be used as an impurity other than phosphorus, and in the case of a p-channel TFT, B (boron) can be used as an impurity.

Further, as shown in FIG. 5, after covering the entire surface of the substrate 1 with the protective insulating film 7, contact holes 9 and 9 are formed at predetermined positions on the source / drain regions 2 and 3. Further, an Al film is deposited on the entire surface and patterned to form the electrode layers 8 and 8. The contact hole 9 may be formed through the amorphous semiconductor doped layers 2a and 3a, or the amorphous semiconductor doped layer 2 may be formed.
It may be stopped at a position reaching the surfaces of a and 3a.

Through the above steps, the TFT having the source / drain regions 2 and 3 having the laminated structure of the amorphous semiconductor doped layer 2a and the polycrystalline semiconductor doped layer 2b is manufactured.
The source / drain regions 2 of the laminated structure shown in FIG.
The method of forming No. 3 is not limited to the above method, and may be formed using the following method. That is, the channel layer 10 is formed in advance with an a-Si film, and phosphorus is dosed in the channel layer 10 with the gate electrode 6 as a mask at a dose of 1 × 10 5.
Ion implantation is performed at ¹⁶ / cm ² and an acceleration voltage of 30 keV.
Thereafter, the surface of the amorphous channel layer 10 doped with phosphorus is irradiated with an ArF excimer laser beam for 250 to 300 m.
Irradiation is performed under the condition of j / cm ² to perform laser activation treatment. As a result, the entire amorphous channel layer 10 is recrystallized and the implanted impurities are activated.
As a result, a low resistance polycrystalline silicon film having impurities introduced therein is formed. Then, Si is implanted into the surface of the polycrystalline silicon film by ion implantation, and, for example, about 50
Amorphize to a depth of about nm. Even in this step, the upper side of the channel layer is doped with the amorphous semiconductor doped layers 2a, 3
It is possible to form the source / drain regions 2 and 3 having a laminated structure in which a and the lower layer side are the polycrystalline semiconductor doped layers 2b and 3b.

In the TFT having the above structure, the amorphous semiconductor doped layers 2a and 3a are formed by the gate electrode 6.
It is formed thicker than the thickness of the channel 4a formed on the surface of the channel layer 10 immediately below. Moreover, the resistance is higher than that of the lower polycrystalline semiconductor doped layers 2b and 3b. FIG. 8 is a cross-sectional structural view schematically showing a state of the above-mentioned thin film transistor during an off operation. TF
When T is in the off state, for example, when the gate voltage is −20 V and the voltage of 5 V is applied between the source / drain electrodes 2 and 3, the channel 4a has a thickness t _c , for example 100 Å, on the surface of the channel forming region 4. Formed to a degree. And
The off current flows along the path indicated by the arrow X. That is, in the source / drain region 2, after passing through the low-resistance polycrystalline semiconductor doped layer 2b and vertically crossing the high-resistance amorphous semiconductor doped layer 2a in the vicinity of the channel formation region 4, the current flows to the channel 4a. . This off current X
Since the path is configured to pass through the high-resistance amorphous semiconductor doped layer 2a, the resistance of the off-current path increases, and as a result, the off-current is reduced.

FIG. 9 is a characteristic diagram showing the drain current-gate voltage characteristics of a conventional thin film transistor (conventional example) having no off-current reduction structure and the above-described thin film transistor of the present invention (present invention). As is clear from FIG.
It can be seen that the TFT according to the present invention has a reduced drain current when off as compared with the conventional one.

Further, FIGS. 10 and 11 show the T of the present invention.
In the FT, the drain current-gate voltage characteristics when the film thickness of the amorphous semiconductor doped layers 2a and 3a are variously changed are shown. Here, A shows the case where the thickness t _X of the amorphous semiconductor doped layer is 50 nm, and B shows t _X = 2 similarly.
0 nm and C indicate the case of t _X = 80 nm. As can be seen from the characteristics shown in FIGS. 10 and 11, when the thickness of the amorphous semiconductor doped layers 2a and 3a is 20 nm or less,
Although the drain current at the time of off is not sufficiently reduced as compared with the conventional one, the off current is reduced when the thickness is 50 and 80 nm (A, C).

In particular, as shown in FIG. 11, when the thickness of the amorphous semiconductor doped layers 2a and 3a is 80 nm or more, the drain current at the time of off can be reduced, but the drain current at the time of on decreases. Resulting in.

As described above, the amorphous semiconductor doped layer 2
a and 3a are the source / drain regions 2 and 3 and the channel 4
It acts as a series resistor with respect to the drain current path passing through a. Then, while it has the effect of reducing the drain current when it is off, it acts to reduce the drain current when it is on. Therefore, by controlling the resistance values of the amorphous semiconductor doped layers 2a and 3a within an appropriate range, it is possible to adjust the drain current when the thin film transistor is on and off to an optimum level. In the thin film transistor according to the present invention, the amorphous semiconductor doped layer 2a,
The resistance value of 3a depends on its thickness. Therefore, according to various experimental results shown in FIGS. 10 and 11, the thickness of the amorphous semiconductor doped layer exceeds 20 nm and is 80 n or less.
It is preferably less than m. Furthermore, preferably 5
It is set to about 0 nm. The thickness of the amorphous semiconductor doped layer is determined by the X-ray diffraction peak ratio and cross-sectional TEM before and after ion doping for amorphization.
(Transmission electron microscope) Calculated using observation. Note that the calculation of the thickness of the amorphous semiconductor doped layer and the doped film using the ion doping method are described in J. Appl. Phys. Vol.
5. No. 10, 1994 p4993.

Second Embodiment In the above embodiment, the thin film transistor having the coplanar structure has been described, but the present invention can be applied to the thin film transistor having the inverted stagger structure. FIG. 12 is a cross-sectional structure diagram of a thin film transistor having an inverted stagger structure. This thin film transistor includes a gate electrode 26 formed on an insulating substrate 21 and a gate insulating layer 25 formed on the surface thereof.
And a channel layer 30 formed thereon. A pair of source / drain regions 22 and 23 are formed in the channel layer 30, and the electrode layers 28 and 28 are connected to each other.

In each of the source / drain regions 22 and 23, amorphous semiconductor doped layers 22a and 23a are formed on the surface side in contact with the gate insulating layer 25, and polycrystalline semiconductor doped layers 22b and 23b are formed thereon. It has a laminated structure. The amorphous semiconductor doped layers 22a and 23a and the polycrystalline semiconductor doped layers 22b and 23b have the same structure and function as those of the first embodiment.

Here, a method of manufacturing the thin film transistor having the above structure will be described with reference to FIGS. First, as shown in FIG. 13, on the insulating substrate 21,
For example, a gate electrode 26 is formed by forming a polycrystalline Si film by using the APCVD method and patterning it. Furthermore, S is formed on the gate electrode 26 and the insulating substrate 21.
A gate insulating layer 25 made of an insulating material such as iO ₂ is formed.

Next, as shown in FIG. 14, a polycrystalline Si film having a film thickness of 10 is formed on the gate insulating film 25 by the LPCVD method.
It is formed to 0 nm. Then, a resist is formed on the polycrystalline Si film and patterned, and a resist pattern 31 is formed only on a region where a channel is to be formed. Then, using the resist pattern 31 as a mask, impurities 32, for example, in the case of an n-channel TFT, phosphorus is added in the polycrystalline Si film 30 at a dose amount of 1 × 10 ¹⁶ / cm ^-2 and an acceleration voltage of 60 k
Ion implantation is performed by eV to make the polycrystalline Si film 30 amorphous.

Further, as shown in FIG. 15, after patterning the amorphized channel layer 30 into a predetermined shape, the ArF excimer laser beam 33 is irradiated with 150 to 20.
Irradiation under the irradiation condition of 0 mj / cm ² and about 50 n from the surface
Melt recrystallize to a depth of m. As a result, the recrystallized regions become phosphorus-doped low-resistance polycrystalline semiconductor doped layers 22b and 23b, and the lower layers thereof are amorphous semiconductor doped layers 22a and 23a in which the amorphous state is maintained.
Becomes By this step, the source / drain regions 22 and 23 having a laminated structure of the a-Si films 22a and 23a and the polycrystalline Si films 22b and 23b are formed. Also in this step, as in the first embodiment, the type of impurities used for ion implantation for amorphization is selected according to the conductivity type of the TFT, and the amorphous semiconductor doped layer 22 is used.
In order to control the thickness of a and 23a, the acceleration voltage of the impurities to be ion-implanted is appropriately adjusted.

Furthermore, the amorphization step by Si ion implantation described as another method for forming the amorphous semiconductor doped layer of the first embodiment may be applied to this step as well. It is possible. After that, as shown in FIG. 16, an aluminum film is deposited on the entire surface by a sputtering method or the like, and then patterned to form electrode layers 28 and 28 connected to the source / drain regions 22 and 23, respectively.

Through the above steps, a TFT having an inverted stagger structure is manufactured. In the above-mentioned first and second embodiments, the source / drain regions are composed of a high resistance a-Si film (amorphous semiconductor doped layer) and a low resistance polycrystalline Si film (polycrystalline semiconductor doped layer). Although an example having a laminated structure of layers has been described, the present invention is not limited to such a two-layer structure. That is, the high resistance amorphous semiconductor doped layer may be provided in the current path of the drain current passing through the source / drain region and the channel region. For this reason, a high resistance amorphous semiconductor doped layer is provided at the boundary with the channel region in at least one of the pair of source / drain regions 2 and 3, and the lower layer side thereof is doped with an impurity having a lower resistance. The region may be laminated in multiple layers.

[0043]

As described above, the semiconductor thin film element according to the present invention is provided with the high resistance impurity region functioning as a series resistance in the current path of the drain current and forming the laminated structure with the low resistance impurity region. With the configuration, a thin film semiconductor element with reduced off current can be realized. Moreover, even when a large number of elements are formed on the substrate, it is possible to accurately control the thickness of the high resistance impurity region of each element, so that a display image in a display device using the thin film semiconductor element of the present invention, such as a liquid crystal display, is displayed. It is possible to realize a device having excellent uniformity.

[Brief description of drawings]

FIG. 1 is a sectional structural view of a thin film transistor having a coplanar structure according to an embodiment of the present invention.

FIG. 2 is a manufacturing process chart showing one process of manufacturing the thin film transistor shown in FIG.

3A to 3D are manufacturing process diagrams showing one process of manufacturing the thin film transistor shown in FIG.

4A to 4C are manufacturing process diagrams showing one step of a manufacturing process of the thin film transistor shown in FIG.

5A to 5D are manufacturing process diagrams showing one process of manufacturing the thin film transistor shown in FIG.

6 is a schematic cross-sectional view schematically showing a crystalline state of a channel layer in the manufacturing process shown in FIG.

7 is a schematic cross-sectional view showing the structure of the channel layer after amorphization in the manufacturing process shown in FIG.

8 is a schematic cross-sectional view showing an operating state near the channel of the thin film transistor shown in FIG.

FIG. 9 is a characteristic diagram showing drain current-gate voltage characteristics of a thin film transistor according to a conventional example and the present invention.

FIG. 10 is a characteristic diagram showing drain current-gate voltage characteristics of the thin film transistor according to the present invention.

FIG. 11 is a characteristic diagram showing drain current-gate voltage characteristics of the thin film transistor according to the present invention.

FIG. 12 is a sectional structural view of a thin film transistor having an inverted stagger structure according to a second embodiment of the present invention.

FIG. 13 is a manufacturing process explanatory view illustrating a step in the manufacturing process of the thin film transistor shown in FIG.

FIG. 14 is a manufacturing process explanatory view which illustrates one manufacturing process of the thin film transistor shown in FIG.

FIG. 15 is a manufacturing process explanatory view illustrating one step of the manufacturing process of the thin film transistor shown in FIG. 12;

16 is a manufacturing process explanatory view illustrating a step in the manufacturing process of the thin film transistor shown in FIG. 12. FIG.

FIG. 17 is a sectional structural view of a conventional thin film transistor having an LDD structure.

FIG. 18 is a manufacturing step cross-sectional view showing a step in the manufacturing process of the conventional thin film transistor shown in FIG. 17.

FIG. 19 is a manufacturing step cross-sectional view showing a step in the manufacturing process of the conventional thin film transistor shown in FIG. 17.

20 is a sectional view of a manufacturing step showing one step of the manufacturing process of the conventional thin film transistor shown in FIG. 17. FIG.

21 is a sectional view of a manufacturing step showing one step of the manufacturing process of the conventional thin film transistor shown in FIG. 17. FIG.

22 is a sectional view of a manufacturing step showing one step of the manufacturing process of the conventional thin film transistor shown in FIG. 17. FIG.

FIG. 23 is a sectional structural view of a conventional thin film transistor having an offset structure.

[Explanation of symbols]

 2, 3, 22, 23 ... Source / drain regions 2a, 3a, 22a, 23a ... Amorphous semiconductor doped layer 2b, 3b, 22b, 23b ... Polycrystalline semiconductor doped layer 4a ... Channel 5, 25 ... Gate insulating layer 6 , 26 ... Gate electrode

Claims (4)

[Claims] 1. A semiconductor layer having a main surface formed on a substrate, a pair of source / drain regions formed in the semiconductor layer at regular intervals in the main surface direction of the semiconductor layer, and a pair of the A channel formation region located between the source / drain regions in the vicinity of the main surface of the semiconductor layer, in which a channel is formed when a predetermined gate voltage is applied, and a channel formation region of the semiconductor layer. A gate insulating layer and a gate electrode formed on the gate insulating layer, wherein at least one of the pair of source / drain regions is sequentially laminated from the main surface of the semiconductor layer in a thickness direction of the semiconductor layer. At least a first impurity region having a relatively high resistance and a second impurity region having a relatively low resistance, and the thickness of the first impurity region is equal to the thickness of the channel. Characterized in that it is formed to be larger than the thickness of,
Thin film semiconductor device. 2. A gate electrode formed on a substrate, a gate insulating layer formed on the gate electrode, a semiconductor layer formed on the gate insulating layer, and the gate insulating layer of the semiconductor layer. A pair of source / drain regions formed in the semiconductor layer at regular intervals along the main surface in contact with each other, and a predetermined gate located near the main surface of the semiconductor layer between the pair of source / drain regions. A channel forming region in which a channel is formed when a voltage is applied, and at least one of the pair of source / drain regions is sequentially stacked from the main surface of the semiconductor layer in a thickness direction of the semiconductor layer. At least a first impurity region having a relatively high resistance and a second impurity region having a relatively low resistance, and the thickness of the first impurity region is the thickness of the channel. Characterized in that it is formed so as to be larger Ri,
Thin film semiconductor device. 3. The thin film semiconductor device according to claim 1, wherein the first impurity region is formed of an amorphous semiconductor. 4. The thin film semiconductor device according to claim 3, wherein the first impurity region is formed of amorphous silicon and the second impurity region is formed of polycrystalline silicon.