JPH08315590A - Nonvolatile semiconductor memory - Google Patents

Abstract

PURPOSE: To perform write/erase operation quickly for all objective memories by quickly detecting whether write/erase operation for a plurality of memory cells has been performed correctly or not. CONSTITUTION: A high voltage is applied to a P type region prior to writing operation and the data in memory cells is erased by setting a control gate at DV. A writing data is latched from IO,/IO into a data latch/sense amplifier, i.e., a CMOSFF, and a precharge signal ϕp goes to H to precharge a bit line BLi. The bit line BLi is provided with 0V when 0 is written while provided with an intermediate potential VM when 1 is written by the latched data. A write confirming operation is precharged, from a state where the bit line BLi is reset to 0V, to drive a select gate and a control gate thus reading the data in the memory cell onto the bit line BLi. Subsequently, a verify signal ϕV goes to H and the potential is outputted only from a bit line BLi used for writing 1 and the potential is sensed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a flash EEPRO.
The present invention relates to a nonvolatile semiconductor memory device using M.

[0002]

2. Description of the Related Art Conventionally, a magnetic disk device has been widely used as a storage device of a computer system. However, the magnetic disk device has the following disadvantages:
Sensitive to shocks because it has a highly precise mechanical drive mechanism,
Due to its weight, it has poor portability, consumes a large amount of power, is not easily driven by a battery, and cannot access at high speed.

Focusing on these drawbacks, in recent years the EEP
Development of a semiconductor memory device using a ROM is in progress. Semiconductor memory devices generally have such advantages.
That is, since it has no mechanical drive portion, it has advantages such as strong impact resistance, light weight and excellent portability, low power consumption, easy battery drive, and high speed access.

As one of the EEPROMs, a NAND cell type EEPROM capable of high integration is known. It has the following structure. That is, a plurality of memory cells are arranged in the column direction, for example. The source and drain of adjacent cells of these cells are sequentially connected in series. Such a connection constitutes a unit cell group (NADA cell) in which a plurality of memory cells are connected in series. Such a unit cell group is connected as a unit to a bit line.

A memory cell usually has a FETMOS structure in which a charge storage layer and a control gate are laminated. The memory cells are integrated and formed in an array in a p-type well formed on a p-type substrate or an n-type substrate. The drain side of the NAND cell is connected to the bit line via the select gate.
The source side of the NAND cell is connected to the source line (reference potential wiring) via the select gate. The control gate of each memory cell is connected to a word line arranged in the row direction.

The write operation of this NAND type EEPROM is as follows. By the previous erase operation, NAND
The thresholds of all memory cells in the cell are made negative. After that, data writing is performed in order from the memory cell located farthest from the bit line. A high voltage Vpp (approximately 20 V) is applied to the control gate of the selected memory cell, and an intermediate potential VM (approximately 10 V) is applied to the control gate and select gate of the memory cell on the bit line side. 0V or an intermediate potential is applied to the bit line according to the write data. When 0V is applied to the bit line, the potential is transmitted to the drain of the selected memory cell, and electrons are injected from the drain to the floating gate. As a result, the threshold value of the selected memory cell shifts in the positive direction.
This state is, for example, "0". Electron injection does not occur when an intermediate potential is applied to the bit line. Therefore, at this time, the threshold value of the memory cell does not change. That is, the threshold has a negative value. This state is set to "1".

Data erasing is simultaneously performed on all memory cells in the NAND cell. That is, all control gates and select gates are set to 0V, bit lines and source lines are set in a floating state, and a high voltage of 20V is applied to the p-type well and the n-type substrate.
Is applied. As a result, the electrons in the floating gates of all the memory cells are extracted into the p-type well, and the threshold value of the memory cells shifts in the negative direction.

The data read operation is performed as follows. That is, the control gate of the selected memory cell is set to 0V.
The power supply potential Vcc (= 5V) is applied to the control gate and the select gate of the non-selected memory cell. In this state, it is detected whether or not a current flows through the selected memory cell. It can be seen that the data of "1" is stored if the data flows, and the data of "0" is stored if the data does not flow.

As is clear from the above description of the operation, the NA
In the ND cell type EEPROM, the non-selected memory cell acts as a transfer gate during write and read operations. Therefore, there is a limit to the threshold voltage of the written memory cell. For example, the preferable range of the threshold value of the memory cell programmed with "0" must be about 0.5 to 3.5V. Considering changes with time after data writing, variations in manufacturing parameters of memory cells, and variations in power supply potential, the threshold distribution after data writing needs to be smaller than the above range.

However, it is difficult to keep the threshold value range after "0" writing within the permissible range in the conventional method in which the write potential and the write time are fixed and data is written under the same condition for all memory cells. . For example, in memory cells, variations in manufacturing process cause variations in cell characteristics. Therefore, some memory cells are easily written and some are hard to be written. Focusing on such a difference in writing characteristics, in order to perform writing such that the threshold value of each memory cell falls within a desired range, the length of writing time is adjusted and writing is performed while verifying. The method of putting in is also proposed.

However, when such a method is adopted, it is necessary to output the data of the memory cell to the outside of the device in order to judge whether the writing has been sufficiently performed. Therefore, there is a problem that the total writing time becomes long.

Regarding erase verify, Japanese Patent Laid-Open No. 3-2
As disclosed in 59499, a technique is known in which outputs of a plurality of sense amplifiers are input to an AND gate and their logics are taken to generate a batch erase verify signal. However, this circuit configuration is , NOR type erase verify can be used only, and write verify cannot be applied. The reason is that the value of the write data is both “1” and “0”, and the batch verification cannot be performed by taking the logic of the sense amplifier output. In this way, since write verification cannot be performed collectively, when writing data,
It was necessary to repeatedly perform writing and verify reading, and to output the data of each memory cell to the outside of the chip one by one. This has been a factor that prevents the speeding up of the write operation.

[0013]

SUMMARY OF THE INVENTION The present invention has been made in view of the difficulty of achieving the above-mentioned high speed, and its purpose is to:
An object of the present invention is to provide an EEPROM capable of speeding up a write operation, a write verify, an erase operation and an erase verify without increasing the area of a control circuit, and a system using the EEPROM.

[0014]

A nonvolatile semiconductor memory device of the present invention corresponds to a plurality of data latch means for temporarily holding write data input from the outside and a plurality of the data latch means. A plurality of memory cells that are provided and that perform a write operation according to the data held in the data latch means during a write operation;
Data corresponding to the plurality of data latch means is provided, and following the write operation, the data read from the memory cell is compared with the data held in the data latch means, and data is written to the memory cell. A plurality of comparing means for determining whether or not each of the plurality of comparing means, and a batch verifying means for outputting a write completion signal when all of the plurality of comparing means determine that writing has been performed to the corresponding memory cell. Composed as one.

[0015]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a NAND type EEP according to a first embodiment of the present invention.
FIG. 2 is a block diagram showing a ROM. A bit line control circuit 2 is provided to perform data writing, reading, rewriting, and verify reading with respect to the memory cell array 1. The bit line control circuit 2 is connected to the data input / output buffer 6. The address signal from the address buffer 4 is applied to the bit line control circuit 2 via the column decoder 3. A row decoder 5 is provided to control the control gate and the select gate in the memory cell array 1. A substrate potential control circuit 7 is provided to control the potential of a p-type region (p substrate or p-type well) in which the memory cell array 1 is formed.

The program end detection circuit 8 detects the data latched in the bit line control circuit 2 and outputs a write end signal. The write end signal is output from the data input / output buffer 6 to the outside.

The bit line control circuit 2 mainly has a CMOS flip-flop (FF). These FFs perform latching of data for writing, sensing operation for detecting the potential of the bit line, sensing operation for verify reading after writing, and latching of rewriting data.

2A and 2B are a plan view and an equivalent circuit diagram of one NAND portion of the memory cell array, respectively. 3A and 3B are respectively shown in FIG.
It is the AA 'line sectional view and BB' sectional view of (a).
In the p-type region 11 surrounded by the element isolation oxide film 12, a memory cell array having a plurality of memory cells, that is, a plurality of NAND cells is formed. Below is one NAND
A description will be given focusing on cells. In this embodiment, eight memory cells M1 to M8 are connected in series to form one NAND cell. Each memory cell is above the substrate 11,
Floating gate 14 (14 ₁ , 1) via gate insulating film 13
4 ₂ , ..., 14 ₈ ) are formed. Above these floating gates 14, control gates 16 (16 ₁ , 16 ₂ ,..., 16 ₈ ) are formed via an interlayer insulating film 15. Each n-type diffusion layer 19 is shared as a source in one of two adjacent memory cells and as a drain in the other. As a result, the memory cells are connected in series.

On the drain side and the source side of the NADA cell, select gates 14 ₉ formed by the same process as the floating gate and control gate of the memory cell, respectively.
19 ₉ and 14 _10, 16 ₁₀ are provided. The upper part of the substrate on which the elements are formed as described above is covered with the CVD oxide film 17. The bit line 18 is provided on the oxide film 17. The bit line 18 is brought into contact with the drain side diffusion layer 19 at one end of the NAND cell.
The control gates 14 in the same row of a plurality of NAND cells arranged in the row direction are connected in common and run in the row direction.
It is arranged as G1, CD2, ..., CG8. These control gate lines are so-called word lines. The select gates 14 ₉ , 16 ₉ and 14 ₁₀ , 16 ₁₀ are also arranged as select gate lines SG1 and SG2 running in the row direction, respectively. The gate insulating film 13 between the select gates 14 ₁₀ and 16 ₁₀ and the substrate 11 can be made thicker than the gate insulating film of the memory cell. If the thickness is increased in this way, reliability can be improved.

FIG. 4 shows an equivalent circuit of a memory cell array in which the plurality of NAND cells are arranged in a matrix.

FIG. 5 shows a concrete configuration example of the bit line control circuit 2 in FIG. The CMOS flip-flop FF serving as a data latch and a sense-up device is provided with the first and second two
It has two signal synchronous CMOS inverters IV1 and IV2. The first signal synchronous CMOS inverter IV1 is
E type, p-channel MOS transistors Qp1, Qp2
, E type, n-channel MOS transistor Qn3,
With Qn4. Second synchronous CMOS inverter IV
2 is E type, p channel MOS transistor Qp
3, Qp4 and E type n-channel MOS transistors Qn5, Qn6.

The output node of the CMOS flip-flop FF and the bit line BLi are connected via an E type n-channel MOS transistor Qn7 controlled by the signal φF.

Between the bit lines BLi and Vcc, an E type controlled by the output node of the flip-flop FF,
An n-channel MOS transistor Qn8 and an E type n-channel MOS transistor Qn9 controlled by the signal φV are connected in series. These transistors allow the bit line BLi to (V) depending on the data of the CMOS flip-flop FF at the time of verify read.
It is charged to cc-Vth).

E type, p channel MOS transistor Qp5 and D type, n channel MOS transistor Q
The series circuit of D1 is a circuit for precharging the bit line BLi to Vcc. The transistor QD1 is provided to prevent a high voltage from being applied to the transistor Qp5 during erasing or writing. E type, n channel MO
The S transistor Qn10 is a reset transistor for resetting the bit line BLi to 0V.

The two nodes N11 and N12 of the CMOS flip-flop FF are connected to the input / output line / IO, via two transfer gates (E type, n-channel MOS transistors Qn1 and Qn2) which are both controlled by the column selection signal CSLi. Each is connected to IO.

The node N11 of the CMOS flip-flop FF is connected to the gate of the E type n-channel MOS transistor Qn11. The output of the transistor Qn11 is used as the write end detection signal VDTC.

FIG. 6 shows a connection relationship between the bit line control circuit 2, the memory cell array 1 and the program end detection circuit 8.

The E type p-channel MOS transistor Qp6 in the program end detection circuit 8 outputs a write end detection signal VDTC. The FF is symbolized for the sake of convenience, as shown in FIG.

The circuit operation at the time of writing and checking in this embodiment will be described below. In the following description, one NAND cell is composed of a series circuit of eight memory cells as described above.

Prior to writing, the data in the memory cell is stored in the p-type region (p substrate or p well) at about 20 V (Vp
p) is applied and the control gates CG1 to CG8 are set to 0 V to erase. By this erasing, the threshold value of the memory cell becomes 0 V or less.

FIG. 7 shows the operation during writing / writing confirmation. In FIG. 5, write data is output line I.
O. / IO to be latched in the CMOS flip-flop FF. After this, the precharge signal φP is "H", /
.PHI.P becomes "L" and the bit line BLi is precharged to Vcc. Further, the voltages VMB and φF change from Vcc to the intermediate potential VM (-10V). Depending on the latched data, the bit line BLi becomes 0 V when "0" is written and VM when "1" is written. At this time,
In the case where the select gate SG1 is VM, SG2 is 0V, and CG2 is selected as the control gate,
CG1 is VM, CG2 is high voltage Vpp (~ 20V), and C
G3 to CG8 are VM.

Select gates SG1 and SG2, control gate C
When G1 to CG8 are reset to 0V, the signal .phi.F becomes "L" and the reset signal .phi.R becomes "H", and the bit line BLi is reset to 0V. Then, the write confirmation operation is performed.

In the write confirmation operation, first, the precharge signal φp becomes "H" and / φp becomes "L", and the bit line BL
i is precharged to Vcc. Then, the row decoder 5 drives the selection gate and the control gate. After the data in the memory cell is read to the bit line, the selection gates SG1 and SG2 and the control gates CG1 to CG8 are reset. After that, the verify signal φV becomes “H”,
Only the bit line BLi for which "1" has been written (Vcc-Vt
h) is output.

After that, φSP and φRP become “H”, and φS
N and φRN become “L”, and φF becomes “H”. Signal φS
P becomes "L", φSN becomes "H", and the bit line potential is sensed. After that, the signal φRP becomes “L”, and φ
RN becomes "H", and the rewrite data is latched.
At this time, the relationship among the write data, the memory cell data, and the rewrite data is shown in Table 1 below.

Table 1 Write data 0 0 1 1 Memory cell data 0 1 0 1 Rewrite data 1 0 1 1 After that, the write end detection signal / φDV becomes "L". If all the rewrite data is "1", the write end detection signal VDTC becomes "H". If there is at least one "0", VDTC is "L". The writing / writing confirmation operation is repeated until VDTC becomes "H". And
The detection result is the data input / output pin or READY / BU
Output from the SY pin to the outside.

In this embodiment, erase, write, read,
Bit line BLi and select gate SG at the time of write confirmation
The potentials of 1, SG2 and control gates CG1 to CG8 are shown in Table 2. Here, the case where CG2 is selected is shown.

Table 2 Erase Write Read Read Write “0” “1” Confirm Bit Line BLi Floating 0V 10V 5V 5V Select Gate SG1 0V 10V 10V 5V 5V Control Gate CG1 0V 10V 10V 5V 5V 5V 5V 5V 5V CG2 0V 20V 20V 20V 20V 5V 〃 CG3 0V 10V 10V 5V 5V 〃 CG4 0V 10V 10V 5V 5V 〃 CG5 0V 10V 10V 5V 5V 〃 CG6 0V 10V 10V 5V 5V 〃 CG7 0V 10V 10V 5V 5V 〃 CG8 0V 10V 10V 5V 5V selection gate SG2 0V 0V 0V 5V 5V source line floating 0V 0V 0V 0V substrate 20V 0V 0V 0V 0V FIG. 8 shows a NAND type EEPROM of the second embodiment of the present invention.
It is a block diagram which shows M. The basic configuration is the same as in FIG. The second embodiment differs from the first embodiment in that the cell array 1
Is divided into two blocks 1A and 1B, and a bit line control circuit 2 is provided commonly to these cell blocks 1A and 1B.

9 and 10 show the bit line control circuit 2 and the program end detection circuit 8. In FIG. 9, E
Type, n-channel MOS transistor Qn16, Qn1
7 and E type, p-channel MOS transistor Qp7,
An FF is formed by Qp9. The E type n-channel MOS transistors Qn14 and Qn15 are FF equalizing transistors. The E type n-channel MOS transistors Qn27 and Qn28 are data detecting transistors.

The E type, n-channel MOS transistor Qn18 and the E type, p-channel MOS transistor Qp8 are FF activation transistors. E type,
The n-channel MOS transistors Qn19 and Qn20 are F
Cell array block 1 and two nodes N1 and N2 of F
Bit lines BLai (i = 0, 1, ...) In A and 1B, BL
It is a transistor for connection with bi (i = 0, 1, ...).
E type, n channel MOS transistors Qn21 to Q
n24 is a transistor for charging the bit line to Vcc-VTH according to the data. Qn25 and Qn26 are bit line precharge / reset transistors. In FIG. 10, E type p-channel MOS transistors Qp10 and Qp11 are program end detecting transistors. / ΦDVA and / φDVB are program end detection signals, and φVEA and φVEB are program end detection signals.

Next, the EEPROM configured as described above
The confirmation operation of writing to the memory will be described with reference to FIG. Here, it is assumed that the bit line BLai of the memory cell array 1A is selected.

Similar to the previous embodiment, for example, 0.5V is applied to the selected control gate instead of 0V, and the verify signal φAV is output. First, the bit line BLai is precharged to 3V and BLbi is precharged to 2V. After that, the precharge signals φPA and φPB are set to the “L” level, and the bit lines BLai and BLbi become floating. The control gate and the select gate are selected by the row decoder 5, and SG1, CG1 and CG3 to CG8 are Vcc and CG2.
Is, for example, 0.5V. In normal reading, if the threshold voltage of the memory cell is 0 V or more, it is read as "0", but in verify reading, it cannot be read as "0" unless it is 0.5 V or more.

After that, the bit line BLai is set to (V) by the verify signal φAV if "1" is written.
It is charged to cc-Vth). Here, the voltage level of the precharge performed by the verify signal may be equal to or higher than the precharge voltage of the selected bit line. The equalize signal φE is output and the CMOS flip-flop is reset. After that, .phi.A and .phi.B become "H", and the nodes N1 and N2 are connected to the bit lines BLai and BLbi, respectively. .PHI.P becomes "L" level and .PHI.N becomes "H" level, and the data on the bit line BLai is read. The read data is latched and becomes the data for the next rewrite.
At this time, the rewrite data is converted from the data of the memory cell at the time of verify read by the previous write data. This data conversion is the same as in Table 1 of the previous embodiment.

After that, / φDVA becomes "L", VDTCA becomes "H" and the program end detection signal φVEA becomes "L" when the writing is completed, as in the previous embodiment.
The write operation ends. At this time, the detection result is output to the outside from the data input / output pin or the READY / BUSY pin.

By the verify read / rewrite operation of this embodiment, too, the unnecessary increase in the threshold value of the memory cell to which "0" is written can be suppressed as in the previous embodiment.

In this embodiment, the potentials of the control gates CG1 to CG8 and the select gates SG1 and SG2 at the time of erasing, writing, verify reading, and reading are as shown in Table 3. Table 3 shows the potential relationship when the control gate CG2 is selected and the bit line BLai is selected.

[0046]Table 3 Erase Write Read Read Write"0""1" confirmation  Bit line BLai Floating 0V 10V 3V 3V Bit line BLbi 〃 0V 0V 2V 2V Select gate SG1 0V 10V 10V 5V 5V Control gate CG1 0V 10V 10V 5V 5V 5V 〃 CG2 0V 20V 20V 5V 5V 〃 CG3 0V 10V 10V 5V 5V 〃 CG4 0V 10V 10V 5V 5V 〃 CG5 0V 10V 10V 5V 5V 〃 CG6 0V 10V 10V 5V 5V 〃 CG7 0V 10V 10V 5V 5V 〃 CG8 0V 10V 10V 5V 5V selection gate SG2 0V 0V 0V 5V 5V Source line Floating 0V 0V 0V 0VBase plate 20V 0V 0V 0V 0V FIG. 12 shows the data in the bit line control circuit 2 according to the present invention.
Select the latch and the program end detection circuit 8.
This is schematically shown in relation to the dot line. Same figure
(A) is the one shown in the first embodiment. E-ta
Ip, n-channel MOS transistors QnD0 to QnDm
Corresponds to the transistor Qn11 in FIG. E type, p
The channel MOS transistor Qp12 is a program shown in FIG.
This corresponds to the transistor Qp6 of the end-of-frame detection circuit 8.

FIG. 6B shows an E type for data detection, n
The channel MOS transistors are connected in series. If all the gates of the data detection transistors QnD0 to QnDm are "H", the program is completed and Vx is "L".
Becomes

Further, in FIGS. 7C and 7D, an E type p-channel MOS transistor is used as the data detecting transistor.
The transistors QpD0 to QpDm are used, and an E type, n-channel MOS transistor Qn29 is used for the program end detection circuit 8. Even in such a configuration,
As in the case of (a), it is possible to detect whether or not writing is completed.

When the detection transistors Qn DO to Qn Dm are connected in parallel as shown in FIG. 12A, even if the number of bit lines is 1000 bits, proper detection is possible. When the transistors are connected in series as shown in FIG. 9B, the source and drain of the adjacent transistors can be made common, so that the pattern area can be made small.

FIG. 13 is an embodiment showing a case where the circuit of FIG. 12 is applied to a one-transistor type (NOR type) flash EEPROM. NOR type flash EEP
In the ROM, the data is inverted at the end of writing. Therefore, as shown in FIG. 13, the terminal of the FF opposite to that in FIG. 12 may be connected to the transistor for data detection.

Next, a NOR type flash EEPROM
An example will be described. JP-A-3-250
FIG. 6 of Japanese Patent Publication No. 495 discloses a memory that employs a NOR type memory cell structure and achieves a high degree of integration comparable to that of a NAND type. In this memory, both writing and erasing operations can be performed with an FN tunnel current. By applying the collective verify circuit in the embodiment of the present invention as described above to this memory, the write verify time can be greatly shortened.

The embodiment thus constructed will be described with reference to FIGS. The circuit configuration of this embodiment is shown in FIG. This device is different from the NAND type E ² PROM in the following points. That is, the memory cell block M
The data to be written in the memory cell MC in the CB is latched in the data latch DR. A signal is output from the node on the opposite side of the data latch DR to the detection transistor.

FIG. 15 shows the distribution of the threshold V _th of the cell in which the data has been written and the cell in which the data has been erased.

Table 4 shows the voltage applied to each part in multiple operations of erase (erase), write (write) and read (read).

_{Table 4} BSL BL WL V _SS Erase 0v Floating 20v 0v Write “0” write (V _th > 5) 22v 0v 0v floating “1” write (V _th <5) 22v 20v 0v floating Unselected cell 22v 0v / 20v 10v floating Read 5v 0v / 5v 5v 0v Next, the erase operation will be described. A block for data rewriting is selected by the row decoder of the block. In addition, the bit line corresponding to the selected memory cell is set to the floating state and the word line is set to 20v. As a result, electrons are injected into the floating gate of the selected memory cell. This implantation is done by FN current. Therefore, the amount of current is extremely small. Therefore, it is possible to erase the memory cells for several thousand bits at the same time.

The verify operation after erasing is performed by the collective verify operation. That is, for example, 5v is added to the word line. At this time, the memory cell to be erased is turned on / off depending on whether the threshold value is sufficiently shifted in the positive direction by the erase operation. That is, if it is off, it is understood that the erase is OK.

More specifically, the verify operation is performed as follows. The signal PRE becomes "L" level, and the transistor T _PRE is turned on. As a result, the precharge line PRECL becomes V through the transistor T _PRE.
Precharged by _cc . At this time, the select line BSL is set to 5v and the select gate SG is turned on.
As a result, the bit line BL is also precharged. The selection target of the word lines WL is 5v. At this time, among the memory cells, the memory cells that have been erased / not sufficiently erased are turned off / on. When the memory cell is turned off / on, the precharge potential of the bit line BL, that is, the precharge line PRECL is held / discharged. The potential of the precharge line PRECL at this time is detected by the sense amplifier and latched in the data latch DR. After that, the signal ERV is set to "H", and the content of the data latch DR is read to the node NA. The potential of the node NA becomes “L” when all the memory cells in the column corresponding to the node NA are erase OK, and becomes “H” when even one of the memory cells has the erase NG. The potential of the node NA is applied to the gate of the verify transistor T _VE . This transistor T _VE
Is turned off / on by "L / H" of the node NA. By turning on / off, the potential of the collective verify sense line L _VE does / does not reach the V _SS level. The above operation is performed for each column. Therefore, the collective verify sense line L _VE
Level is OK for all cells in all columns.
In the case of, the value becomes "H", and in the case of the verify NG even if there is even one cell in any part of the column, it becomes "L".

Next, the write operation (program operation) will be described. The word line of the block to be programmed is set to 0v. 1 for word lines in other blocks
The electric field stress between the drain and the gate in each memory cell is reduced to 0 v. In the block to be programmed, the bit line connected to the memory cell from which electrons are to be extracted from the floating gate is selectively set to 20v for programming.

Program verify is performed by setting the potential "H" of the precharge line PRECL at the time of verify read.
/ L "level and" 0/1 "of the program data. However, the collective verify is performed by the signal PR.
This is performed by setting V to "H". Then, in the case of the program NG, rewriting is performed. In this rewriting, the precharge line PRECL connected to the "0" write OK cell is discharged to "L" level. Therefore, at the time of rewriting, since the bit line is at the “L” level, no electrons are emitted from the floating gate. On the other hand, in the cell of "1" write OK, the threshold value is sufficiently lowered. Therefore, at the time of reprogramming, the precharge potential is discharged through the cell of "1" write OK and becomes "L" level. Therefore, the threshold value of the "1" write OK cell does not change even after reprogramming. On the other hand, program NG, that is, "1"
In the case of write NG, the precharge potential does not decrease due to discharge. Therefore, the "H" level is latched again,
Will be programmed again.

The following effects can be obtained by the embodiment described above. Since the cell structure is the same as the NAND type cell, miniaturization is possible and the chip can be miniaturized.
Furthermore, since the cell itself is a NOR type, the operating current I
_{The cell} is large, and high-speed random access is possible. Further, page write / page read is possible.

In the embodiments of FIGS. 12B and 12C, the same operation can be realized by directly connecting the gate of the data detecting transistor to the bit line BLi. Such examples are shown in FIGS. 16 (a) and 16 (b), respectively. Similarly, in the embodiments of FIGS. 13A and 13D, the same operation can be realized by directly connecting the gate of the data detecting transistor to the bit line BLi. This is shown in FIG.
They are shown in (a) and (b), respectively.

Although the single bit line system is adopted in FIGS. 12, 13, 16 and 17, it is also possible to adopt an open or folded bit line system. The configurations of the data detection transistor, the COMS flip-flop FF, and the selected bit line may be the same as those in this embodiment.

FIGS. 12, 13, 16 and 17 schematically show the structure of the data detecting transistor, the CMOS flip-flop FF and the selected bit line, and can be similarly implemented in various bit line systems. it can.

Next, another embodiment of the present invention will be described. In each of the embodiments described above, one end of the CMOS flip-flop (data latch and sense amplifier circuit) provided at one end of the bit line is connected to the gate electrode of the detection transistor. Then, regardless of the address signal, it is detected whether or not the contents in all the data latches are "1" write data, and it is detected whether or not the write state is sufficient.

Therefore, the data of the data latch circuit at the defective column address or the unused redundant column address provided for relief is also detected. Originally, the writing state is sufficient, but it is detected as if it is insufficient, which causes a problem that writing is not completed. That is, there is a possibility that the write state confirmation operation after writing the data may malfunction due to the influence of the defective column address or the unused column address.

Therefore, in this embodiment, means for relieving the malfunction of the detection circuit for detecting the rewrite data is provided.
This makes it possible to detect the write state only for the column address that is originally used, without being affected by the write state of the defective column address or the unused column address.

The basic structure is the same as that of the first embodiment shown in FIGS. In addition to the first embodiment, in this embodiment,
To remedy the malfunction of the write end detection circuit, a fuse and a non-volatile memory are connected to the write end detection MOS transistor, as described later.

FIG. 18A shows an algorithm for writing / writing confirmation. When a program command is input, "1" program data is automatically latched in the data latch circuits at all column addresses including redundant columns. Here, all column addresses refer to all column addresses of the selected divided portion when the cell array is divided and the data latch circuit is also divided.

The write operation is exactly the same as in the first embodiment, and the write confirmation operation is also substantially the same as in the first embodiment. However, in Table 1 above, the memory cells at the defective column address and the unused column address are "1" before data input.
Has been reset to Therefore, the rewrite data is always "1" regardless of the write data or the memory cell data.

If the write / write confirmation operation is performed according to the algorithm shown in FIG. 18A, even if there is a memory cell in which "0" cannot be written in the defective column address, the write operation is affected by this memory cell and the writing is completed. The detection operation does not malfunction. More specifically, although the write state is sufficient, the memory cell at the defective column address or the unused column address affects the write state, and the write is not detected by mistake, and the write is not completed. It is possible to prevent the problem of.

FIG. 18B shows another algorithm.
For example, assume that a bit line at a defective column address is shorted to the ground potential. In this case, as shown in FIG. 18A, when "1" program data is set, the intermediate potential VM is applied to this bit line. As a result, the intermediate potential VM is short-circuited with the ground potential. As a result, the VM generated in the booster circuit may not be boosted to a predetermined voltage.

Therefore, in the algorithm shown in FIG. 18B, "0" program data is automatically set only in unused column addresses (including defective addresses) after data is input from the outside. Also, after verify reading, "1" program data is automatically set in the unused column address. In this way, the NAND cell type EE having high reliability is not affected by the defect of the bit line leak.
A PROM is realized. 18 (a) and 18 (b), the portion inside the broken line is automatically written in the EEPROM.
It shows what happens internally.

FIG. 19A shows the CMOS shown in FIG.
A data latch / sense amplifier of a flip-flop and a write end detection transistor are schematically shown. 17B and 17C show an example in which the fuses Fu1 and Fu2 are connected to the write end detection MOS transistor in order to relieve the malfunction of the write end detection circuit. FIG. 17
In (b), a fuse Fu1 made of a poly-Si line or an Al line is provided between the source of the write completion detecting MOS transistor and the ground line. Of these fuses Fu1 after the EEPROM test, the fuse Fu1 at a defective column address or an unused column address is cut by a laser beam or the like. As a result, the write end detection operation is not performed for the column address where the fuse Fu1 is cut.

FIG. 19C shows the fuse Fu2 as
A non-volatile memory cell is used. In order to use this nonvolatile memory cell as a fuse, first, ultraviolet light is applied to erase (initialize) the fuse data. That is, for example, V _{th of the} memory cell Fu2 is set to be negative, or 0
<V _th <V _cc . In order to program the fuse data, VF1 is applied to, for example, VM of V _cc or more,
VF2 is set to 0v and VDTC is set to _Vcc . The "0" program data is latched in the latch connected to the column address where the source of the write completion detecting MOS transistor is disconnected from the ground potential. The "1" program data is latched in the latch connected to the column address which is not to be disconnected. The memory cell (fuse Fu at the column address where the “0” data is latched)
A current flows in 2) and its V _th rises due to hot electron injection. Since no current flows in the cell (fuse Fu2) at the column address where "1" data is latched, its _Vth does not rise. In this case, VF
2 and V _cc, may be 0v the VDTC.

In the normal operation, the potentials of the respective parts are set as follows. That is, V of the memory cell at the time of erasing the fuse data
_{When th} becomes negative, V _th of the memory cell is made positive,
The memory cell (fuse Fu
2) is cut. When V _{th of the} memory cell is in the range of 0 <V _th <V _cc at the time of data erasing, V _th of the memory cell is set to V _th > V _cc and VF1 = V _cc ,
VF2 is grounded to obtain the disconnected state of the memory cell.

In erasing the data in the fuse memory Fu2, VF1 is set to the ground potential, VF2 is set to a VM level higher than V _cc , and V _th of the fuse is set to V by the tunnel current.
_It may be _th <0v or 0v < _Vth < _Vcc .

FIG. 20 (a) focuses on one column in the circuit shown in FIG. 19 (c). Figure 2
0 (b) is a plan view of the write end detection MOS transistor and fuse nonvolatile memory shown in FIG. 20 (a). FIG. 20C is a sectional view taken along line XX ′ in FIG. The write completion detecting MOS transistor and the nonvolatile memory for fuse are formed at the same time as the NAND type memory cell is formed. The gate electrode of the write completion detection MOS transistor has a two-layer structure, similarly to the select gate of the NAND cell, and these two-layer gates are connected to each other on the isolation insulating film 12.

The first element such as the write completion detecting MOS transistor and the nonvolatile memory cell for fuse is NA
It is formed similarly to the second element such as the selection transistor and the memory cell in the ND cell. For example, the concentration of the n-type diffusion layer of the first element may be slightly increased by hot electron injection so that it can be easily programmed. For example, the concentration of the n-type diffusion layer of the first element is set to the concentration of the n-type diffusion layer of the peripheral transistor having the n-type diffusion layer that is darker than that of the second element. Then, the second element may be formed simultaneously with the n-type diffusion layer of the peripheral transistor.

FIG. 21 shows another example of the write end detection MOS transistor and the fuse non-volatile memory cell. The figure (a) is a cross-sectional view of the element structure, (b), (c)
3 is an equivalent circuit diagram of FIG. The programming of the nonvolatile memory cell for fuse is performed in the same manner as in FIG. When programming by grounding VF2,
1 (b). When programming is performed by grounding VDTC, it becomes as shown in FIG. Further, this structure is formed similarly to the transistor shown in FIG.

When programming the nonvolatile memory cells shown in FIGS. 20 and 21, it is more efficient to set the power supply potential V _cc higher than that during normal operation. Further, it is more efficient to program the CMOS flip-flop power supply VMB to, for example, VM of V _cc or more.

FIG. 22 shows a NAND cell type EE in the circuit having the fuse shown in FIGS.
3 shows a programming algorithm for a PROM.

After the program command is input (S1), "0" program data is automatically set in all column addresses including unused column addresses (including defective columns) (S2). After that, program data is input in the page mode (S3), and writing / writing confirmation / writing end detection is automatically performed (S4 to S7). The "0" program data is set in the unused column so that the intermediate potential VM is not applied to the unused bit line during programming. Moreover, if VM is the output of the booster circuit and the unused bit line is short-circuited with the ground potential, for example, VM will not be boosted to a predetermined potential.

FIG. 23 shows another example of FIG. 19 (b). A write end detection MOS transistor is connected to a bit line sharing the same column address selection signal CSLi. The fuses for these transistors may be shared. This reduces the layout area.
Of course, this fuse may be replaced with a non-volatile memory.

Next, an embodiment in which the above-mentioned rescue means is applied to the second embodiment shown in FIGS. 8 to 11 will be described.
The basic operation is the same as in the second embodiment. Also in this embodiment, if the programming is performed by the algorithm shown in FIG. 18, the malfunction of the write completion detecting circuit due to the influence of the unused column address can be reduced as much as possible.

Further, as shown in FIG. 24, a fuse may be used for programming according to the algorithm of FIG. In the case of FIG. 24A, two write detection MOS transistors are connected to one data latch / sense amplifier. One fuse is connected to each of these two transistors. Fuse cutting during programming is performed for two fuses at the same time. Therefore, one fuse may be used as shown in FIG. In addition, FIG.
In (b), a non-volatile memory can be used as the fuse.

The circuits of FIGS. 19B and 19C are shown in FIG.
The same function can be provided even if each is changed as in (a) and (b). In addition, FIG.
As shown in (b), p is used as the detection MOS transistor.
A channel E type MOS transistor may be used.
FIG. 27 shows an example in which the detection MOS transistor is directly connected to the bit line. Also in this example, a nonvolatile memory can be used for the fuse.

FIG. 28 is a time chart for explaining the third embodiment. This is for explaining the operation of collectively latching "0" and "1" program data in the data latch / sense amplifier circuits at all column addresses.

In FIG. 6A, φF maintains "L", I / O becomes "H", and / I / O becomes "L",
φSP = “L” and φSN = “H”. Then, φR
P = “L” and φRN = “H”, and the “1” latch ends.

In the case of the "0" latch, I / O = "L" and / I / O = "H" as shown in FIG. After FF becomes inactive, first, φRP = “L”, φRN =
It becomes "H". Then, φSP = “L”, φSN =
It becomes "H".

FIG. 29 is a time chart for explaining the fourth embodiment. This chart shows "0" or "1" for the data latch and sense amplifier at all column addresses.
The operation when latching program data is shown. While φA and φB remain “L”, the potentials of I / O and / I / O are determined according to the data “0” or “1”. φP =
FF is deactivated by setting "H" and φN = "L".
After that, φE becomes “H” and is equalized. After completion of the equalization, all column selection signals CSL become "H", φP = "L", φN = "H", and they are latched.

All columns in FIGS. 28 and 29 mean that, for example, when the cell array is divided and the data latch / sense amplifier is also divided accordingly, the selected portion is selected. Refers to all columns.
Further, in FIG. 8, the open bit line system is adopted, but the folded bit line system can be similarly applied.

FIG. 30 shows a modification of the third embodiment, in which 1
The case where two CMOS flip-flops FF are shared by two adjacent bit lines is shown. At the end of the bit line BL opposite to the flip-flop FF, p-channel E type write detection MOS transistors T1, T
2 gates are connected. Same column selection signal CSL
Fuse F of write detection transistors T1, T1; T2, T2 whose gates are connected to the bit line selected by i
1 and F2 can be shared as shown in FIG. Further, the fuses F1 and F2 can be inserted between the power supply potential V _cc and the sources of the write detection transistors T1 and T2 (FIG. 31 (a)). In this case, use two fuses
It can be shared by two fuses F (see FIG. 31).
(B)).

Thus, according to the third and fourth embodiments,
In addition to the same effects as the first and second embodiments described above,
The following effects can also be obtained. That is, when the result of the write verify read is detected, the write state can be confirmed without being affected by the unused column address or the defective column address. As a result, it is possible to obtain an EEPROM having a write end detection circuit with extremely few malfunctions.

Next explained is the fifth embodiment of the invention. FIG. 32 is a NAND cell type EEPROM of the fifth embodiment.
It is a block diagram of M. For the memory cell array 1,
A bit line control circuit 2 for performing data writing, reading, rewriting and verify reading is provided. The bit line control circuit 2 is connected to the data input / output buffer 6. The output of the column decoder 3 is applied to the memory cell array 1 via the bit line control circuit 2.
The column decoder 3 receives the address signal from the address buffer 4 and the redundant address signal output from the column redundancy circuit 10. The address signal from the address buffer 4 is applied to the column redundancy circuit 10. A row decoder 5 is provided to control the control gates and select gates in the memory cell array 1. A substrate potential control circuit 7 is provided to control the potential of the p substrate or the n substrate in which the memory cell array 1 is formed.

The program end detection circuit 8 detects the data latched by the bit line control circuit 2 and outputs a write end signal. The write end signal is output to the outside via the data input / output buffer 6. Also, since the bit line is charged to a predetermined voltage regardless of the address signal,
A bit line charging circuit 9 is provided. The equivalent circuit of the memory cell array 2 is shown in FIG.

FIG. 33 shows a specific configuration of the memory cell array 1, the bit line control circuit 2 and the bit line charging circuit 9. The NAND cells NC shown in FIG. 2 are arranged in a matrix. NCijr (i = 0 to k, j = 0 to
n) is a redundant part. Data latch and sense amplifier R /
W0 to R / Wm and R / W0r to R / Wkr are n-channel and E-type MOS transistor data transfer transistors QFn0 to QFnm and QFn0r to QF, respectively.
Bit lines BL0 to BLm, BL0r to
It is connected to BLkr. Column selection signals CSL0 to CSL which are inputs to the data latch and sense amplifier R / W
m, CSL0r to CSLkr are the outputs CSL0 to CSLm of the column decoder 4 and the outputs (CSL0r to CSLkr) of the redundancy circuit 10, respectively. Bit line BL0
Up to (k + 1) of BLm can be replaced with bit lines BL0r to BLkr in the redundant portion.

N-channel E type MOS transistor Q
Rn0 to QRnm and QRn0r to QRnkr are reset transistors for resetting the bit line to the ground potential. N-channel E type MOS transistors QPn0 to QPnm, QPn0r to QPnkr
Is a charging transistor for transferring the bit line charging voltage VBL to the bit line as required.

The fuses F0 to Fm and F0r to Fkr are
This is for disconnecting between the charging transistor and VBL, and all that are connected to unused bit lines including defective bit lines are disconnected. For example, when the bit line BL2 is replaced with the redundant bit line BL0r, the fuse F2 is cut off. The remaining redundant bit lines BL1r to BLk
When r is not used, the fuses F1r to Fkr are all blown.

FIG. 34 shows the operation at the time of writing. Prior to the write operation, all data latch / sense amplifiers R /
W is reset to "0" program data. Then, the program data is transferred from the data lines I / O and / I / O to R / W and latched. While data is latched in all R / Ws, the bit lines, control gates and select gates are precharged. After the bit line reset signal φR becomes “L”, the bit line precharge signal φP and the charging voltage VBL become the power supply voltage V _cc . Bit lines other than unused bit lines, that is, used bit lines are V
_Charged to _cc . Control gates CG1 to C of NAND cell
G8 and select gate SG1 are charged to _Vcc . The select gate SG2 is set to the ground potential during the write operation. Thereafter, the bit line precharge signal φP and the charging voltage VBL are boosted to the intermediate potential VM (about 10v), and the bit line B
L, control gates CG1 to CG8, and select gate SG1 are also V
Boosted to M.

After the data latch is completed, the precharge signal φP becomes “L”, the data transfer signal φF becomes V _cc , and then the voltage is boosted to VM. Due to the latched program data, only the bit line where "0" data is latched is set to the ground potential. Also, the selected control gate (here CG2) is a high voltage V _pp (about 20v)
Boosted to. The unused bit lines including the defective bit line remain at the ground potential because the corresponding R / W is reset to "0" program data before the data latch operation. In the memory cell connected to the bit line whose R / W is latched with "0" program data, the threshold value is increased. In the memory cell connected to the bit line in which “1” is latched in R / W, the threshold value does not change, and the threshold value at the time of erasing is held.

After the control gates CG1 to CG8 and the selection gate SG1 are reset to the ground potential, the data transfer signal φF is grounded, the reset signal φR becomes "H", and the bit lines are reset to the ground potential.

During this write operation, the unused R / W is reset to "0" program data prior to the data loading and the fuse disconnection operation of the bit line charging circuit causes the unused bit lines to be erased. The intermediate potential VM is never applied.

FIG. 35 shows the read operation. The reset signal φR becomes “L” and the precharge signal φP becomes “H”. This charges all bit lines except the unused bit line to VBL (typically V _cc ). The selected control gate (here, CG2) is grounded, and the remaining control gates CG1 and CG3 to CG8 are "H".
(Typically V _cc ). Since the threshold voltage of the memory cell in which “0” data is written is high (V _th > 0v), the bit line potential remains “H”. Since the threshold voltage of the memory cell in which “1” data is written is low (V _th <0 v), the bit line potential becomes “L”. After the data of the memory cell is output to the bit line as the bit line voltage, the data transfer signal φF becomes “H” and the bit line voltage is sensed by the data latch / sense amplifier R / W. The potential of each part of the memory cell is the same as in Table 2.

As described above, according to this embodiment, the defective bit can be relieved by cutting the fuse of the bit line charging circuit, and the same effects as those of the third and fourth embodiments described above can be obtained. .

FIG. 36 is a diagram showing a sixth embodiment.
Similarly, the specific configurations of the memory cell array 1, the bit line control circuit 2, and the bit line charging circuit 9 are shown.

Two adjacent bit lines BLai and BLb
i, BLajr and BLbjr (i = 0 ... m, j = 0 ...
data latch / sense amplifier R /
Wi, R / Wjr (i = 0 ... m, j = 0 ... k) are arranged one by one. Data transfer signal φFa, reset signal φRa, precharge signal φP for bit line BLai
a is prepared. ΦFb, φ for bit line BLbi
Rb and φPb are prepared. Further, the bit line charging voltage power supply VBL is commonly prepared for BLai and BLbi.

37 and 38 show write and read operations, respectively. If BLai is selected, BLa
Regarding i, the operation is similar to that of the embodiment of FIG. The non-selected bit line BLbi prevents the erroneous writing to the memory cell connected to BLbi while being charged to the intermediate potential VM during the writing operation. In addition, BLbi maintains a grounded state during a read operation and serves to suppress coupling noise between bit lines. Table 5 shows the potential of each part of the memory cell.
Shown in

Table 5 Erase write Read out “0” “1” Bit line BLai Floating 0v 10v 5v Bit line BLbi 10v 10v 0v Select gate SG1 0v 10v 10v 5v Control gate CG1 0v 10v 10v 5v Control gate CG2 0v 20v 20v 0v Control gate CG3v5v 10G 10v 5v control gate CG5 0v 10v 10v 5v control gate CG6 0v 10v 10v 5v control gate CG7 0v 10v 10v 5v control gate CG8 0v 10v 10v 5v selection gate SG2 0v 0v 0v 0v 0v 0v 0v 0v 0v 0 plate FIG. 39 is a modification of the embodiment shown in FIG. here,
Four types of data I / O lines I / O0 to I / O3 are used, and a common column selection signal CSLi is input to the four data latch / sense amplifiers R / W. If even one of the four bit lines to which CSLi is commonly input has a leak defect, it is necessary to repair the four bit lines together. Therefore, in this embodiment, four fuses are combined into one fuse. Similarly in the embodiment shown in FIG. 36, as shown in FIG. 40, the fuses of a plurality of bit lines for commonly inputting CSLi can be integrated into one fuse.

FIG. 41 shows a modification of the embodiment shown in FIG. The example of FIG. 41 is different from the example shown in FIG. 40 in that the fuse is divided into a fuse Fa for BLai and a fuse Fb for BLbi. In this case, since the two fuses Fa and Fb are provided, it is inevitable that the circuit area becomes large. However, since the BLai and BLbi can be separately rescued, the rescue efficiency is high.
This relief method will be described in detail with reference to FIGS. 42 and 43.

FIG. 42 schematically shows the embodiment shown in FIG. If repair is performed only with the column selection signal CSLi, BLai and BLbi are replaced at the same time, as shown in FIG. Similarly, in the case of FIG. 40, BLai0 to BLai3 and BLbi0 to BLbi3 are also included.
And will be replaced at the same time. On the other hand, FIG.
In the embodiment, as shown in FIG. 42 (b), only BLai or only BLbi is replaced by the redundant part BLajr or BLb.
It can be replaced with jr without any operational problem. To this end, the column selection signal CSLi and the data transfer signal φF
Relief is performed by a logical product with a (or φFb).

FIG. 43 schematically shows FIG. 41. As in FIG. 42 (b), only BLai0 to BLai3 are BL.
ajr0 to BLajr3, or BLbi0 to BLbi
Only 3 can be replaced with BLbjr0 to BLbjr3. In this case, the fuse may be connected as shown in FIG. As is clear from FIGS. 42 and 43, B
It suffices if the arrangement relationship between La and BLb is maintained and relief is performed.

FIG. 44 shows an embodiment in which one data latch / sense amplifier R / W is shared by four bit lines. BLa1i and BLbli are adjacent to each other. R
BLa2i and BLb2i are arranged symmetrically with respect to / W. Even in such a case, CSLi and φFa1, φFa2, φ should be kept while maintaining the positional relationship between BLa and BLb.
By taking the logic of Fb1 and φFb2, various relief methods can be implemented as shown in FIGS.

Specifically, in FIG. 45 (a), the same R
Bit lines BLa1i and BLa2 connected to / W
i, BLb1i, BLb2i are simultaneously replaced. FIG.
5 (b), two bit lines BLa1i, BLa2i
Alternatively, BLb1i and BLb2i are replaced as a unit.
In FIG. 46A, two bit lines BLa1i, BLb
1i or BLa2i, BLb2i is replaced as a unit. In addition, in FIG. 46B, each bit line is replaced with the bit line of the redundant portion.

In the embodiments of FIGS. 39, 40, and 41, as shown in FIGS. 47, 48, and 49, a MOS transistor for precharge and a MOS transistor for reset are used to force the column selection signal CSLi. The lines may be shared. When the bit line is precharged or reset, that is, φR or φP is “H”
Is set to "H". In this example, the signal φ
Although PR is separately required, the number of reset or precharge MOS transistors can be reduced.

In addition, in the fifth and subsequent embodiments, a fuse for relieving a defective bit is provided between the bit line charging circuit and the final voltage supply line, but these embodiments and the third and fifth embodiments are also provided. It is also possible to use and together.

The various circuit configurations for shortening the write verify time have been described above using the first to sixth embodiments. Next, an embodiment using the present invention for erase verification will be described.

FIG. 50 shows a NAN according to the seventh embodiment of the present invention.
FIG. 3 is a block diagram showing a nonvolatile semiconductor memory device using a D-type EEPROM. A sense amplifier / latch circuit 2 for performing data writing, reading, writing and erasing verification is connected to the memory cell array 1. The memory cell array 1 is divided into blocks composed of a plurality of pages. This block is the minimum erase unit. The sense amplifier / latch circuit 2 is connected to the data input / output buffer 6. The address signal from the address buffer 4 is input to the column decoder 3. The output from the column decoder 3 is input to the sense amplifier / latch circuit 2. The memory cell array 1 includes a row decoder 5 for controlling a control gate and a select gate.
Is connected. P in which the memory cell array 1 is formed
A substrate potential control circuit 7 for controlling the potential of the mold region (p-type substrate or p-type well) is connected to the memory cell array 1.

The verify end detecting circuit 8 detects the data latched in the sense amplifier / latch circuit 2,
The verify end signal is output. The verify end signal is output to the outside through the data input / output buffer 6.

FIG. 51 shows a sense amplifier / latch circuit 2,
The connection relationship between the memory cell array 1 and the verification end detection circuit 8 is shown. In the circuit of FIG. 51, a detection means (detection transistor Qn12) controlled by the first output of the sense amplifier / latch circuit FF is provided.
An E type n-channel MOS transistor is used as the detection transistor Qn12. This transistor Qn12 is provided in each sense amplifier / latch circuit FF connected to each bit line BLi.
As shown in FIG. 51, the detection transistors Qn12 are provided in parallel by commonly connecting their drains to the sense line VDTCE.

Next, the erase operation will be described first with reference to the flowchart of FIG. When the erase command is input, the erase verify cycle is entered. If the erased state is detected, the erase ends at that point (YES in step 101). When it is detected in step 101 that the memory cell is not erased, the erase operation is performed (step 102), and then the verify operation is performed (step 103). If the verify is NG, erase and verify are repeated a predetermined number of times (step 10).
4).

Next, the erase confirmation operation will be described. In the erase operation, a high voltage (for example, 20v) is applied to the p-type region (p-type substrate or p-well) where the memory cell is formed, and VSS is applied to the control gate. This causes the threshold of the memory cell to shift in the negative direction. Next, the data in the memory cell is read. ΦF “H”
, Φsp is “H”, Φsn is “L”, Φr
The C ² MOS inverter is deactivated by setting p to “H” and Φrn to “L”. After that, / ΦP is set to "L" to precharge the bit line to VCC. Next, the selected control gate is set to VSS and the non-selected control gate is set to VCC.
Then, the selected select gate is held at VCC for a certain period of time. At this time, if the selected memory cell is erased and has a negative threshold value, a cell current flows and the bit line is discharged until it reaches VSS. Next, Φsp is set to “L” and Φsn is set to “H”, and the bit line potential is detected. Then, Φrp is “L”, Φrn
The data is latched by setting "H" to "H". After that, it is confirmed whether the verification is completed using the detection transistor. As described above, the sense line VDTCE is commonly connected to the drains of the detection transistors of the plurality of sense amplifier / latch circuits. If all memory cells have a negative threshold, the sense line VDTCE goes "H". In this case, check the next page. If at least one cell with a positive threshold value remains, VDTCE becomes "L". In that case, erasing is repeated until VDTCE is detected to be "H". The detection result is output to the outside from the data input / output pin or the READY / BUSY pin.

In this example, the data was confirmed page by page. However, the confirmation operation may be performed at once for all pages in one NAND block. In this case, VSS is applied to all control gates in the selected block, and the read operation is performed in this state. At this time, if even one memory cell having a positive threshold value remains, the bit line is not discharged, and therefore detection can be performed by the same method as in the above-described embodiment.

The voltage applied to the control gate does not necessarily have to be the VSS level. A negative voltage may be applied to include a margin. In addition, even if VSS is applied to the control gate and a positive voltage is applied to the source or the source and the p-type substrate or the p-well, a state where a negative voltage is applied to the control gate is artificially created. Good.
In addition, a fuse may be provided between the source of the detection transistor and VSS. If the fuse of the sense amplifier / latch circuit corresponding to the defective bit line or the unused bit line for redundancy is cut off, there is no problem in operation. As described above,
The state of erasure can be detected.

Further, these operations can be controlled systematically. In this case, the system is NAND type EE
Each PROM block has a management table that stores whether or not the block is in the erased state. A controller that controls the host system or the non-volatile semiconductor memory device uses a NAND type EEPROM when erasing.
In order to detect whether or not the block to be erased in M is in the erased state, the management table is first referenced. If the reference result is unerased, it is erased. If it indicates that the data has been erased, no further erase operation may be performed.

Confirmation of erasure is also valid before the write operation. Before the write operation, it may be confirmed whether or not the area to be written is erased. In this case, it may be performed in block units or page units.

In FIG. 51, the write verify operation is almost the same as that of the conventional one, and the detailed description thereof will be omitted.

FIG. 53 shows an eighth embodiment of the present invention. The basic configuration is the same as in FIG. In the eighth embodiment, the cell array is divided into two blocks 1A and 1B, and a common sense amplifier / latch circuit 2 is provided in these cell array blocks 1A and 1B. FIG. 54 shows the configuration of the sense amplifier / latch circuit. E type n
Channel MOS transistors Qn16, Qn17 and E
The type p-channel MOS transistors Qp7 and Qp9 form a flip-flop FF. E type n
The channel MOS transistors Qn14 and Qn15 are F
This is an F equalizing transistor. Qn27, Qn
28 is a detection transistor.

E type n-channel MOS transistor Q
n18 and E type p channel MOS transistor Qp
Reference numeral 8 is a transistor for FF activation. E type n
The channel MOS transistors Qn19 and Qn20 are F
F node N1 and N2 and cell array block 1
A transistor for connecting to the bit line in A and 1B.
Qn25 and Qn26 are transistors for bit line precharge and reset. Qn21 to Qn24 are transistors for connecting the bit line and the VCC wiring.

The verify operation after erasing in such a configuration will be described. Here, a case where the bit line BLai of the memory cell array 1A is selected will be described.

First, the bit line BLai is set to 3v and BLb
i is precharged to 2v (reference potential).
After that, the precharge signals ΦPA and ΦPB become “L”, and the bit lines BLai and BLbi are brought into a floating state. Next, select control gate to VSS,
The non-selected control gate is set to VCC and the selected selection gate is set to VCC, and they are held for a certain period of time. After the CMOS flip-flop is reset by the equalize signal,
ΦA and ΦB become “H”, and the nodes N1 and N2 are connected to the bit lines BLai and BLbi, respectively. ΦP becomes “L” and ΦN becomes “H”, and the bit line BLai is read. The read data is latched. afterwards,
It is collectively detected by the detection transistor Qn27.

Next, the bit line B of the memory cell array 1B
It is assumed that Lbi is selected. First, the bit line BLb
i is precharged to 3v and BLai is precharged to 2v (reference potential). After that, the precharge signals ΦPA and ΦPB become “L”, and the bit lines BLai and BLbi.
Becomes floating. Next, the selected control gate is set to VSS, the non-selected control gate is set to VCC, and the selected selection gate is set to VCC, which are held for a certain time.
The CMOS flip-flop is reset by the equalize signal. After that, ΦA and ΦB become “H”,
Nodes N1 and N2 are bit lines BLai and BLb, respectively.
i is connected. ΦP becomes “L” and ΦN becomes “H”, and the bit line BLbi is read. The read data is latched. After that, the detection transistor Qn28
Are collectively detected by.

Qn28 is used as a detection transistor at the time of write verify of the memory cell array 1A. Qn27 is used as a detection transistor at the time of write verify of the memory cell array 1B. In this way, which sensing transistor is used during the verify operation is controlled according to the memory address and the erase / write mode. As a result, the verify operation can be performed by one sensing transistor.

FIG. 55 shows a ninth embodiment of the present invention. In the seventh embodiment of FIG. 51, the detection transistors are connected to both nodes of the sense amplifier / latch circuit. On the other hand, in the ninth embodiment, the p-type detection transistor and the n-type detection transistor are connected to one node of the circuit. At the time of write verify, an n-type detection transistor is used as in the conventional case. A p-type detection transistor is used during erase verification. After erasing,
Perform read operation. If there is an insufficiently erased memory cell, "H" is latched at the bit line side node of the sense amplifier / latch circuit, and "L" is latched at the node opposite to the bit line. As a result, the p-type detection transistor is turned on and VDTCE is set to the “H” level. This potential is detected and the erase operation is performed again.

FIG. 56 shows a tenth embodiment of the present invention. In the eighth embodiment of FIG. 54, the detection transistors are connected to both nodes of the sense amplifier / latch circuit. On the other hand, in the embodiment, the p-type detection transistor and the n-type detection transistor are connected to one node of the circuit. An n-type detection transistor Qn28 is used for the write verification of the memory cell array 1A. For erase verify of the memory cell array 1A, Qp
29 p-type sensing transistors are used. The p-type detection transistor of Qp29 is used for the write verification of the memory cell array 2A. An n-type detection transistor Qn28 is used for erase verification of the memory cell array 2A.

The embodiments in which the present invention is used for erase verification have been described above. It goes without saying that this configuration is also applicable to the NOR type cell as in the write verify described above.

As described above, the following effects can be obtained by using the present invention for erase verification. That is, the erase verify operation can be performed at high speed without reading the data to the outside. Further, when the cell array is composed of two blocks, one detecting means is
Erase verification of one memory cell array block;
It can be used for write verify of the other memory cell array block. As a result, the area of the collective verify circuit can be reduced. Further, a means for detecting whether or not the selected block is in the erased state is provided before the erase operation. Therefore, it is not necessary to perform an unnecessary erasing operation at the time of rewriting processing or the like. As a result, it is possible to increase the speed and improve the reliability.

Then, the first collective verifying means is used for both erase verify and write verify.
One embodiment will be described.

The features of this embodiment are as follows. That is, program verify and erase verify are
Read 256 bytes at a time and read all at once
Batch verify control circuit B to determine whether the result is NG or NG.
BC was provided. Further, the data register circuit DR is configured to be capable of collective verification, and is configured not to be written to the program completion bit again when program verification becomes NG after program verification and reprogramming is performed. Further, a reprogramming control circuit RPC for controlling the data register circuit DR as described above is provided.

The EEPROM of FIG. 57 will be generally described below. The EEPROM of FIG. 57 shows a byte structure having an output of 8 bits and a structure of 256 bytes per page. The memory cells are arranged in a matrix of m rows × 256 bytes in the memory cell array MCA. That is, m word lines are output from the row decoder RD. Further, in each byte, 8 NAND cells B in which 8 rows of memory cells are connected vertically
Eight Cs are arranged in the row direction to form one NAND cell row unit RU, and (m / 8) pieces of this row unit RU are arranged in the column direction. In each unit RU, the drain of each 8 NAND cell BC has a corresponding bit line BL.
And all sources are commonly connected to V _SS .

In each unit, the control gates and the two select gates of the eight memory cells arranged vertically are connected to the row decoder RD via the eight word lines WL and SGD and SGS.

Each bit line BL'OO is connected to a data register circuit DR for latching data at the time of reading and writing. This data register circuit D
From R, two types of signals are output: an output IO amplified depending on whether the potential of the bit line BL'OO is high or low and an inverted signal NIO thereof. The IO and NIO signals are input to the common IO bus line I / OBUS via the column gate transistor CGT which is turned on and off by the output signals of the column decoders CDI and CDII. The signals IO and NIO are input to the sense amplifier circuit S / A from each common IO bus line I / OBUS. The output signal d ^* of the sense amplifier circuit is input to the output buffer circuit I / OBUF.

A write precharge circuit WPC for setting the bit line BL to a high potential at the time of writing and a read precharge circuit RPC for precharging the bit line BL at the time of reading are connected to each bit line BL. ing. The write precharge circuit WPC is composed of an n-channel type transistor TW ₁ having a drain connected to the signal BLCRL, a gate connected to the signal BLCD, and the other end (source) connected to a bit line. Also,
The read precharge circuit RPC has a power source V _{DD at} one end,
A transistor TR ₁ which gate signal PRE bit line is connected to the other end, the bit line to one end, gate signal RST, V _SS is connected to the other end transistor TR ₂
It is composed of

The data register circuit DR includes a latch circuit formed of two inverters IV1 and IV2 and a signal B.
The LCD has a transistor TT input to the gate and connected to the bit line of the memory cell. Further, it has two transistors T _PV and T _EV connected to the respective output terminals of the two inverters IV 1 and IV 2.
The signal IO is applied to one end of the transistor T _PV , and the signal PROVERI is input to the gate. One end of the transistor T _EV is connected to NIO, and the signal E is applied to the gate.
RAVERI is input. The other _ends of the transistors T _PV and T _EV are commonly connected to the gate of the transistor T ₁₄ . One end of the transistor T ₁₄ is connected to V _SS , and the other end thereof is the collective verify control circuit BB.
Input to C. It also has transistors T ₁₁ and T ₁₂ . The transistor T ₁₁ is an n-type, one end of which is connected to the power supply BLCRL, the gate receives the signal NIO, and the other end of which is connected to one end of the transistor T ₁₂ . The output signal PV of the reprogramming control circuit RPCC is input to the gate of the transistor T ₁₂ . The other end of the transistor T ₁₂ is connected to the bit line BL'00.

The collective verify control circuit BBC outputs the signal P
It has a 2-input NOR circuit NOR1 to which the ROVERI and the signal ERAVERI are input. The NOR circuit NOR
The output signal of _{No. 1} is input to the gates of the transistors TP ₁ and TN ₁ . One end of the transistor TP ₁ is connected to the power supply V _CC and the other end is connected to one end of the transistor TN ₁ . The other end of the transistor TN ₁ is connected to V _SS . The midpoints of the transistors TP ₁ and TN ₁ are connected to the transistor T ₁₄ in each data register circuit DR and to the input side of the inverter IV3. The output signal PEOK of the inverter IV3 is output to the outside through an IO buffer circuit (not shown) as a determination signal of whether or not it is OK at the time of verification.

The reprogram control circuit RPCC has an inverter IV _RP and a flip-flop circuit FF _RP .
The signal PROVERI is input to the inverter IV _RP . The output signal and the inverted signal of the inverter IV _RP are input to each of the two NOR circuits in the flip-flop circuit FF _RP . Output signal P of flip-flop circuit FF _RP
V is input to the gate of n-channel transistor T ₁₂ of the data register circuit DR as the control signal.

Next, an EEPROM having such a configuration
Will be described. At the time of erasing, the high voltage (about 20 V) boosted by the erase boosting circuit SU6 is applied to the substrate (p-well) in which the memory cells are formed.
Along with this, the word lines WL1 to WLm and the select gates SGD and SGS are controlled by the row decoder RD.
Is set to "0" V, and electrons are erased from the floating gate to the substrate to erase.

Next, the read operation will be described. By the row decoder RD, the select gates SGD and SGS of the row unit RU having the cell to be selected are set to "H" level and selected. Further, the target cell is selected by setting the word line WL to "0" V.
After this state, a predetermined pulse signal is applied as the signal PRE, the transistor TR ₁ is turned on, and the bit line BL
Is precharged to "H" level. At this time, when "0" data is written in the memory cell to be read, the memory cell is turned off and no current flows. Therefore, the level of the bit line BL is maintained at "H" level, and the level H is latched by the data register circuit DR.
On the other hand, when "1" data is written in the selected cell, the memory cell turns on. Therefore, the bit line BL
Becomes a "1" level and the level is latched by the data register circuit DR. At this time, 256 connected to the selected (L level) word line
All data for bytes is latched by the data register circuit DR connected to each bit line.
Then, by serially changing the column address A _c applied to the column address buffer CAB from “00” to “FF”, the column gate transistors CGT in the bytes 1 to 256 are sequentially turned on, and the common bus line IO bus. The data is sequentially read via.

At this time, due to the structure of the NAND cell, the on-current of the memory cell is very small, about several μA, and charging / discharging thereof requires about several μsec. However, once the data is read and taken into the data register circuit DR, only the data is output via the common bus line I / OBUS, and thus high-speed access of about 100 nsec becomes possible.

Next, the write operation will be described. FIG. 58 shows a timing chart for explaining the write operation.

When the program command PC is input, the program mode is entered. At this time, the signal BLCD for controlling the transmission transistor TT of the data register circuit DR becomes “L” level, and the transistor TT
Turns off. At the same time, the booster circuit SU starts operating, and the signals BLCRL and BLCU input to the write precharge circuit WPC are gradually boosted.
Rise to about V. At this time, the potential of the bit line BL'OO in the memory cell array group also rises as BLCRL rises. At this time, the selected WL is 20V
To a high potential, the gate of the select gate transistor on the source side of the NAND cell group is set to 0V, and the other gates are set to 1V.
Each is set to an intermediate level of about 0V.

In this state, the column address A _c is sequentially changed and the write data is input to the data register circuit DR. At this time, the write data input to the data register circuit DR is latched therein. When the write data of 256 bytes is latched in the data register circuit DR, the signal BLCU becomes the “L” level and the write precharge circuit WPC is turned off. At the same time, the signal BLCD rises to about 10V, the transistor TT is turned on, and the bit line BL'OO and the data register circuit DR are connected. At this time, the power supply VBIT supplied to the data register circuit DR also rises to about 10V. If the "1" level is latched in this circuit DR, the high level of the bit line BL is maintained as it is. If the "0" level is latched in the circuit DR, the precharged bit line BL is discharged to the "L" level, and electrons are injected into the floating gate. In this way, writing of 256 bytes is simultaneously performed.

The operations of program-> program verify-> reprogram will be described below with reference to the timing chart shown in FIG.

The first program operation is the same as in FIG. That is, when the program command PC is input to enter the program mode, the control signal BLCD is "L".
The level becomes the level, the transmission transistor TT in the data register circuit DR is turned off, and the data register circuit DR is disconnected from the bit line. At the same time, the booster circuits SU1 to SU6 start operating and the signals BLCRL, B input to the write precharge circuit WPC.
The LCU gradually increases to reach about 10V. At this time, the potential of the bit line in the memory cell array MCA also rises to a high potential as the signal BLCRL rises. At this time, the selected WL is set to the high potential of about 20V and the NAND
Select gate transistor T ₂ on the source side in the cell group
Of the other transistor T ₁ (select line SL1) is set to an intermediate level of about 10V.

In this state, the column address A _c is sequentially changed and 8-bit write data for a certain byte n is input to the eight data register circuits DR and latched. This is repeated 256 times, and the write data of 256 bytes is latched in all the register circuits DR. After that, the signal BLCU becomes "L" level, and the write precharge circuit WPC is turned off. At the same time, the signal BLCD rises to about 10 V, turning on the transistor TT and connecting the bit line and the data register circuit DR. At this time, the power supply VBIT supplied to the data register circuit DR also rises to about 10V. If "1" level data is latched in the data register circuit DR, the bit line level is maintained at the high level. In addition, the data register circuit D
If the "0" level is latched in R, the high level of the precharged bit line is lowered to "L" level by discharging, and electrons are injected into the floating gate in the selected memory cell, that is, "0". "Data writing occurs. Such writing is simultaneously performed for 256 bytes. The writing operation so far is the same as in the case of FIG.

Next, when the above writing is completed, the verify command VC is input and the program mode is released. The signal BLCD becomes “0” V, and BLCR
L becomes "5" V, signal VBIT becomes 5V,
The bit line is discharged by the reset signal RST. At this time, in the present embodiment, the latch data in the data register circuit DR is not reset. That is, the write data remains latched in the data register circuit DR. In this state, the H level control signal PRE is applied to the read precharge circuit RPC to precharge the bit line. Now, consider the case where "0" data is written. Due to the latch circuit in the data register circuit DR, the signal IO is at "1" level and its inverted signal NIO is at "0" level. At this time, in the program verify mode, the transistor T ₁₂ in the data register circuit DR is turned on, but the transistor T ₁₁ is turned off because the level of the gate signal of the transistor T ₁₁ is “0”. The bit line is not charged from.

After such a "0" write operation, there are two cases, that is, the case where the write becomes NG and the case where the write becomes OK. That is, when it becomes OK, the threshold voltage of the memory cell is shifted in the positive direction, so that the precharged potential is held as it is. And a signal BLCD for controlling the transmission transistor TT
Is set to "1" level, the data register circuit D
R and bit line are connected, and N which was "0" level until now
The potential of IO is increased by the bit line charged to high potential.
It is charged to "1" level. Therefore, the signal PROVER
The “0” level is input to the gate of the transistor T ₁₄ via the transmission transistor TT to which I is input, and the transistor T ₁₄ is turned off.

On the other hand, consider the case where the write fails. That is, even though "0" is written, the threshold voltage of the memory cell exists in the negative direction, so that the potential is discharged to "0" level while being precharged. And the transmission transistor TT
When the signal BLCD for controlling the data is set to "1" level, the transistor TT is turned on and the data register circuit D
R and the bit line are connected. However, this time, the potential of NIO remains "0" level, the gate of the transistor _T 14 is "1" level signal is input, the transistor T ₁₄ is turned on.

Next, consider the case where "1" data is written. When "1" is written, the signal IO is set to "0" level and the signal NIO is output by the latch circuit in the data register circuit DR.
Is at "1" level.

If the verify operation is performed in this state, the data
Transistor T in the register circuit DR₁₁Is on
Become. Therefore, the transistor T₁₁, T₁₂Bite through
Line continues to be charged during the verify operation. Reed Pretty
Transistor TR for Charge ₂Is the memory
Is discharged to "0" level by the on-current when the switch turns on.
Is set to a small conductance gm. Shi
Kashi, transistor T₁₁, T₁₂Conductance of gm
Is always verified by the verify operation after writing "1".
Set a large value to charge the output line to "1" level.
It is fixed. That is, the transistor T₁₄At the gate of
A "0" level signal is input.

In addition, there may be a case where the threshold value of the memory cell becomes high due to erroneous writing even though "1" is written. In such a case, even if the verify operation is performed, the transistor T
_A “0” level signal is input to the gate of ₁₄ . Therefore, there is a problem that it cannot be distinguished from the above case.
However, the presence / absence of such erroneous writing is selected by a test before shipping the product. Therefore, it is almost unnecessary to consider such erroneous writing in actual use.

In this way, the gate of the transistor T ₁₄ in the data register circuit DR connected to each bit line is "0" level or "1" corresponding to the data read by the verify operation. The level is entered. That is, when the bits of the program NG exists even one, the input signal to the gate of the transistor T ₁₄ is "1" level. Therefore, the transistor T ₁₄ is turned on, the signal PEOK becomes “1” level, and the verify NG is shown.

At this time, a new program command PC
Enter II to reprogram. At the time of this reprogramming, unlike the case of the first programming, the program O of the latch data in the data register circuit DR is programmed.
The bit data of K has been changed to "1" write data. Therefore, "0" is written only for the NG bit. That is, no further additional writing is performed on the bit that has become the program OK as a result of the programming, and therefore the threshold voltage does not rise further. In this way, if re-programming is performed several times and all bits become program OK,
The gate signals of the transistors are all at "0" level. At this time, the signal PEOK becomes "0" level for the first time, and the program ends.

When the above method of the present invention is used, at the time of verification, the column addresses are not changed sequentially,
The verify operation can be performed collectively. Therefore, the verify time can be shortened, which in turn shortens the program time. Also, when reprogramming is performed in the case of verify NG, the program completion bit is not programmed again. Therefore, the distribution of the threshold voltage can be reduced and the read margin can be improved.
FIG. 60 shows the V _th distribution during the write operation when the present invention is used. When writing is performed from the erased state, even if the fast-writing memory cell FMC is verified OK, the slow cell SMC is NG. When reprogramming is performed in this state, no additional writing is performed on the memory cell of verify OK. For this reason,
No increase in threshold occurs. That is, the distribution width of the threshold voltage at the time when the cell SMC in which writing is slow becomes the verification OK can be narrowed to V _th DB. As a result, the read margin RM can be sufficiently secured.

Although the above description is based on the program operation, the erase operation and the read operation as to whether or not the erase is OK can be collectively performed as in the program verify. That is, the signal NIO is input to the transistor T ₁₄ during erase verify. Therefore, the signal PEOK is "0" when the erase is OK.
It becomes a level and batch verification is possible.

FIG. 61 shows a flowchart in the erase mode. As can be seen from FIG. 61, in the erase mode, the erase operation itself is the same as the conventional one,
The verify operation can be performed collectively. Therefore, the verification time can be shortened.

In FIG. 57, I / O BUF is an output circuit, the details of which are shown in FIG. 62, for example.

FIG. 63 showing a conventional example shows a part of an array in which a plurality of memory cells are arranged as a memory cell array in a matrix of m rows × 256 bytes.

The bit line is usually formed of an Al film having a thickness of several thousand angstroms and its pitch is several μm.
Arranged in pitch. For this reason, interlayer capacitance also exists between adjacent bit lines. In the figure, the interlayer capacitance between the bit line BL1 and the bit line BL2 is shown as C ₁₂ , and the interlayer capacitance between the bit line BL2 and the bit line BL3 is shown as C ₂₃ .
Further, since the bit line is wired on the memory cell, there is also a capacitance to the substrate. This is C ₁ , C ₂ , C
It is represented as ₃ . Further, the memory cell is connected to the bit line via the selection transistor. Therefore, the junction portion of the selection transistor also has a capacitance. This is represented as C _1j , C _2j and C _3j .

For example, taking a 16M NAND E ² PROM composed of 8192 × 256 bytes of memory cells as an example, the capacitance C ₁ = C ₂ = between the bit line and the substrate.
C ₃ = 0.39pF, interlayer capacitance between the bit line and the bit line C ₁₂ = C ₂₃ = 0.14pF, the capacitance _{C 1j = C 2j = C 3j} = 0.11pF junction portion.

It has been described above that when the data in the memory cell is read, the bit line is precharged to the power supply voltage Vcc level and whether the precharged potential is discharged or not. That is, in the case of the "1" cell, the memory cell is turned on to discharge the precharged potential. Also,
In the case of a "0" cell, the memory cell remains off, so the precharged potential is held as it is. now,
Consider three adjacent bit lines. Bit lines BL1 and B
It is assumed that L3 is connected to the "1" cell and only the bit line BL2 is connected to the "0" cell. When reading, the bit line BL2 is not discharged, but the bit lines BL1 and BL3 are discharged. At this time, since the above-mentioned capacitance exists, the bit line BL2 is affected by the potential fluctuation. That is,
If the voltage displaced by the influence is ΔV, Becomes

In this way, a potential drop of about 1.8 V will occur. This applies not only to the read operation but also to the verify operation during programming. At the time of program verify, there may be a memory cell in which programming has not been sufficiently performed, so that the operation margin becomes more severe.

The description will be given below. FIG. 64 shows a timing chart at the time of program verification.

When a program command PC (not shown) is input, the program mode is entered. At this time, the transmission transistor T of the data register circuit DR
The signal BLCD for controlling T becomes "L", and the transistor TT turns off. At the same time, the booster circuit SU starts operating, and the signals BLCRL and BLCU input to the write precharge circuit WPC (see FIG. 55) are gradually boosted and rise to about 10V. At this time, the potential of the bit line BL in the memory cell array group also rises as BLCRL rises. At this time, the selected WL
Is set to a high potential of about 20V, the gate of the source side select gate transistor of the NAND cell group is set to 0V, and the other gates are set to an intermediate level of about 10V.

In this state, the column address AC is sequentially changed and the write data is input to the data register circuit DR. At this time, the write data input to the data register circuit DR is latched there. When 256 bytes of write data are respectively latched by the data register circuit DR, the signal BLCU becomes "L" and the write precharge circuit WPC is turned off. At the same time, the signal BLCD rises to about 10V and the transistor TT
Turns on, and the bit line BL and the data register circuit DR
Is connected. At this time, the power supply VBIT supplied to the data register circuit DR also rises to about 10V. If "1" is latched in this circuit DR, the bit line B
The “H” of L is maintained as it is. If "0" is latched in the data register circuit DR, the level of the precharged bit line becomes "L", and electrons are injected into the floating gate. In this way, writing of 256 bytes is performed simultaneously.

When the writing is completed, a verify command VC (not shown) is input and the program mode is released. The signal BLCD becomes 5V and BLCRL becomes 0.
V, the signal VBIT becomes 5V, and with this,
The reset signal RST discharges the bit line BL.
At this time, the write data is also reset in the data register DR at the same time.

In this state, the read precharge circuit RP
The transistor TR1 in C is turned on by the control signal PRE, and the bit line is precharged. Then, the data in the memory cell is read as described above, and the write data is verified.

That is, the signals Pv and BLCD are set to the "H" level at the time when the bit lines are fully discharged, and the "L" and "H" levels of the bit lines are sent to the data latch circuit DR. Transfer and re-latch reprogram data. If the verify is NG, that is, if "1" is read even though "0" is written, the bit line is at "L" level. Therefore, the "L" level is latched as it is.
At the time of rewriting, write "0" again. On the other hand, when the verification is OK, the bit line is at the "H" level. At this time, the signals Pv and BLCD are "H".
When it reaches the level, the "H" level of the bit line is transferred to the data latch circuit DR, and the latch data is inverted from "0" data to "1" data. That is, at the time of reprogramming, the threshold voltage does not increase because "1" is written. The bit line for which "1" is written is discharged to "L" level during verification. Signal Pv is "H"
When the level becomes high, the gate of the transistor T ₁₁ becomes "H" level because "1" is latched in the data register DR. Thereby, the transistor T ₁₁ ,
The bit line becomes "H" level again through T ₁₂ . When the signal BLCD goes "H", the bit line goes "H".
The level is latched in the data latch circuit DR again. In this way, N of the bit lines that are writing "0"
Reprogram only the G bits.

However, when performing such a program verify operation, there are the following problems. Next, the problem will be described.

FIG. 65 is a diagram showing a combination of write data WD and verify data VD for three adjacent bit lines.

[0180] shows the case where "1" is written to the bit lines BL1 and BL3 and "0" is written to the bit line BL2, and the bit to which "0" is written is the verify NG. That is, in the verify operation, the precharged potential is discharged to the “L” level on all three bit lines. When the bit line is sufficiently discharged, the signal Pv becomes "H" level and reprogram data is set. That is, since the bit lines BL1 BL3 are "1" write, as the description, the charge from the transistor T _11, T ₁₂ becomes "H" level. At this time, there is a direct current path of a current from the transistors T ₁₁ and T ₁₂ through the memory cell to the power source Vcc to Vss. Therefore, the gm of the transistors T ₁₁ and T ₁₂ is set sufficiently large with respect to the gm of the memory cell so that the “H” level thereof is sufficiently guaranteed.

The bit line BL2 is "0" write NG.
Therefore, the bit line BL2 is also discharged to the "L" level and the bit line BL2 remains at the "L" level even if the signal CON goes to the "H" level. At this time, a problem is that the bit line for which "1" is written is recharged from the "L" level to the "H" level when the reprogram data is set. That is, as described above, the level of the bit line BL2 also rises due to the influence of the coupling between the adjacent bit lines (Tup). For example, considering the threshold drop due to the transistor T ₁₁ , when the power supply voltage Vcc is 5V,
Lift from 0V to 4V. At this time, the bit line BL
The level of 2 will change by ΔV = 0.358 × 4 = 1.4V.

Further, the distribution of the potential level after the predetermined verify also varies due to the variation in the threshold distribution of the memory cell in which "0" is written. This state is shown in FIG. 66. The level after verification may be completely discharged up to "0" V or only up to about 1V. At this time, if affected by the above-mentioned coupling, the potential fluctuates up to 2.4 V and exceeds the sense level. That is, a memory cell that should be a "0" write NG is erroneously detected as a "0" write OK, and the operation margin of the memory cell is reduced.
In the example of combinations (1) to (6) shown in FIG.

A method for solving the above problems will be described below. The operation of writing data to the memory cell after the program command is input is the same as the operation described with reference to FIG. The difference is the operation at the time of program verification. In the program verify mode, the bit line is precharged by the signal PRE. When the bit line precharge is completed, the verify read operation is performed. At this time, the signal Pv is also set to "H" level at the same time. As a result, for the bit line for which “1” is written, the transistor T ₁₁ ,
Since T ₁₂ turns on, it will be charged. Therefore,
The "H" level is maintained without being discharged to the "L" level. Then, after a predetermined time, the signal BL
By setting CD to “H” level, the potential level of the bit line is transferred to the data latch circuit DR, and detected and latched. That is, the bit line for which "1" is written is always at "H" level, and "0" is written for verification OK.
The bit line of is also set to "H" level. In addition, verify N
The G bit line will be discharged. By doing so, as described above, the bit line of "1" write is not discharged. Therefore, when the rewrite data is set, the above-described potential change from the “L” level to the “H” level does not occur.

Therefore, the data can be detected without being affected by the coupling. Therefore, it is possible to prevent data from being erroneously detected. This is shown in FIG.
It can be seen that the combination of FIG. 68 is improved as compared with the case described in FIG. This is illustrated in FIG. 69 in comparison with FIG. 66. As described above, when the rewriting is set, the lifting due to the influence of the coupling of the bit line is eliminated, so that the data can be read correctly.

FIG. 70 shows a rewriting setting transistor T
Another example of ₁₁ and T ₁₂ will be shown. (A) is an example used in the above description, and (b) is another example. By using a transistor having a threshold voltage near 0 V as the transistor T ₁₁ , the “H” level of the bit line at the time of verification can be set close to Vcc. Further, the effect is further enhanced by inputting the boosted potential to the gate of the transistor T ₁₂ . That is, the amount of potential drop (threshold drop) is reduced with respect to the power supply voltage Vcc, and a large margin is provided for the read operation.

71 to 77 are general circuit diagrams used for carrying out the above method, the description thereof will be omitted.

By carrying out the verify operation by such a method, the influence of the bit line coupling can be ignored.

Although not particularly mentioned in the above description, at the time of program verify, the gate of the memory cell is raised by about 0.5 V in order to obtain a margin with respect to the "0" cell.

As described above, with respect to the cell in which "1" is written, the transistors T ₁₁ and T ₁₂ are always turned on during the verify operation, and the current is passed through the memory cell.
It is flowing.

The sources of the memory cells are commonly connected outside the memory cell array, a high voltage of about 20 V is applied at the time of erasing, and connected to a Vwell circuit for setting to the GND level at the time of programming and reading. That is, the wiring resistance of the source line exists. It is assumed that a current of about 10 μA is applied to each cell during verification. When writing “1” for about one page, 2
Current always flows in the memory cells of 56 bytes. That is, 256 × 8 × 10 μ = 20 mA.

Now, assuming that a resistance of about 20Ω exists in the source line, the voltage of the source line floats by 0.4V. On the other hand, when “0” is written for almost one page, almost no current always flows. Therefore, the potential of the source hardly rises to the GND level. That is, there is a problem that the potential of the source at the time of program verify changes due to the write pattern.

Further, at the time of reading, since the path of the current that constantly flows does not exist, the level of the source becomes almost the GND level. Therefore, the distribution of the memory cells varies depending on the write pattern, and the operation margin of the memory cells varies. Further, when the "1" pattern is written in most of the cells for one page, the potentials of the sources at the time of program verify and at the time of read are different, so even if the verify is OK, the actual read is NG.

FIG. 78 shows the structure of the chip. The ground of the circuit for floating the gate of the memory cell by about 0.5 V during program verify is connected to the Vss line of the peripheral circuit. The source line of the memory cell is connected to the Vwell circuit. Therefore, even if the source line of the memory cell floats due to the write pattern, the source of the verify level setting circuit does not float, resulting in a difference in the potential of the source line. Therefore, it is assumed that the verify level is set to 1.0V in consideration of the floating of the source. Assuming that the threshold distribution of the written memory cells is 2.5V, the upper limit of the written memory cells is (1V + 2.5V =) 3.5V when "0" is written in most cells of one page. . On the other hand, when almost "1" is written, the potential of the source also rises by about 0.5V, so the gate of the memory cell becomes equivalent to 0.5V, which is 0.5V + 2.5V, and the upper limit is The threshold value is 3.0V. This difference results in a difference in AC characteristics and a difference in reliability.

To solve this point, as shown in FIG. 79, the source of the verify level setting circuit is commonly connected to the source of the memory cell via the transistor T _A. To the gate of the transistor T _A, a signal “PROVERI” which becomes “H” level at the time of program verification is applied. With this configuration, the source of the verify level setting circuit becomes the same as the source of the memory cell at the time of program verify, so that the change in the source potential of the memory cell can be reflected as it is.

Therefore, if the source floats by 0.5 V, the output potential also rises by 0.5 V with respect to the set value, so that a constant voltage is always applied between the source and gate of the memory cell. . That is, no matter what pattern you write,
Since the same distribution can be obtained, higher reliability can be obtained.

FIG. 80 shows a verify level setting circuit, and FIG. 81 shows a Vwell circuit. Next, a modified example of the eleventh embodiment in which the same effect as that of the eleventh embodiment (FIG. 55) can be obtained with another circuit configuration will be described. In FIG. 82 showing this modification, the same circuits as in the eleventh embodiment (FIG. 55) are designated by the same reference numerals. FIG. 82 shows a memory cell array for one column and its peripheral circuits.

In this modified example, unlike the eleventh embodiment, the data latch circuit DR has two data latch circuits DR1 and DR2. The first data latch circuit DR1 has two inverters directly connected in antiparallel between IO and NIO. The second data latch circuit DR2 has two inverters connected between IO and NIO via the transistors T ₃₁ and T ₃₂ . The transistors T ₃₁ and T ₃₂ are controlled by the signal SDIC. Further, the output signals of the first and second data latch circuits DR1 and DR2 are applied to the exclusive NOR circuit XNOR. That is, only when the logic levels of the two input signals are the same, the level becomes "H". The output of this exclusive NOR circuit XNOR is the transistor T controlled by the signal VREAD.
Added to IO via ₂₁ . Inverted signal of the output of this circuit XNOR through the transistor T ₂₂ which is controlled by a signal VREAD, applied to NIO. In FIG. 82, the transistor T ₁₁ and the transistor T ₁₁ in FIG.
₁₂ is not needed and has been removed.

The read operation and erase operation of the device of FIG. 82 are the same as those in the eleventh embodiment, and the explanation thereof will be omitted.

The write operation will be described below. The program operation is similar to that described above. The program command PC is input to enter the program mode. A column address and a page address indicating a page are input from the outside. At this time, the signal BLCD becomes "L" and the transistor TT is turned off. At the same time, the booster circuit SU starts to operate, and the write precharge circuit W gradually increases.
The signals BLCRL and BLCU input to the PC are boosted and rise to about 10V. At this time, the potential of the bit line BL in the memory cell array group also rises with the rise of BLCRL. At this time, the selected WL is 20V
To a high potential, the gate of the select gate transistor on the source side of the NAND cell group is set to 0V, and the other gates are set to 1V.
Each is set to an intermediate level of about 0V.

In this state, the column address AC is sequentially changed and the write data is input to the data register circuit DR. At this time, the write data input to the data register circuit DR is latched by the first data latch circuit DR1. After the write data of 256 bytes is latched in the first data circuit DR1, the signal BLCU
Becomes "L" and the write precharge circuit WPC is turned off. Further, when the signal SDIC becomes “H”, the transistors T ₃₁ and T ₃₂ are turned on, and the second data latch circuit D
The write data is latched in R2. Then, the signal SD
Transistor T _31, T ₃₂ IC becomes "L" is turned off. Signal SDIC is "H" at the same time as writing data input
As a level, the first and second data latch circuits may be simultaneously latched. At this time, VREAD
Transistors T _21, T ₂₂ because is "L" is OFF. At the same time, the signal BLCD rises to about 10V, the transistor TT is turned on, and the bit line BL and the data register circuit DR are connected.

At this time, the power supply VBIT supplied to the data register circuit DR also rises to about 10V. First
If "1" is latched in the data latch circuit DR1 of, the "H" of the bit line BL is maintained as it is. If "0" is latched in the first data latch circuit DR1, the level of the precharged bit line becomes "L", and electrons are injected into the floating gate. In this way, writing of 256 bytes is performed simultaneously.

Then, as described above, the verify command CF is input after the program operation is completed. As a result, the signal BLCD becomes 0V and BLCRL becomes 5V.
Further, the signal VBIT becomes 5V, and the bit line is discharged by the reset signal RST. At this time, the write data remains latched in the second latch circuit DR2 in the data register circuit DR. In this state,
Control signal RP of "H" to read precharge circuit RPC
C is added and the bit lines are precharged.

Then, the signal BLCD becomes 5V, and the read data is latched by the first latch circuit in association with this. At this time, the data latched in the second latch circuit DR2 is compared. Then, the signal BLCD
Becomes 0V, and the data latch circuit is separated from the memory cell. Then, next signal VREAD is 5V, the transistors T _21, T ₂₂ is turned on, comparator result is latched by the first latch circuit DR1. This level is shown in Figure 83.
An error judgment is made even under the condition that the write data is "1" and the verify data is "0", which is surrounded by a broken line. That is, the write data is "1" and the verify data is "0".
That is, the verify NG signal is output even under the condition ignored in the eleventh embodiment.

The verify read operation is the same as in the eleventh embodiment. That is, when the verify read command CF is input after a predetermined time has passed from the program operation, the verify output mode is entered. Then, / RE is "H" →
By sequentially changing from “L” to “H” to “L”, the column address AC is incremented one after another, and the contents of the latch data are sequentially stored for 256 bytes (256 times).
Output. In the circuit configuration of FIG. 82, the comparison result described in FIG. 83 is output. That is,
“1” data is output in parallel to the verify NG bit, and “0” data is output in parallel to the other bits.

In the above, the method of performing program, verify, and reprogram by command input has been described. However, by inputting a program command, verify operation and reprogram operation are performed by the internal auto operation, and PASS and FAIL determination is performed. Can be done, which makes it even easier to use.

The basic conceptual block diagrams of FIGS. 84 and 85 are shown. The program auto command is decoded by the command register circuit CR. Based on the output of the circuit CR, the logic circuit LOG1 outputs the pulse signal AUTOPules.
Is output. The signal AUTOpules is input to the flip-flop FF1 and latched when the program mode signal PRO is at the "H" level.

Next, the program is started by setting the PRO signal to the "H" level. After a predetermined program time, the program end signal PROE from the logic circuit 2 resets the flip-flop FF1 and the command register circuit CR. Program end signal PROE
Is input to the flip-flop FF1 and also to the flip-flop FF11 to enter the verify mode. Binary counter B for the specified verification time
Counted by C11.

At this time, the verify operation as described above is performed to determine whether the verify is OK. If N
In the case of G, a counter P that counts the number of programs
The NC count value is incremented by 1 and reprogrammed. If OK, pass.

By doing so, it becomes possible to judge PASS and FAIL just by inputting the auto program command, and it becomes easy to use.

Although the above description is based on the program operation, the erase operation can be considered in the same manner.

Next, the combination of verify read and auto program will be described. If verification is still NG even after reprogramming is performed a predetermined number of times, the page (256 bytes) is treated as an error. Here, it is possible to externally identify how many bits of cells are the verify NG. Here, this is called a verify read mode. The program → verify read operation will be described below with reference to the time chart of FIG.

The program operation is similar to that described above. When the program command PC is input, the program mode is entered. A column address and a page address indicating a page are input from the outside. At this time, the transmission transistor T of the data register circuit DR
The signal BLCD for controlling T becomes "L", and the transistor TT is turned off (see FIG. 55). Also, with this,
The booster circuit SU starts operating, and the signals BLCRL and BLCU input to the write precharge circuit WPC are gradually boosted and rise to about 10V. At this time, the potential of the bit line BL in the memory cell array group is also BLCR
It rises as the potential of L rises. At this time, the selected W
L is set to a high potential of about 20V, the gate of the source side select gate transistor of the NAND cell group is set to 0V, and the other gates are set to an intermediate level of about 10V.

In this state, the column address AC is sequentially changed and the write data is input to the data register circuit DR. In the figure, / WE works as a latch signal for input data. At this time, the write data input to the data register circuit DR is latched there. The write data for 256 bytes is the data register circuit D
When latched by R, the signal BLCU becomes "L" and the write precharge circuit WPC is turned off. With this,
The signal BLCD rises to about 10V, the transistor TT is turned on, and the bit line BL and the data register circuit DR are connected. At this time, the data register circuit DR
The power supply VBIT supplied to the device also rises to about 10V. If "1" is latched in this circuit DR, "H" of the bit line BL is maintained as it is. If "0" is latched in the data register circuit DR,
The level of the precharged bit line becomes "L",
Injection of electrons into the floating gate occurs. In this way, 2
56 bytes are written at the same time.

Subsequently, after a lapse of a predetermined time, not the collective verify command VC but the verify read command CF.
Input to enter the verify output mode. The column address AC is incremented one after another, and the contents of the latch data are sequentially output for 256 bytes (256 times). “1” is output in parallel to the verify NG bit, and “0” is output in parallel to the other bits.

As described above, with the structure using the collective verify circuit, it can be output to the outside of the chip whether the verify is NG or not. Here, the output data is not a data actually written in the cell as in the related art, but a verify NG signal indicating whether rewriting should be performed. Therefore, the number of cells having a write error can be counted without having to have an external comparator circuit or the like. The total number of cells for which "0" is output in the verify read is the total verify NG for the "1" page. In addition, as a matter of course, it is possible to specify at which address the verify NG occurred.

Next, verify NG count and ECC
An embodiment in combination with the (error correct circuit) will be described. In general, a method of adding a redundant cell to compensate for an error cell has been used to improve the reliability of stored data.
For example, a redundant bit of 64 bits is provided for a page of 256 bytes (2K bits). By performing Hamming coding using the Hamming distance as redundant bit data, a data error of up to 6 bits can be corrected. More generally, for an M-bit data string, N
Adding redundant bits of bits, It is possible to correct T-bit errors that satisfy

A flow chart of an embodiment having an ECC circuit is shown in FIG. When the write operation is started and the program is started, one page (256 bytes) of data is written. Further, redundant data is written in the 64-bit redundant cell of the error collect circuit. Then, the verify operation is started, and if the verify is OK, it means that the writing is completed without any abnormality and the writing operation is completed. If the verify is NG, the counter is compared with a counter indicating how many times the reprogram is performed. If the counter is the third time or less, the reprogram is performed. Number of reprogram settings (3 in this case)
If the number of times exceeds), verify read is performed. here,
As described above, the number of NG bits for one page is counted. Subsequently, it is compared whether or not the count result can be corrected with a predetermined redundant bit number (64 bits in this case), and if this can be done, the writing is OK and the writing operation is completed. If the number of NG bits is too large to save even redundant bits, a write error will occur.

In this way, even if the write NG bit occurs, no write error will occur as long as it is within the range that can be remedied by the ECC. Therefore, when the storage device is configured as described above, the number of write errors as seen from the outside is significantly reduced as compared with the conventional case. Especially, EEPRO with deterioration over time
In M, the effect is remarkable.

Further, when the ECC circuit is added in the above configuration, a write error may not occur despite the presence of the NG bit. However, NG bit is ECC
It is possible to know how close to the rescue limit of ECC while determining whether the range is within the rescue range.
As an example, a warning may be issued when 80% of the ECC repair limit becomes NG bits. Particularly, in the case of an EEPROM that deteriorates with time, it becomes a means for determining the life of the chip.

Further, as described in the embodiments shown in FIGS. 55 and 6, the verify operation can be performed collectively. Therefore, the writing time including the verification is not so long.

Although the embodiment in which the ECC is added has been described above, this may be configured by one chip or a plurality of Es.
It may be configured as a storage system including an EPROM chip. The effect does not change at all. Although the Hamming method is used as the redundant code generation method, the present invention is not limited to this, and various coding methods such as Reed-Solomon coding method, HV coding method, fire coding method, cyclic coding method, etc. The method may be used.

Although the method of performing the address control by the external input has been described above, an example in which the address pin and the data input pin are made common will be described below.

FIG. 88 shows an example thereof. Where AL
E, NWP, CE, NWE and RE are external control signals. These signals are input from the corresponding input pins, respectively, to determine the operation mode of the chip. In addition, a signal indicating whether the chip is accessible or not is output from the control circuit to the outside through the Ready / Busy pin.
The external signal CLE determines the command input mode. The external control signal ALE determines the address input mode. The external control signal CE is a chip select signal. The external control signal NWE functions as a clock signal for fetching the respective input data in the command input mode, the address input mode and the data input. The external control signal RE is a clock signal having an address increment function and an output buffer enable function when reading consecutive addresses from the addresses input at the time of data reading.

FIG. 88 is a timing chart showing the external control mode when writing is performed. Where first
Serial data input command 8 in command input mode
0H is input. As a result, the chip enters the program start address, and enters the address input mode.
In the address input mode, the column address and page address are fetched into the address buffer at the clock of three steps of the external control signal NWE, and each internal address signal is determined to a predetermined logic level corresponding to the input address data. At this time, the Ready signal is held at the Ready / Busy output terminal. When the address input operation is completed, the signal SDIC changes from "L" to "H" level. Therefore, the common bus line IOi / IOiB
Then, the write data and its inverted data are transferred from the I / O input terminal. Next, while the external control signal NWE is at "L" level, the column decoder output signal CSLn corresponding to the input column address is "H".
Level. In this way, the data is transferred into the data register.

As a result, the contents of the data register from address 0 to address N-1 are the data "1" at the time of initialization. The data registers from address N to address N + j are input from the I / O input / output terminals,
Data is latched.

After this data input mode, when the auto program command 10H is input in the command input mode, the chip writes to the memory cell.

After that, the operation described above (program →
Verify → reprogram) is performed automatically.

During the above writing operation, the Busy signal is output from the Ready / Busy output terminal. The READY signal is set to be automatically output when a predetermined writing time has elapsed. To detect whether the write mode is normally completed, a 70H flag read command is input in the command input mode, and the verify result (signal PE
This is possible by reading "OK" from the I / O input / output terminal.

FIG. 89 shows the input waveform of the external control signal and the data input timing when writing is performed in the above-mentioned semiconductor memory without using the auto command.
Serial data input command 8 in command input mode
0H is input. As a result, the chip inputs the program start address and enters the address input mode. In the address input mode, the column data output signal corresponding to the column address, which is input while the external control signal WE is at the "L" level, is at the "H" level, as in the read mode described above. As a result, the latch contents of the data register are written in the write data latch on the common bus line. In this way, the write data is sequentially latched. When the latch is completed, the program command "40H" is input and the program mode is entered.

Next, when a verify command is input,
The word line corresponding to the internal address signal in the address buffer circuit corresponding to the row address is selected. Further, after a predetermined delay time, one page of memory cell data whose control gate is connected to the selected word line is read out via the bit line and latched in the data register. Next, the content PE of this data register is
The column address is incremented by changing from "H" to "L" to "H", and the data is sequentially called to the outside of the chip. The read data is compared with the external storage write data by the chip. As a result, it is possible to determine at which address and at what bit the error occurred.

FIG. 90 shows the input waveform of the external control signal and the data input timing when the write and verify operations are performed. First, the serial data input command 80H is input in the command input mode. This allows
Since the chip inputs the program start address, it enters the address input mode. In the address input mode, similarly to the read mode described above, the column address and the page address are changed by the three-step clock of the external control signal WE.
It is taken into each address buffer circuit and each internal address signal is set to a predetermined logic level corresponding to the input address data. After that, the column data output data corresponding to the column address, which is input while the external control signal WE is at "L" level, becomes "H" level. As a result, the latch contents of the data register are written in the write data on the common bus line. In this way, the write data is sequentially latched. When this latch ends, the program command "40H" is input,
Switch to program mode. At the time of writing this data, writing is performed until the next verify read command is input.

Next, when a verify command (collective verify) is input, collective verification is performed as described above. Next, in this state, R
E is changed from "H" to "L" to "H", the column address is incremented, and data is sequentially read out of the chip.

In this way, "0" data is output from the bit that has become write NG, and "1" data is output from the bit that has been set to OK. Therefore, the number of defective bits can be determined though it is pseudo. FIG. 91
Is another example of the system shown in FIG. 90. here,
After inputting the verify read command, move RE,
An example has been shown in which the flag read command “70H” is input without incrementing the column address and whether or not the program is OK is output. Even if the system is configured in this way, it is possible to determine Fail / Pass.

As is well known, the writing of data to the NOR type memory cell is performed by injecting hot electrons into the floating gate. Therefore, when writing,
A write current of about 1 to 2 mA is consumed for each memory cell. Therefore, the NAND E ² type is possible, but the NOR type cannot perform page writing of 256 bytes or the like. However, the NOR type is used because it has advantages such as high reading speed.

Since the NOR type is E ² , the data can be rewritten on the on-board. First, addressing is performed, write data is input, writing is performed to a memory cell, data of an address written next is read out, data comparison is performed, and it is determined whether or not writing is performed.

When such an operation is performed on the board, the CPU produces the signals necessary for the data write and verify operations. Therefore, during this period, CP
There is a problem that U is occupied.

Therefore, it is common to open the CPU by automating the write and verify operations inside the chip.

At this time, there is also an example in which a circuit for latching write data, a circuit for latching read data, and a circuit for comparing this data are provided (Japanese Patent Application No. 3-125).
399). In this example, there is a problem that the pattern area becomes relatively large and the chip size becomes large.

The embodiment described below is a comparatively small pattern area which can be used not only for writing but also for erasing.

That is, the embodiments described above are the NAN.
Although a memory cell having a D structure is taken as an example, a batch verify method using a NOR type cell having a two-layer structure will be described below. That is, 2 in FIGS.
An example of a layered memory cell (EEPROM) is shown.

FIG. 92 is a pattern plan view, and FIG. 93 is FIG.
94 is a sectional view taken along the line BB ', and FIG. 94 is a sectional view taken along the line CC' in FIG. In these figures, reference numeral 211 denotes a floating gate (FG) made of polycrystalline silicon of the first layer. 21
2 is a control gate (C
G). The control gate 212 is used as the word line of the memory cell.

Reference numeral 213 is a P-type substrate. 21
4 and 215 are N ⁺ formed on the substrate 214.
The source (S) and the drain (D) are formed of the type diffusion layer. Reference numeral 216 is a contact hole. 217 is the drain 21 via the contact hole 217.
6 is an aluminum layer (bit line BL) connected to 6. Further, reference numeral 218 denotes a gate insulating film for the floating gate transistor, which has a thickness of 100 angstrom. Reference numeral 219 is an insulating film provided between the floating gate 211 and the control gate 12, and is composed of, for example, a three-layer structure film having an O—N—O structure (Oxide-Nitride-Oxide) and has a thickness of It is about 200 Å in terms of oxide film. 220 is a field insulating film, and 221 is an interlayer insulating film.

Next, the principle of operation will be described. When erasing,
An erasing voltage of 12 V is applied to the source 214 and the drain 21
5 in a floating state, and the control gate 213
And As a result, through the thin gate insulating film 18,
A high voltage is applied between the floating gate 211 and the source 214. As a result, due to the Fowler-Nordheim tunnel effect, the electrons in the floating gate 211 are emitted to the source 214 and erased.

At the time of writing, about 6 V is applied to the drain 215.
0V to source 214 and 12V to control gate 213
Are applied respectively. As a result, impact ionization occurs near the drain, electrons are injected into the floating gate 11, and writing is performed.

At the time of reading, 1 V is applied to the drain 215.
0V to the source 214 and 5V to the control gate 213. At this time, the floating gate 211 is turned on / off depending on whether or not there is an electron in the floating gate 211 to indicate data “0” or “1”, respectively.

A semiconductor integrated circuit using such a memory cell, for example, a flash type EEPRO having a 4-bit structure
M is configured as shown in FIG.

In FIG. 95, A _{0 to} A _i are row address input signals, which are amplified and shaped by the row address buffer circuit 1 and then input to the row decoder circuit 2. B _{i + 1 to} B _j are column address input signals, which are amplified and shaped by the column address buffer circuit 3 and then input to the column decoder circuit 4. The row decoder circuit 2 selects only one of the plurality of word lines WL. The column decoder circuit 4 selectively turns on one gate 6A in each column selection gate circuit 6 to select one bit line BL for each I / O, for a total of four bit lines BL. As a result, one memory cell MC, that is, four memory cells MC for each I / O are selected from the memory cell array 5. The information of each selected memory cell MC is detected and amplified by the sense amplifier circuit 7, respectively. The output of each sense amplifier circuit 7 is read out of the chip via each output buffer circuit 8. That is, four pieces of information are simultaneously output to the outside.

In FIG. 95, the memory cell array 5 is composed of four memory cell array units (MCAU) 5A. Each unit 5A has four word lines WL, four bit lines BL, and 1 for simplifying the description.
It has six memory cells MC and four reference memory cells RMC. 4 bit lines B
Corresponding to L, the gate 6 in the column selection gate circuit 6
A also has four. One of these gates 6A
One of them is turned on by the column decoder circuit 4. The reference memory cell RMC has a reference bit line RBL having a reference gate RBT on the way.
Is connected to the sense amplifier circuit (SA) 7.

4 for the EEPROM having such a configuration
Writing of bit data is performed as follows. That is, four data are read from four I / O pads (not shown) for each I / O. The write circuit 10 sets the potential of the bit line BL according to the read data. That is, the write circuit 10 supplies a high potential when the write data is "0" and a low potential when the write data is "1" to the bit line BL selected by the input address signal. At this time, the high potential is also output to the word line WL selected by the input address signal.

That is, when "0" data is written, the selected word line WL and the bit line BL to which the data is to be written have a high potential. As a result, the memory cell MC
Hot electrons generated in the vicinity of the drain D of the memory cell MC are injected into the floating gate FG of the memory cell MC. As a result, the threshold voltage of the memory cell MC is shifted in the positive direction and "0" data is stored.

On the other hand, when writing "1" data, the bit line BL has a low potential. As a result, the floating gate FG
No electrons are injected into the memory cell MC, and the threshold voltage of the memory cell MC does not shift. As a result, "1" data is stored.

On the other hand, when erasing data, the source of the memory cell is set to a high voltage. As a result, the floating gate FG
The electrons injected into are emitted by the FN (Fowler Nordheim) tunnel effect.

FIG. 96 concretely shows a part of FIG. 95. In these figures, the same reference numerals indicate the same circuits. FIG. 96 specifically shows the sense amplifier circuit (SA) 7 and the comparator circuit 9 in detail. Further, a circuit INCIR for inputting one of the signals to be compared to the comparator circuit 9 and a collective verify circuit VECIR for receiving the output of the comparator circuit 9 are shown.

As described above, MC is a memory cell composed of a floating gate type MOS transistor, RMC is a reference memory cell (dummy cell) composed of a floating gate type MOS transistor, BL is a bit line, RBL is a reference bit line, The RBT is a dummy bit line selection transistor equivalent to one of the column selection gate transistors 6A. The transistor RBT is, V _CC potential is supplied to a gate, which is inserted into the reference bit line RBL. BAS is a bus line to which a plurality of column selection gate transistors 6A, 6A, ... Are connected in parallel, LD1 is a first load circuit (bias circuit) connected to this bus line BAS, and LD2 is this reference bit. It is a second load circuit (bias circuit) connected to the line RBL. The potential Vin of the bit line BL ′ on the output side of the first load circuit LD1 and the potential (reference potential) Vref of the reference bit line RBL ′ on the output side of the second load circuit LD2 are the data detection circuit 28 (for example, CMOS
Composed by the current mirror).

In the sense amplifier circuit (SA) 7, a P-channel transistor P4 for activation control is connected between the V _CC power supply and the data detection circuit section 28. An inverted signal / CE is applied to the gate of the transistor P4.
* 1 is given. When the transistor P4 is off, the data detection circuit unit 28 is in a non-operating state and current consumption is reduced. In addition, an inverted signal / CE is applied to the gate between the output terminal DSO of the data detection circuit unit 28 and the ground terminal.
The N-channel transistor N7 to which * 1 is applied is connected.

In the sense amplifier circuit 7, the reference potential Vref of the reference bit line RBL generated based on the data of the reference memory cell RMC and the bit line BL generated based on the data read from the selected memory cell. Potential Vin of is compared. Based on the comparison result, the stored data in the memory cell is detected,
It outputs to the output buffer circuit 8 through three inverters.

The output of the sense amplifier circuit 7 is also input to one input terminal of the comparator circuit 9. The signal (write data) applied to the I / O pad is applied to the other input terminal of the comparator circuit 9. In the comparator circuit 9, these two input signals are compared and
The result (VR0) is added to the collective verify circuit VECIR. The output V from the comparator circuit 9 in the other 3 bits is supplied to the collective verify circuit VECIR.
R1, VR2 and VR3 are also added. The collective verify circuit VECIR outputs these outputs VR0, VR1, VR.
The output from the output circuit Dout is allowed only when 2 and VR3 all indicate write OK. In other cases, that is, even when one of the outputs VR0 to VR3 indicates write NG, the output from the output circuit Dout is blocked.

97 and 98 show the output VR0 from the comparator circuit 9 at the time of program verify and at the time of erase verify, respectively. FIG. 97 (a)
Indicates the case of "1" write. Program OK
In this case, the sense amplifier output DS0 becomes "1". As a result, the comparator output VR0 also indicates "1", that is, the program is OK. FIG. 97 (b) shows the case of "0" write. In the case of "0" write NG, the sense amplifier output DS0 indicates "1". Therefore, the comparator circuit output VR0 indicates "0", that is, the program NG.
FIG. 97C shows the case of "0" write. When "0" write is OK, the sense amplifier output DS0 is "0".
Indicates. Therefore, the comparator circuit output VR0 indicates "H", that is, the program is OK. When all of the comparator circuit outputs VR0 to VR3 indicate "H (program OK)", the batch verify circuit output PV
FY indicates “H”. As can be seen from FIG. 98, in the case of erase OK / NG, the sense amplifier output DS0 is “1”.
/ O ". In response to this, the comparator circuit output V
R0 indicates “1 / O”. Comparator circuit output VR
When all of 0 to VR3 indicate erase OK, the collective verify circuit output EVFY becomes "1". When even one of the comparator circuit outputs VR0 to VR3 indicates erase NG, the output EVFY becomes "0".

Next, FIG. 99 shows a further different embodiment. In this embodiment, a collective verify circuit is incorporated in the memory cell shown in FIG. 6 of JP-A-3-250495. In FIG. 99, circuits similar to those in FIG. 96 are designated by the same reference numerals.

Table 6 shows the voltages applied to the respective parts during erase, write and read in the device of FIG.

Table 6 I / O pad BSL BL WL Vss Erase − 0 V flow 20 V 0 V ^{(electron injection) Ting} light “0” light (without electron removal) 0 V 22 V 0 V 0 V floating “1” light (without electron) 5 V 22 V 20 V 0 V Floating unselected cell-22 V 0V / 20V 10 V Floating lead-5 V 1 V 5 V 0 V The operations of the program verify and erase verify in the apparatus shown in FIG. 99 are the same as the operations shown in FIG.

Next, an example of a storage system using the nonvolatile semiconductor memory device having the collective verify function as described above will be described.

Storage systems are typically organized hierarchically to maximize capacity at minimum cost. The cache system as one of them utilizes the locality of memory access. A computer using an ordinary cache system includes a high-speed, small-capacity SRAM and a low-speed, large-capacity DRAM in addition to a CPU. In such a cache system, a part of the main memory composed of DRAM or the like having a long access time is
The SRAM is replaced with an SRAM having a short access time, thereby shortening the effective access time. That is, CPU
If there is data in the SRAM (that is, if the cache hits), the data is read from the SRAM that can operate at high speed, and if it does not hit (in the case of a mishit), the data is read from the main memory such as DRAM. Read out. If the cache capacity and replacement method are appropriate, the hit rate will exceed 95%, and the average access will be very fast.

In the NAND type EEPROM as described above, writing and erasing can be performed in page units (for example, 2K bits). Processing on a page-by-page basis makes writing and erasing very fast. However, in such a device, since random access is sacrificed, a cache memory composed of RAM such as SRAM and DRAM is essential. NAND type EE
When the cache system is applied to a nonvolatile storage device such as a PROM, the number of times of writing is reduced, and as a result, the life of the chip is extended.

A first embodiment of a memory system using a nonvolatile semiconductor memory device will be described. FIG. 100 shows the circuit configuration. This system has a ROM 121 and a control circuit 122. The ROM 121 has a collective verify function. The control circuit 122 controls writing in the ROM 121 and has at least a write data register inside. This write control circuit 122
Outputs the page data to be written next in response to the collective verify signal output from the ROM 121. This control circuit may be configured by using a CPU, or may be configured by a plurality of chips including a gate array and SRAM.

In the NAND type EEPROM as described above, the batch erase block usually covers several pages. Therefore, when a system such as a cache memory is configured, writing is performed for each batch erase block. For example, a NAND type EE having the above 8 NAND type memory cell
In the PROM, one batch erase block is composed of 2K bits (1 page) × 8 = 16K bits (8 pages), and writing is also performed in this block unit. Therefore, the write operation always involves writing eight pages.

In the circuit shown in FIG. 100, the ROM 121
The write operation for the next page is performed by using the collective verify signal VFY output by. That is, after latching the data of the first page, writing and verification are repeated inside the ROM. When the writing of all data for one page is completed, the collective verify signal VFY for the first page is output. The control circuit 122 detects the collective verify signal VFY and latches the data of the second page in the ROM 121. Then, 2 inside the ROM
Writing and verifying for the second page is repeated, and when writing of all data for one page is completed, the collective verify signal VFY for the second page is output. The third and subsequent pages are written in the same manner as above.

For example, in the NAND type EEPROM having the 8 NAND type memory cells as described above, the control circuit 122 transfers data for 8 pages in one write operation, and the second page and subsequent pages are collectively processed in the previous page. After detecting the verify signal, the page data is transferred.

As described above, according to this embodiment, the write page data can be transferred from the control circuit 122 to the ROM 121 based on the collective verify signal. Conventionally, a comparison circuit and a large-capacity register for verify reading are provided externally, but this is not necessary in this embodiment. This makes the configuration of the control circuit 122 very simple.

The above-described embodiment shows a configuration in which the control circuit 122 has only one ROM 121. On the other hand, it is also possible to configure a memory system having a plurality of ROMs that output a collective verify signal. FIG. 101 shows an example of this. This system has the collective verify function as described above. This system includes ROM 101-
It has 103, RAM 104, and control circuit 105. R
The OMs 101 to 103 output the collective verify signal when the writing is completed. The RAM 104 is a C (not shown).
Used as a cache memory for access from the PU. The control circuit 105 includes a RAM 104 and a ROM 1.
The data transfer between 01 to 103 is controlled. RAM
Data transfer between the ROM 104 and the ROMs 101 to 103 is performed via the data bus 106. ROM10
1 to 103 constitute a main memory and have a much larger capacity than the RAM 104 used as a cache memory.
A general 4-way mapping method is desirable, but various existing mapping methods such as direct mapping and full associative are possible. The block in the cache memory has the same capacity as the batch erase block.

Next, the case where the batch erase block is 16K and the mapping method is 4-way will be described. At this time, SRA
M is 64K bits and has four 16K blocks. These blocks temporarily hold copy data of the batch erase block in the ROM. For example, R
It is assumed that the data in the second, third, fourth, and fifth batch erase blocks in the OM are being accessed. At this time, copy data of these data is temporarily held in four blocks in the SRAM.

It is assumed that a CPU (not shown) performs write and erase operations on, for example, the third batch erase block. At this time, a copy of the data has already been copied to S.
Since it exists (hits) in the RAM, the ROM is not directly accessed, and data is exchanged only through the high-speed SRAM.

It is assumed that the CPU (not shown) reads data from the sixth batch erase block, for example. At this time, the copy of the data of the batch erase block is
Since it does not exist in SRAM (misses), RO
It is necessary to transfer the data read from M to the SRAM. However, prior to this, one of the blocks in the SRAM needs to be written back in the ROM. For example, 2
Data from the second batch erase block from SRAM to ROM
When writing back to, all data in the batch erase block of the ROM is erased, and subsequently, the block data of the SRAM is sequentially transferred and written. In this write back operation, the erase verify signal can be used. This erase verify signal (indicating that the erase operation is completed)
In response to, the data of the first page is transferred from the SRAM. Subsequently, the data transfer for the second and subsequent pages can be performed by detecting the collective verify signal of the previous page, as described above. In the above 8 NAND type EEPROM, data transfer for 8 pages is required. Then, all the data of the 6th batch erase block
The data is copied to an empty block of the SRAM, and the SRAM outputs the data at the address to the CPU.

It is assumed that the CPU (not shown) writes to the seventh batch erase block, for example. At this time, the copy of the data of the batch erase block is
Does not exist in SRAM (misses). Therefore,
It is necessary to perform the above-mentioned write-back operation and read operation prior to the write operation to the SRAM. For example, the data of the third batch erase block is transferred from SRAM to ROM
When writing back to, all data in the batch erase block of the ROM is erased, and subsequently, the block data of the SRAM is sequentially transferred and written. An erase verify signal can be used in this write-back operation. This erase verify signal (indicating that the erase operation is completed)
In response to, the data of the first page is transferred from the SRAM. Subsequently, the data transfer for the second and subsequent pages can be performed by detecting the collective verify signal of the previous page, as described above. In the above 8 NAND type EEPROM, data transfer for 8 pages is required. Then, all the data of the 7th batch erase block is S
The data is copied to an empty block of the RAM, and the data requested by the CPU to write is written to the corresponding area of the SRAM.

As described above, the ROM which outputs the collective verify signal can easily form a cache system in combination with the SRAM or the like. This is because the batch verify signal is used for data write back at the time of a miss hit.

Next, a third embodiment of the memory system having the collective verify function will be described. FIG. 102 shows an example of the circuit. That is, it has ROMs 111 and 112 having a collective verify function, and a control circuit 113 which controls writing and has at least a write data register inside. The control circuit 113 may be configured by using a CPU, or may be configured by a plurality of chips including a gate array and SRAM. Further, the ROM 111 and the ROM 112 may be mounted together on one chip, or may be composed of a plurality of chips.

Continuous page data is stored in ROM111 and R
It is alternately stored in the OM 112. For example 1, 3, 5,
..., the (2N-1) th page is stored in the ROM 111 as 2,
The fourth, sixth, ..., (2N) th page are stored in the ROM 112. As described above, the operation in the write mode includes the operation of transferring page data to the write data latch inside the chip and the subsequent write and verify operations. In this system, writing and verifying of the ROM 112 are performed while the write data is being transferred to the ROM 111. Furthermore, when writing data over a plurality of pages, the ROM111 and the ROM11
Data is alternately transferred to 2 and 3.

Also in the circuit configuration shown in FIG. 101, the collective verify signal output from the ROM is used to control the write data transfer. First, the data on the first page is R
After being transferred to the OM 111, the ROM 111 is subjected to write and verify operations. While the write and verify operations are being performed on the ROM 111, the control circuit 113 transfers the data of the second page to the ROM 112 and subsequently performs the write and verify operations. R
When the writing of the first page of the OM 111 is completed, a collective verify signal is output. In response to this, the control circuit 113 transfers the data of the third page to the ROM 111 and subsequently performs the write and verify operations. Four
The same applies to page writing from the page onward.

As described above, according to the third embodiment, the write page data can be transferred from the control circuit 113 to the ROMs 111 and 112 based on the collective verify signal. Unlike the conventional example, this embodiment does not require an external comparison circuit or a large-capacity register for verify read, and the configuration of the control circuit 112 is very simple. Moreover, since writing is performed alternately, the writing time becomes faster. However, the size of the batch erase block is doubled.

[0280]

According to the present invention, whether or not writing or erasing is properly performed for each of a plurality of memory cells is quickly detected, and writing or erasing is performed for all target memory cells. This can be performed quickly, and moreover, it is possible to prevent the threshold value of the memory cell from changing too much even if writing and erasing are repeated.

[Brief description of drawings]

FIG. 1 is a NAND cell type EEPR according to a first embodiment.
The block diagram which shows the structure of OM.

FIG. 2 is a plan view and an equivalent circuit diagram showing a NAND cell configuration according to the first embodiment.

FIG. 3 is a sectional view taken along line AA ′ and BB ′ of FIG.

FIG. 4 is an equivalent circuit diagram of the memory cell array in the first embodiment.

FIG. 5 is a diagram showing a configuration of a bit line control circuit unit in the first embodiment.

FIG. 6 is a diagram showing a connection relationship between a bit line control circuit unit and another circuit in the first embodiment.

FIG. 7 is a timing chart showing a data write / write confirmation operation in the first embodiment.

FIG. 8 is a NAND cell type EEPR according to a second embodiment.
The block diagram which shows the structure of OM.

FIG. 9 is a diagram showing a configuration of a bit line control circuit according to a second embodiment.

FIG. 10 is a diagram showing a configuration of a program end detection circuit according to a second embodiment.

FIG. 11 is a timing chart showing a write confirmation operation in the second embodiment.

FIG. 12 is a diagram showing another embodiment of a data latch unit and a program end detection circuit.

FIG. 13 is a diagram showing another embodiment of the data latch unit and the program end detection circuit.

FIG. 14 is a circuit diagram of an example of a NOR flash EEPROM.

FIG. 15 is a threshold distribution diagram.

FIG. 16 is a diagram showing another embodiment of the data latch unit and the program end detection circuit.

FIG. 17 is a diagram showing another embodiment of the data latch unit and the program end detection circuit.

FIG. 18 is a diagram showing an algorithm at the time of writing / writing confirmation in the third embodiment.

FIG. 19 is a diagram schematically showing a data latch / sense amplifier and a write end detection transistor.

FIG. 20 is a diagram showing a configuration of a writing end detection transistor and a nonvolatile memory for fuse of FIG. 19;

FIG. 21 is a diagram showing a configuration example different from the configuration in FIG.

22 is a diagram showing a program algorithm when the circuit of FIG. 19 is used.

23 is a diagram showing a circuit configuration different from that in FIG.

FIG. 24 is a diagram showing the configuration of a bit line control circuit in the fourth embodiment.

FIG. 25 is a diagram showing another configuration example of the bit line control circuit in the third and fourth embodiments.

FIG. 26 is a diagram showing another configuration example of the bit line control circuit in the third and fourth embodiments.

FIG. 27 is a diagram showing another configuration example of the bit line control circuit in the third and fourth embodiments.

FIG. 28 is a diagram showing the timing of the operation of collectively latching the same data in the data latch unit of the bit line control circuit in the third embodiment.

FIG. 29 is a diagram showing the timing of the operation of collectively latching the same data in the data latch section of the bit line control circuit in the fourth embodiment.

FIG. 30 is a modification of the third embodiment and includes one CMOSF.
FIG. 6 is a diagram showing a circuit configuration in which F is shared by two adjacent bit lines.

FIG. 31 is a view showing another example of the configuration of FIG. 30;

FIG. 32 is a NAND cell type EEP according to the fifth embodiment.
The figure which shows the structure of ROM.

FIG. 33 is a diagram showing a specific configuration of a memory cell array and its peripheral circuits.

FIG. 34 is a timing chart showing an operation at the time of writing in the fifth embodiment.

FIG. 35 is a timing diagram showing a read operation in the fifth embodiment.

FIG. 36 is a diagram showing a specific configuration of a memory cell array and its peripheral circuits in a sixth embodiment.

FIG. 37 is a timing chart showing a write operation in the sixth embodiment.

FIG. 38 is a timing chart showing a read operation according to the sixth embodiment.

FIG. 39 is a view showing a modified example of the thirty-third embodiment.

FIG. 40 is a diagram showing a modification of the embodiment shown in FIG. 36.

41 is a view showing a modified example of the embodiment shown in FIG.

42 is a diagram schematically showing replacement of bit lines in the embodiment shown in FIG.

43 is a diagram schematically showing replacement of bit lines in the embodiment shown in FIG.

FIG. 44 is a diagram showing an example in which a data latch / sense amplifier is shared by four bit lines.

FIG. 45 is a diagram schematically showing replacement of bit lines in the embodiment of FIG. 44.

FIG. 46 is a diagram schematically showing replacement of bit lines in the embodiment of FIG. 44.

FIG. 47 is a diagram showing a modification of the embodiment shown in FIG. 39.

FIG. 48 is a diagram showing a modification of the embodiment shown in FIG. 40.

FIG. 49 is a diagram showing a modification of the embodiment shown in FIG. 41.

FIG. 50 is a block diagram showing a non-volatile semiconductor memory device according to a seventh embodiment of the present invention.

FIG. 51 is a circuit diagram of a sense amplifier / launch circuit according to a seventh embodiment.

FIG. 52 is a flow chart for explaining an erase operation in the seventh embodiment.

FIG. 53 is a block diagram showing an eighth embodiment of the present invention.

FIG. 54 is a circuit diagram of a sense amplifier / latch circuit according to an eighth embodiment.

FIG. 55 is a circuit diagram of a sense amplifier / latch circuit according to a ninth embodiment of the present invention.

FIG. 56 is a circuit diagram of a sense amplifier / latch circuit according to a tenth embodiment of the present invention.

FIG. 57 is an overall configuration diagram of an eleventh embodiment of the present invention.

FIG. 58 is a timing chart of FIG. 57.

59 is an explanatory diagram of a read margin of FIG. 57.

FIG. 60 is an erasing flowchart of FIG. 57;

FIG. 61 is an erase flowchart.

62 is a detailed example of the output circuit of FIG. 57. FIG.

FIG. 63 is a partial view of a conventional memory.

FIG. 64 is a timing chart at the time of program verification.

FIG. 65 is a diagram showing write data WD and verify data VD.
FIG.

FIG. 66 is a diagram showing distribution of potential levels after verification and threshold dependency of bit lines.

FIG. 67 is a timing chart of program verify.

[FIG. 68] Write data WD and verify data VD
FIG.

FIG. 69 is a diagram showing potential level distribution and bit line threshold dependency after verification.

FIG. 70 shows another example of a rewriting transistor.

FIG. 71 is a general circuit diagram used to implement the present invention.

FIG. 72 is a general circuit diagram used to implement the present invention.

FIG. 73 is a general circuit diagram used to implement the present invention.

FIG. 74 is a general circuit diagram used to implement the present invention.

FIG. 75 is a general circuit diagram used to implement the present invention.

FIG. 76 is a general circuit diagram used to implement the present invention.

FIG. 77 is a general circuit diagram used to implement the present invention.

FIG. 78 is a chip circuit diagram and a threshold distribution diagram as an example.

FIG. 79 is another circuit diagram of the chip as an example.

FIG. 80 is a verify level setting circuit.

81 is a detailed example of a Vwell circuit. FIG.

FIG. 82 is a modification of the eleventh embodiment (FIG. 55).

83 is a chart for explaining the operation of FIG. 82.

FIG. 84 is a conceptual diagram of an auto program.

85 is a flowchart of FIG. 84.

FIG. 86 is a timing chart of the verify operation after the program operation.

FIG. 87 is a flowchart of an embodiment including an ECC circuit.

88 is a timing chart 1 in the external control mode. FIG.

89 is a timing chart 2 in the external control mode. FIG.

FIG. 90 is a timing chart 3 in the external control mode.

FIG. 91 is a timing chart 4 in the external control mode.

FIG. 92 is a plan pattern view of EEFROM.

93 is a cross-sectional view taken along the line BB of FIG. 92.

94 is a cross-sectional view taken along the line CC of FIG. 92.

FIG. 95 is a block diagram of a 4-bit flash EEPROM.

96 is a partial detailed view of FIG. 95. FIG.

97 is a timing chart at the time of program verification. FIG.

FIG. 98 is a timing chart at the time of erase verify.

FIG. 99 is a circuit diagram of still another embodiment.

FIG. 100 shows a storage system as an example.

FIG. 101 shows a storage system as a different embodiment.

FIG. 102 shows a storage system as a further different embodiment.

 ─────────────────────────────────────────────────── ─── Continuation of front page (31) Priority claim number Japanese Patent Application No. 4-77946 (32) Priority date Hei 4 (1992) March 31 (33) Country of priority claim Japan (JP) (31) Priority Claim number Japanese patent application No. 4-105831 (32) Priority date No. 4 (1992) March 31 (33) Country of priority claim Japan (JP) (31) No. of priority claim Japanese patent application No. 4-175693 (32) Priority Hihei 4 (1992) July 2 (33) Priority claiming country Japan (JP) (72) Inventor Hirohito Nakai 580-1 Horikawa-cho, Sachi-ku, Kawasaki-shi, Kanagawa Toshiba Corporation Semiconductor System Technology Center (72) Inventor Yoshiyuki Tanaka 1 Komukai Toshiba-cho, Sachi-ku, Kawasaki-shi, Kanagawa Ltd. Toshiba Research and Development Center (72) Inventor Riichiro Shirata 1 Komukai Toshiba-cho, Ko-ku, Kawasaki-shi, Kanagawa Corporate Toshiba Research and Development Center (72) Inventor Seiichi Aridome Kanagawa Komukai-shi Toshiba-cho, Kawasaki-shi 1 Co., Ltd. Toshiba Research and Development Center (72) Inventor Neo Ito Komukai-shishi 1, Kawasaki-shi, Kanagawa Toshiba Komukai Toshiba Research and Development Center (72) Inventor Yoshihisa Iwata Within the Toshiba Research and Development Center, 1 Komukai Toshiba-cho, Sachi-ku, Kawasaki-shi, Kanagawa (72) Inventor Hiroshi Nakamura 1 Komukai Toshiba-cho, Kouki-ku, Kawasaki-shi, Kanagawa Toshiba Research and Development Center (72) Hideko Ohira, Komukai Toshiba-cho 1 Stock Company, Sachi-ku, Kawasaki-shi, Kanagawa Toshiba Research & Development Center (72) Inventor Yutaka Okamoto 1 Komukai-shi Toshiba-cho, Kawasaki-shi, Kanagawa Stock Company Toshiba Research & Development Center (72) Inventor Masamichi Asano Komukai-cho, Kouki-shi, Kawasaki-shi, Kanagawa 1 Stock Company, Toshiba Research & Development Center (72) Inventor Shigeyoshi Tokushi, Komukai-shi, Kawasaki-shi, Kanagawa Machi 1 Stock Company Toshiba Research and Development Center

Claims (1)

[Claims] 1. A memory cell having a plurality of memory cells arranged substantially in a matrix, wherein the memory cells arranged in the row direction are activated by one of a plurality of word lines, and data is erased from the activated memory cells. And a semiconductor memory device in which data input / output is performed by a corresponding one of a plurality of bit lines running in a column direction, in which a threshold voltage of the memory cell is moved in a positive direction after data writing. Precharge means for precharging each bit line at the time of write verify, and a difference in potential of the bit line after the precharge between when the memory cell is properly programmed and when the programming is not properly performed. And bit line potential output means, which are provided for each bit line and which output an output corresponding to The semiconductor memory device outputs the Luo, writing and outputs a signal of the write completion only when indicating that properly performed, characterized in that it comprises a batch verify means.