JPH08313935A - Lcd device of type integrated with cpu and its production - Google Patents

Lcd device of type integrated with cpu and its production

Info

Publication number
JPH08313935A
JPH08313935A JP12343695A JP12343695A JPH08313935A JP H08313935 A JPH08313935 A JP H08313935A JP 12343695 A JP12343695 A JP 12343695A JP 12343695 A JP12343695 A JP 12343695A JP H08313935 A JPH08313935 A JP H08313935A
Authority
JP
Japan
Prior art keywords
cpu
circuit
glass substrate
lcd device
bare chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP12343695A
Other languages
Japanese (ja)
Inventor
Hiroshi Ogawa
博 小川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Home Electronics Ltd
NEC Corp
Original Assignee
NEC Home Electronics Ltd
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Home Electronics Ltd, Nippon Electric Co Ltd filed Critical NEC Home Electronics Ltd
Priority to JP12343695A priority Critical patent/JPH08313935A/en
Publication of JPH08313935A publication Critical patent/JPH08313935A/en
Withdrawn legal-status Critical Current

Links

Abstract

PURPOSE: To provide an LCD device of a type integrated with a CPU by using a non-alkaline glass substrate. CONSTITUTION: This LCD device is composed of an LCD circuit which is formed with a TFT array 21 by using polycrystalline silicon as well as drivers for driving TFTs having a TFT source driver 22 and a TFT gate driver 23 on the non-alkaline glass substrate 1 and a CPU circuit which is formed with a bare chip of a CPU 31, RAM 32, ROM 32 and gate array 34 and a bare chip of a resistor 35, capacitor 36, oscillator 37 and connector 38 respectively on the non-alkaline glass substrate 1.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、多結晶シリコン薄膜の
TFTを用いたLCD装置に係り、特に、CPU回路と
LCD回路とを無アルカリガラス基板上に一体形成した
LCD装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an LCD device using a polycrystalline silicon thin film TFT, and more particularly to an LCD device in which a CPU circuit and an LCD circuit are integrally formed on an alkali-free glass substrate.

【0002】[0002]

【従来の技術】従来のLCD装置は、図3に示すよう
に、1200℃の耐熱を有する石英基板101上にTF
Tのドレイン及びソース配線パターン、電源及びアース
配線パターンの金属層102をスパッタ法(非晶質薄膜
作成)で形成し、ソース及びドレイン領域となる多結晶
シリコン層3をCVD(Chemical Vapor
Deposition:化学気相成長法)で形成させ、
ボロン及びリンの不純物を注入してP+層,n+層を形
成し、このP+層,n+層上に活性層となる多結晶シリ
コン層4をCVD法で形成し、レーザアニール処理(再
結晶処理)を行なってゲート絶縁膜のSiO2層5を形
成するとともにゲート電極の金属層6を形成する。
2. Description of the Related Art As shown in FIG. 3, a conventional LCD device has a TF on a quartz substrate 101 having a heat resistance of 1200.degree.
The metal layer 102 of the drain and source wiring pattern of T, the power source and the ground wiring pattern is formed by the sputtering method (amorphous thin film formation), and the polycrystalline silicon layer 3 to be the source and drain regions is formed by CVD (Chemical Vapor).
Deposition: chemical vapor deposition method),
Impurities of boron and phosphorus are implanted to form a P + layer and an n + layer, a polycrystalline silicon layer 4 serving as an active layer is formed on the P + layer and the n + layer by a CVD method, and a laser annealing process (recrystallization process) is performed. Then, the SiO2 layer 5 of the gate insulating film is formed and the metal layer 6 of the gate electrode is formed.

【0003】その後、反対面のITO膜16を介してカ
ラーフィルタ15を形成した石英基板117と上述の石
英基板101とを張り合わせてLCD14を注入し、偏
向膜13,18を石英基板101,117に張り、TF
Tアレイ及びTFT駆動用ドライバを多結晶シリコンで
形成するに過ぎなかった。
After that, the quartz substrate 117 on which the color filter 15 is formed via the ITO film 16 on the opposite surface and the above-mentioned quartz substrate 101 are bonded to each other to inject the LCD 14, and the deflection films 13 and 18 are attached to the quartz substrates 101 and 117. Upholstery, TF
The T array and the driver for driving the TFT are simply formed of polycrystalline silicon.

【0004】[0004]

【発明が解決しようとする課題】従来のLCD装置は、
TFTアレイ及びTFT駆動用ドライバを多結晶シリコ
ンで形成するに過ぎなかった。
The conventional LCD device has the following problems.
Only the TFT array and the driver for driving the TFT are made of polycrystalline silicon.

【0005】そこで、本発明の目的は、LCD回路とC
PU回路を無アルカリガラス基板上に搭載したCPU一
体型LCD装置及びその製造方法を提供することにあ
る。
Therefore, an object of the present invention is to provide an LCD circuit and a C
An object is to provide a CPU integrated LCD device having a PU circuit mounted on a non-alkali glass substrate and a method for manufacturing the same.

【0006】[0006]

【課題を解決するための手段】上述の課題を解決するた
めに、本発明のCPU一体型LCD装置は、無アルカリ
ガラス基板上に多結晶シリコンを用いてTFTアレイ及
びTFT駆動用ドライバを形成したLCD回路と、上記
無アルカリガラス基板上にCPU,RAM,ROM,ゲ
ートアレイのベアチップ及び、抵抗,コンデンサ,発振
器,コネクタのベアチップを各々形成したCPU回路と
で構成され、このCPU回路及び上記LCD回路間に各
々の接続用配線を施したことを特徴とする。
In order to solve the above problems, in a CPU integrated LCD device of the present invention, a TFT array and a TFT driving driver are formed by using polycrystalline silicon on a non-alkali glass substrate. An LCD circuit and a CPU circuit in which a bare chip for a CPU, a RAM, a ROM, a gate array and a bare chip for a resistor, a capacitor, an oscillator, and a connector are formed on the alkali-free glass substrate, respectively. It is characterized in that each connection wiring is provided between them.

【0007】上述の課題を解決するために、本発明のC
PU一体型LCD装置の製造方法は、無アルカリガラス
基板上に多結晶シリコンを用いてTFTアレイ及びTF
T駆動用ドライバでLCD回路を形成し、かつCPU,
RAM,ROM,ゲートアレイのベアチップ及び、抵
抗,コンデンサ,発振器,コネクタのベアチップで形成
されたCPU回路を上記無アルカリガラス基板上に導電
性接着させ、上記LCD回路及びCPU回路間を各々ス
パッタ法で配線接続し、上記各々ベアチップにワイヤー
・ボンディングを施して樹脂コーテイングを行なうこと
を特徴とする。
In order to solve the above-mentioned problems, C of the present invention is used.
A method of manufacturing a PU-integrated LCD device includes a TFT array and a TF using polycrystalline silicon on a non-alkali glass substrate.
An LCD circuit is formed by a T drive driver, and a CPU,
A RAM, a ROM, a bare chip of a gate array, and a CPU circuit formed of a bare chip of a resistor, a capacitor, an oscillator, and a connector are conductively adhered to the alkali-free glass substrate, and the LCD circuit and the CPU circuit are respectively sputtered. It is characterized in that wiring is connected, and each bare chip is wire-bonded to perform resin coating.

【0008】[0008]

【実施例】次に、本発明の一実施例によるCPU一体型
LCD装置を、図面を参照して説明する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a CPU integrated LCD device according to an embodiment of the present invention will be described with reference to the drawings.

【0009】図1は、本発明の一実施例によるCPU一
体型LCD装置を示す平面図である。
FIG. 1 is a plan view showing a CPU integrated LCD device according to an embodiment of the present invention.

【0010】図2は、本発明の一実施例によるCPU一
体型LCD装置を示す断面図である。
FIG. 2 is a sectional view showing a CPU integrated LCD device according to an embodiment of the present invention.

【0011】本発明の一実施例によるCPU一体型LC
D装置は、図1に示すように、無アルカリガラス基板1
上に多結晶シリコンを用いてTFTアレイ21及びTF
Tソースドライバ22,TFTゲートドライバ23を有
するTFT駆動用ドライバを形成したLCD回路と、無
アルカリガラス基板1上にCPU31,RAM32,R
OM32,ゲートアレイ34のベアチップ及び、抵抗3
5,コンデンサ36,発振器37,コネクタ38のベア
チップを各々形成したCPU回路とで構成される。
A CPU integrated LC according to an embodiment of the present invention
As shown in FIG. 1, the D device is a non-alkali glass substrate 1
TFT array 21 and TF using polycrystalline silicon on top
An LCD circuit in which a TFT driving driver having a T source driver 22 and a TFT gate driver 23 is formed, and a CPU 31, a RAM 32, and a R on a non-alkali glass substrate 1.
OM32, bare chip of gate array 34, and resistor 3
5, a capacitor 36, an oscillator 37, and a CPU circuit in which bare chips of a connector 38 are respectively formed.

【0012】次に、本発明の一実施例によるCPU一体
型LCD装置の製造方法を、図面を参照して説明する。
Next, a method of manufacturing a CPU integrated LCD device according to an embodiment of the present invention will be described with reference to the drawings.

【0013】次に、本発明の一実施例によるCPU一体
型LCD装置の製造方法は、図1及び図2に示すよう
に、耐熱温度が600℃の無アルカリガラス基板1上に
TFTアレイ21のドレイン及びソース配線及びCPU
回路のY方向接続配線パターンとなるアルミ層2をスパ
ッタ法で形成し、ソース及びドレイン領域となる多結晶
シリコン層3をLPCVD法(Low Pressur
e ChemicalVapor Depositio
n:約600℃,数十mTorr程度の減圧(真空)下
でガスを分解させてた結晶シリコン膜を成長させる。)
で形成、ボロン及びリンの不純物イオンを注入して、P
+層,n+層を造り、このP+層,n+層上に活性層と
なる多結晶シリコン層4をLPCVD法で形成してレー
ザーアニール処理を行い、活性化を図ってゲート絶縁膜
となるSiO2層5を形成する。
Next, as shown in FIGS. 1 and 2, a method of manufacturing a CPU-integrated LCD device according to an embodiment of the present invention, a TFT array 21 is formed on a non-alkali glass substrate 1 having a heat resistant temperature of 600.degree. Drain and source wiring and CPU
The aluminum layer 2 which becomes the Y direction connection wiring pattern of the circuit is formed by the sputtering method, and the polycrystalline silicon layer 3 which becomes the source and drain regions is formed by the LPCVD method (Low Pressure).
e Chemical Vapor Deposition
n: A crystalline silicon film obtained by decomposing gas under reduced pressure (vacuum) of about 600 ° C. and several tens of mTorr is grown. )
Formed by implanting impurity ions of boron and phosphorus,
A + layer and an n + layer are formed, a polycrystalline silicon layer 4 to be an active layer is formed on the P + layer and the n + layer by the LPCVD method, and laser annealing is performed to activate the SiO2 layer to be a gate insulating film. 5 is formed.

【0014】従って、ゲート電極のアルミ層6,Y方向
アルミ配線7及び、CPU31,RAM32,ROM3
2,ゲートアレイ34のベアチップと、QFP(Qua
dFlat Package)IC搭載用のパッド8及
び、リード接続用のパッド9と、抵抗35,コンデンサ
36,発振器37,コネクタ38のベアチップ搭載用の
パッド8を形成する。
Therefore, the aluminum layer 6 of the gate electrode 6, the aluminum wiring 7 in the Y direction, the CPU 31, the RAM 32, and the ROM 3
2, the bare chip of the gate array 34 and the QFP (Qua
A pad 8 for mounting a dFlat Package IC, a pad 9 for connecting a lead, and a pad 8 for mounting a bare chip of a resistor 35, a capacitor 36, an oscillator 37, and a connector 38 are formed.

【0015】さらに、反対面の無アルカリガラス基板1
7にITO層16を介してカラーフィルタ15を形成
し、上述の無アルカリガラス基板1とを張り合わせてL
CD14を圧入し、ベアチップ11あるいはQFP,抵
抗35,コンデンサ36,発振器37,コネクタ38を
導電性接着剤で固定させ、ベアチップ11はアルミワイ
ヤ10でボンディングを行なって樹脂12でコーティン
グし、偏向膜13,18を無アルカリガラス基板1,1
7に張り付ける。
Further, the alkali-free glass substrate 1 on the opposite side
7, the color filter 15 is formed through the ITO layer 16, and the non-alkali glass substrate 1 is bonded to the color filter L.
The CD 14 is press-fitted, the bare chip 11 or the QFP, the resistor 35, the capacitor 36, the oscillator 37, and the connector 38 are fixed with a conductive adhesive, the bare chip 11 is bonded with the aluminum wire 10 and coated with the resin 12, and the deflection film 13 is formed. , 18 are non-alkali glass substrates 1, 1
Stick to 7.

【0016】[0016]

【発明の効果】以上説明したように、本発明の一実施例
によるCPU一体型LCD装置及びその製造方法によれ
ば、安価な無アルカリガラス基板を用いてLCD回路及
びCPU回路を搭載できるため、薄くて安価な装置を実
現できる効果がある。
As described above, according to the CPU integrated LCD device and the manufacturing method thereof according to the embodiment of the present invention, the LCD circuit and the CPU circuit can be mounted by using the inexpensive alkali-free glass substrate. There is an effect that a thin and inexpensive device can be realized.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例によるCPU一体型LCD装
置を示す平面図である。
FIG. 1 is a plan view showing a CPU integrated LCD device according to an embodiment of the present invention.

【図2】本発明の一実施例によるCPU一体型LCD装
置を示す断面図である。
FIG. 2 is a sectional view showing a CPU integrated LCD device according to an embodiment of the present invention.

【図3】従来のLCD装置を示す断面図である。FIG. 3 is a cross-sectional view showing a conventional LCD device.

【符号の説明】[Explanation of symbols]

1,17 無アルカリガラス基板 2,6 LCD回路(アルミ層) 3,4 多結晶シリコン層 5 多結晶シリコン層(SiO2層) 7 接続用配線(Y方向アルミ配線) 8,9 接続用配線(パッド) 10 接続用配線(アルミワイヤ) 11 ベアチップ 12 樹脂 13,18 LCD回路(偏向膜) 14 LCD回路(LCD) 15 LCD回路(カラーフルタ) 16 LCD回路(ITO膜) 1,17 Alkali-free glass substrate 2,6 LCD circuit (aluminum layer) 3,4 Polycrystalline silicon layer 5 Polycrystalline silicon layer (SiO2 layer) 7 Connection wiring (Y direction aluminum wiring) 8,9 Connection wiring (pad) ) 10 wiring for connection (aluminum wire) 11 bare chip 12 resin 13, 18 LCD circuit (deflection film) 14 LCD circuit (LCD) 15 LCD circuit (color filter) 16 LCD circuit (ITO film)

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 無アルカリガラス基板上に多結晶シリコ
ンを用いてTFTアレイ及びTFT駆動用ドライバを形
成したLCD回路と、上記無アルカリガラス基板上にC
PU,RAM,ROM,ゲートアレイのベアチップ及
び、抵抗,コンデンサ,発振器,コネクタのベアチップ
を各々形成したCPU回路とで構成され、このCPU回
路及び上記LCD回路間に各々の接続用配線を施したこ
とを特徴とするCPU一体型LCD装置。
1. An LCD circuit in which a TFT array and a TFT driving driver are formed by using polycrystalline silicon on an alkali-free glass substrate, and C on the alkali-free glass substrate.
PU, RAM, ROM, a bare chip of a gate array and a CPU circuit in which a bare chip of a resistor, a capacitor, an oscillator and a connector are respectively formed, and wiring for each connection is provided between the CPU circuit and the LCD circuit. A CPU-integrated LCD device characterized by:
【請求項2】 無アルカリガラス基板上に多結晶シリコ
ンを用いてTFTアレイ及びTFT駆動用ドライバでL
CD回路を形成し、かつCPU,RAM,ROM,ゲー
トアレイのベアチップ及び、抵抗,コンデンサ,発振
器,コネクタのベアチップで形成されたCPU回路を上
記無アルカリガラス基板上に導電性接着させ、上記LC
D回路及びCPU回路間を各々スパッタ法で配線接続
し、上記各々ベアチップにワイヤー・ボンディングを施
して樹脂コーテイングを行なうことを特徴とするCPU
一体型LCD装置の製造方法。
2. A TFT array and a TFT driving driver using polycrystalline silicon on a non-alkali glass substrate.
The CD circuit is formed, and the CPU circuit formed by the bare chip of the CPU, the RAM, the ROM, the gate array and the bare chip of the resistor, the capacitor, the oscillator, and the connector is conductively adhered to the alkali-free glass substrate, and the LC circuit is formed.
A CPU characterized in that the D circuit and the CPU circuit are connected to each other by a sputtering method, and the bare chips are wire-bonded to perform resin coating.
Method of manufacturing integrated LCD device.
JP12343695A 1995-05-23 1995-05-23 Lcd device of type integrated with cpu and its production Withdrawn JPH08313935A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12343695A JPH08313935A (en) 1995-05-23 1995-05-23 Lcd device of type integrated with cpu and its production

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12343695A JPH08313935A (en) 1995-05-23 1995-05-23 Lcd device of type integrated with cpu and its production

Publications (1)

Publication Number Publication Date
JPH08313935A true JPH08313935A (en) 1996-11-29

Family

ID=14860540

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12343695A Withdrawn JPH08313935A (en) 1995-05-23 1995-05-23 Lcd device of type integrated with cpu and its production

Country Status (1)

Country Link
JP (1) JPH08313935A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1420285A2 (en) * 1997-04-21 2004-05-19 Seiko Epson Corporation Liquid crystal display device, method of manufacturing the same and electronic equipment
KR100492726B1 (en) * 1998-01-26 2005-08-31 엘지.필립스 엘시디 주식회사 System on panel liquid crystal display

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1420285A2 (en) * 1997-04-21 2004-05-19 Seiko Epson Corporation Liquid crystal display device, method of manufacturing the same and electronic equipment
EP1420285A3 (en) * 1997-04-21 2004-07-14 Seiko Epson Corporation Liquid crystal display device, method of manufacturing the same and electronic equipment
US6954249B2 (en) 1997-04-21 2005-10-11 Seiko Epson Corporation Liquid crystal display device, method of manufacturing the same, and electronic equipment
KR100492726B1 (en) * 1998-01-26 2005-08-31 엘지.필립스 엘시디 주식회사 System on panel liquid crystal display
US7016010B2 (en) 1998-01-26 2006-03-21 Lg.Philips Lcd Co., Ltd. Method of fabricating a system-on-panel typed liquid crystal display

Similar Documents

Publication Publication Date Title
US5466617A (en) Manufacturing electronic devices comprising TFTs and MIMs
US7072018B2 (en) IC substrate of glass and display device
KR100376801B1 (en) A method for forming a semiconductor device
US6198133B1 (en) Electro-optical device having silicon nitride interlayer insulating film
US5311040A (en) Thin film transistor with nitrogen concentration gradient
US8547516B2 (en) Display device and method of fabricating the same
US7999262B2 (en) Thin film transistor, method of fabricating the same, and method of fabricating liquid crystal display device having the same
US7407838B2 (en) Method of manufacturing a semiconductor method of manufacturing a thin-film transistor and thin-film transistor
JPH08262475A (en) Production of display device
US5696387A (en) Thin film transistor in a liquid crystal display having a microcrystalline and amorphous active layers with an intrinsic semiconductor layer attached to same
JP3638656B2 (en) Display device and manufacturing method thereof
JPH08313935A (en) Lcd device of type integrated with cpu and its production
KR100492726B1 (en) System on panel liquid crystal display
US20040140469A1 (en) Panel of a flat display and method of fabricating the panel
JPH11271807A (en) Active matrix substrate and liquid crystal display
JPH0563026B2 (en)
KR100297063B1 (en) Display device and electronic device having the display device
KR100399617B1 (en) Method of manufacturing for polycrystalline- Silicon thin layer
US7271410B2 (en) Active matrix circuit
JP4094539B2 (en) Method for manufacturing semiconductor integrated circuit
JP3406894B2 (en) Method for manufacturing display device
JP4387258B2 (en) Semiconductor integrated circuit and manufacturing method thereof
KR101108773B1 (en) Liquid crystal display device and method for manufacturing the same
JP4339102B2 (en) Method for manufacturing display device
JP3406893B2 (en) Method for manufacturing display device

Legal Events

Date Code Title Description
A300 Application deemed to be withdrawn because no request for examination was validly filed

Free format text: JAPANESE INTERMEDIATE CODE: A300

Effective date: 20020806