JPH08305580A - Language processing unit for parallel program - Google Patents

Abstract

PURPOSE: To provide the parallel program language processing unit converting a program so that efficient parallel processing is executed with less number of times of awaiting a synchronizing signal in a chaining calculation process. CONSTITUTION: A source program converted into an internal expression by a syntax analyzer 1 is converted in parallel operation by a parallel computer system comprising plural processors having a local memory and the program is converted into an object program by an object code generator 3 and the converted program is outputted. In this case, the transfer of operands on the way of the processing is eliminated by converting the program so that an operand matrix required for the processing of an allocated part of each processor by a data transfer code insert device 4 is transferred before the start of the processing in each local memory, and part of the intermediate result of the processing is calculated in duplicate by allowing plural processors to calculate it by a calculation processing division allocation device 5 so as to eliminate transfer of the intermediate result on the way of the processing.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parallel program language processing apparatus for converting a source program into an object program which operates in parallel in a parallel computer system composed of a plurality of processors having a local memory.

[0002]

2. Description of the Related Art When a program is executed in a parallel computer system including a plurality of processors having a local memory, an array holding an operand and a result of a calculation process in the program is divided into disjoint partial arrays. However, it is assigned to each of the plurality of programs, and each processor executes only the update calculation process of the sub-array that is shared by itself, that is, the owner calculation rule (owner calculation rule).
Parallel processing based on the compute rule is widely performed. A programming language processing system based on the owner calculation rule is described, for example, in “Languages, Comp.
illers and Run-Time Enviro
nments for Distributed Me
more Machines (Salts, Mehro
tra co-edited, 1992) ”, pp. 139-176,
"Compiler Support for Mach
ine-Independent Parental
Programming in Fortran D "
Has been proposed to.

In the parallel processing of this system, when one processor needs an operand in the partial array assigned to another processor to perform a calculation process, transfer processing of the operand between the processors is performed. Will be needed.

[0004]

In the conventional parallel processing described above, when one processor needs an operand to be operated on a partial array allocated to another processor in order to perform a calculation process, the processor is divided between the processors. Since the transfer processing of the operand is required and the calculation processing cannot be started until the transfer processing is completed, a synchronization wait occurs accordingly. However, in a chained calculation processing process as seen in a normal program, that is, in a calculation processing process in which the result of one calculation process is the operand of the next calculation process, the There is a problem that transfer occurs, and the number of times of waiting for synchronization between processors increases due to the transfer, and the efficiency of parallel processing is impaired.

FIG. 7 shows the flow of data when the program shown in FIG. 4 to be described later is processed by the conventional programming language processor shown in FIG. 6 and executed by a parallel computer system composed of a plurality of programs having local memories. Shows.
In FIG. 7, the arrays A, B, C, and D are divided into 10 equal parts, and continuous
A second processor (array element numbers 101 to 200) when 00 elements are allocated to 10 processors
Is held). Each rectangular cell represents an array element, and the number inside is the element number. The arrows indicate the flow of data, and the lower element is calculated from the upper element in each step.

In FIG. 7, data transfer is not required for the calculation of B and C in step 1, but D is used in step 2.
It can be seen that a total of 4 elements, 2 elements each of B and C, must be transferred from another processor in order to calculate Since the transfer processing cannot be started until these are calculated on the processor of the transfer source, synchronization waiting between processors occurs between step 1 and step 2, and the efficiency of parallel processing is impaired.

In view of the above points, an object of the present invention is to provide a parallel program language processing apparatus for converting a program so that efficient parallel processing can be performed with a small number of synchronization waits in a chain of calculation processing steps. To do.

[0008]

In the parallel programming language processing apparatus of the first invention, an array required for each processor to perform the processing is stored in each local memory for each chained processing unit in the source program. In addition, the program is converted such that data is transferred between the processors so as to be prepared before the start of the processing unit, and a part of the calculation processing that handles the array is executed by a plurality of processors in an overlapping manner.

In the parallel programming language processing apparatus of the second invention, when the array of the source program is divided and arranged in the processor, a part of the array is redundantly arranged in a plurality of processors and one of the calculation processes for handling the array. It is characterized in that a program is converted so that a plurality of processors can be executed in duplicate.

[0010]

In the first aspect of the invention, for each chained processing unit in the source program, an array required for each processor to perform the processing is prepared in each local memory before the processing unit is started. By thus transferring data between the processors, it is possible to eliminate the need for transferring the data of the operand in the middle of a series of calculation processes. In addition, by causing a part of the calculation processing that handles the array to be executed by multiple processors in duplicate, it is an intermediate result that is generated in the process of the chained calculation processing and is necessary for the subsequent processing of each processor. The parts are respectively calculated using only the data on the local memory of each processor, eliminating the need for data transfer of intermediate results in the middle of a series of calculation processes.

In the second invention, by arranging a part of the array so as to be overlapped with a plurality of processors, all the operands required for the calculation processing are prepared on the local memory before the start of the processing, Eliminates the need for data transfer of the operand in the middle of the calculation process. In addition, by causing a part of the calculation processing that handles the array to be executed by multiple processors in duplicate, it is an intermediate result that is generated in the process of the chained calculation processing and is necessary for the subsequent processing of each processor. The parts are respectively calculated using only the data on the local memory of each processor, eliminating the need for data transfer of intermediate results in the middle of a series of calculation processes.

[0012]

EXAMPLES Examples of the present invention will be described with reference to FIGS. FIG. 1 shows a schematic configuration of an embodiment of the first invention. In this embodiment, a syntax analysis device 1 for converting an input Fortran program into an internal representation of the device,
A program conversion device 2 for converting an internally expressed source program into an internally expressed parallelized program that operates in parallel in a parallel computer system consisting of a plurality of processors having local memories, and an internal expression equivalent to it.
A target code generation device 3 that converts and outputs the tran target program, and for each processing unit of the internally expressed program, an array required for each processor to perform the processing is stored in each local memory before the start of the processing unit. , A data transfer code insertion device 4 for inserting a data transfer code for transferring data between the processors and a part of the calculation process for handling the array of the program represented by the internal representation data are duplicated by the plurality of processors. It is composed of a calculation processing divisional allocation device 5 that performs division / allocation so as to be executed.

The Fortran original program, which is an input to this apparatus, is given to the syntax analysis apparatus 1. The syntax analysis device 1 detects the grammar of the source program, converts the source program into an internal representation used in the entire device, and passes it to the program conversion device 2. The program conversion device 2 analyzes the passed source program and determines the method of dividing and arranging the array in the program by the conventional method. Since the method of dividing the array is determined, the method of dividing the calculation process is also automatically determined at this point according to the owner calculation rule.

Next, the program conversion device 2 passes the program to the data transfer code insertion device 4. The data transfer code insertion device 4 divides the delivered program into subroutines and other logical processing units, and for each processing unit, an array that is the minimum required for each processor to perform the processing, that is, Input data is obtained, and a code for transferring data between processors is inserted so that the input data is prepared in each local memory before the start of the processing unit. When obtaining the input data, even if the intermediate result of the process is calculated by another processor, it is treated as being calculated by the own processor. This eliminates the need for data transfer midway through the processing unit.

The program into which the data transfer code has been inserted by the data transfer code insertion device 4 is then passed to the calculation processing divisional allocation device 5. Here, based on the division method of the calculation process determined by the owner calculation rule, the program is actually converted so that each processor executes only its own portion. Further, the program is adjusted so that the data transfer code insertion device 4 actually causes the self processor to perform the calculation processing of the intermediate result, which has been treated as being calculated in the self processor as described above. Since this calculation process is naturally performed also in the processor that should perform it, as a result, the calculation process is redundantly executed by a plurality of processors.

The program parallelized by the above processing is returned to the program conversion device 2 again, adjusted as in a normal language processing device, and finally passed to the object code generation device 3. And output Fo
Converted to rtran object program.

FIG. 2 shows the configuration of the data transfer code insertion device 4. The data transfer code insertion device 4 includes a calculation processing sectioning unit 41 that divides the program delivered from the program conversion device 2 into processing units designated in the subroutine unit or the text of the source program, and the calculation processing sectioning unit 41. By tracing the control flow of the program while considering the definition / reference relationship of the data for each divided processing unit, the minimum data required for the calculation processing of the processor equivalent part of the array that is the final result of the processing unit. Data that is not assigned to the local memory of each processor in the data set obtained by the data flow analysis unit 42 for each processing unit divided by the data flow analysis unit 42 that obtains a set and the calculation processing sectioning unit 41 At the beginning of the relevant processing unit. Composed data transfer instruction insertion unit 43.

The calculation processing sectioning unit 41 divides the program into sub-routine units or processing units designated on the text of the source program, and transfers the processing units to the data flow analysis unit 42. In the data flow analysis unit 42, the passed processing unit is “Compilers-Prim”.
nciples, Techniques, and To
ols (Aho et al., 1986) ”, which is analyzed by the data flow analysis method described in Chapter 10, and the final result array of the processing unit and its index range are obtained from the definition set reaching the exit of the processing unit. Then, by starting from the element of the part in charge of the final result for each processor and going backward in the data flow, the set of array elements that should be prepared at the entrance of the processing unit to calculate the element is calculated. Ask. At this time, if there is an intermediate result of the calculation which is not allocated to the own processor, it is recorded and the calculation processing division allocation device 5
At that time, the code is adjusted based on the information so that the intermediate result is calculated by the own processor. In the data transfer instruction insertion unit 43, of the set of array elements that should be prepared at the entrance of the processing unit obtained by the data flow analysis unit 42, which is not assigned to the processor, at the beginning of the processing unit. Insert an instruction to transfer data from the processor that owns the element.

FIG. 3 shows a schematic configuration of an embodiment of the second invention. This embodiment is compared with the embodiment of the first invention of FIG.
The difference is that an array data division allocation device 6 is used instead of using the data transfer code insertion device 4.
In the array data division and allocation device 6, instead of transferring data between processors during execution, arrays required for each processor to perform the processing are prepared on each local memory at the start of execution of the program. Change the division method itself. Here, the method of dividing the array is determined by the method of data flow analysis or the method instructed on the text of the source program.

The effect of the present invention will be described by taking the Fortran program shown in FIG. 4 as an example. This program is divided into two stages. In step 1, the operand A to the intermediate result B
And C are calculated, and the final result D is calculated from B and C in step 2.
Is calculated.

FIG. 5 is a data flow when the program of FIG. 4 is processed by the programming language processing device of the first invention and is assigned to the processor under the same condition to be executed. Elements A (100) and A (20) that do not exist in the own processor
1) is transferred prior to step 1, and the calculation that is not originally assigned to the processor itself in step 1 (the part surrounded by an ellipse in the figure) is also performed, so that all data can be transferred without data transfer in the middle of the process. The calculation can be performed in its own processor. Therefore, synchronization waiting does not occur in the middle of processing, and the efficiency of parallel processing is improved by the present invention.

If the array A is assigned to the processor in the range of A (100) to A (201) in advance according to the second aspect of the invention, the data transfer before the start of step 1 becomes unnecessary, and the parallel processing is further performed. Efficiency is improved.

The present invention is not limited to the above embodiment. For example, the input language may be the language of any program having an array structure, and the output may be any of the programming language, machine objects, and executable code. Further, the respective constituent elements of the embodiment do not have to be clearly separated, and a part may be shared with other constituent elements. In addition, the present invention can be variously modified and implemented without departing from the gist thereof.

[0024]

As described above, according to the first aspect of the invention, all calculations can be performed in the processor itself without transferring data in the middle of processing, and therefore, in the middle of processing, synchronization waiting is performed. Does not occur, and the efficiency of parallel processing is improved.

According to the second aspect of the invention, since the data transfer before the start of step 1 becomes unnecessary, the efficiency of parallel processing is further improved.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an embodiment of a first invention.

FIG. 2 is a configuration diagram showing an example of a data transfer code insertion device shown in FIG.

FIG. 3 is a configuration diagram showing an embodiment of the second invention.

FIG. 4 is an example of a program for explaining the effect of the present invention.

FIG. 5 is a diagram showing how a program processed by the device of the present invention is executed.

FIG. 6 is a configuration diagram of a conventional device.

FIG. 7 is a diagram showing how a program processed by a conventional device is executed.

[Description of Codes] 1 syntax analysis device 2 program conversion device 3 object code generation device 4 data transfer code insertion device 5 calculation processing division allocation device 6 array data division allocation device 41 calculation processing sectioning unit 42 data flow analysis unit 43 data transfer Instruction insertion part

Claims (3)

[Claims] 1. A programming language processing device comprising a program conversion device for converting a source program into a parallelized program that operates in parallel in a parallel computer system comprising a plurality of processors equipped with local memories. , A group of data (array) required for each processor to perform the processing is calculated for each processing unit (chain processing unit) such that the result of a certain calculation processing becomes the operand of the next calculation processing. A data transfer code insertion device that inserts a data transfer code into a program that allows data transfer between processors so that it is prepared in the local memory before the start of the processing unit, and a part of the calculation processing that handles the array is performed by a plurality of parts. And a device for converting a program to be executed by the processor in duplicate. Parallel programming language processing apparatus. 2. The programming language processing device according to claim 1, wherein the data transfer code insertion device divides the program passed from the program conversion device into subroutine units or processing units instructed on the text of the source program. The final result of the processing unit is obtained by tracing the control flow of the program while considering the definition / reference relationship of the data for each calculation processing sectioning unit and the processing unit divided by the calculation processing sectioning unit. A data flow analysis unit that obtains a minimum required data set for the calculation processing of each processor-corresponding portion of the array, and a data set obtained by the data flow analysis unit for each processing unit divided by the calculation processing sectioning unit Owns data that is not allocated in the local memory of each processor Parallel programming language processing device, comprising: a data transfer instruction insertion unit that inserts an instruction to be transferred from the processor to the head of the processing unit. 3. A programming language processing apparatus for converting a source program into a target program which operates in parallel in a parallel computer system comprising a plurality of processors having a local memory, in which an array of source programs is divided and arranged in processors. , A device that converts a program so that a part of the array is overlapped with a plurality of processors, and a device that converts a program so that a part of the calculation processing that handles the array is executed by a plurality of processors redundantly. A parallel programming language processing device characterized by being provided.