JPH0830439A - Method for performing double-precision multiplication and arithmetic unit - Google Patents

Abstract

PURPOSE:To obtain the result of accurate multiplication between signed binary numbers of double precision by a single-precision multiplier. CONSTITUTION:The high-order and low-order words of a multiplicand X are denoted as XH and XL and the high-order and low-order words of a multiplier Y are denoted as YH and YL; and the products XLXYL, XLXYH, XHXYL, and XHXYH are found in order and added while the places are matched with one another. A multiplicand latch R1 and a multiplier latch Rs of one-word length, a multiplier MSB latch R3 for holding the MOSB of the YL, and a recoding part 11 which applies a the 2-bit Boothis method to the recoding of the multiplier are provided. The recoding part 11 is supplied with '0' for the recording of the low-order two bits of the YL in cases of XLXYL and XHXYL and with the output of the multiplier MSB latch R3 for the recoding of the low-order two bits of the YH in cases of XLXYH and XHXYH. A multiplication processing part 12 for the generation and addition of partial products processes the XL as an unsined binary number and the XH as a binary number in complement notation of 2 respectively according to a muliplicand polarity inversion signal C2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and an arithmetic unit for executing double precision multiplication, and more particularly to execution of double precision multiplication using a single precision multiplier.

[0002]

2. Description of the Related Art In recent years, development of a high-speed digital signal processor (DSP) has been developed as one of hardware for performing high-speed and large-volume digital signal processing in the fields of communication and image processing. It is progressing. In particular, a DSP is required to be able to execute multiplication-related instructions such as multiplication instructions and product-sum operation instructions at high speed.

Naoki Takagi et al. "V using a redundant binary addition tree"
High-speed Multiplier for LSI "(Journal of the Institute of Electronics and Communication Engineers, Vol.
J66-D No. 6 June 1983 pp. 683
-690), a parallel multiplier using a redundant binary representation for internal calculation is proposed. According to the usual binary representation,
Each digit has a value of 0 or 1. On the other hand, in redundant binary representation, a digit with a sign (SD: Signed Digit) is adopted,
Each digit has a value of -1, 0 or 1. This redundant binary representation is a radix-2 SD representation and is also called a binary SD representation. In order to reduce the number of partial products, the radix-4 SD expression, that is, the quaternary SD expression is adopted as the internal expression of the multiplier by utilizing the 2-bit Booth method. In the quaternary SD representation, each digit has a value of -2, -1, 0, 1 or 2.

The parallel multiplier of Takagi et al. Comprises a multiplier recoding circuit, a partial product addition tree, and a redundant binary number / binary number converting circuit. The partial product addition tree is composed of a partial product generation circuit and a redundant binary number addition circuit. According to this multiplier, when the multiplication of the multiplicand and the multiplier, each of which is represented in binary of 2's complement, is performed, the binary number in 2's complement notation, which is a multiplier, is calculated by the multiplier recoding circuit according to the rule of Table 1. Is recoded into a quaternary SD number. Then, the partial product generation circuit generates a partial product of redundant binary representation from the multiplicand and the result of the multiplicand recoding. At this time, since one partial product is generated for each digit of the multiplier expressed in the quaternary SD representation, the number of partial products is half that in the binary representation. Moreover, redundancy 2
Since the carry propagation is suppressed due to the redundancy in the decimal addition circuit, the multiplication result can be obtained at high speed. The output of the partial product addition tree (the product of the redundant binary representation) is converted into a binary representation of 2's complement by a redundant binary number / binary number conversion circuit.

[0005]

[Table 1]

Conventionally, a single precision multiplier is sometimes used to execute double precision multiplication. The double-precision multiplier has a larger circuit scale than the single-precision multiplier. Therefore, considering the hardware cost, the area occupied on the chip, the power consumption, the execution frequency of double-precision multiplication, etc., the single-precision multiplier is repeatedly used to obtain the result of double-precision multiplication. It was.

FIG. 4 shows a conventional double-precision multiplication execution method using a single single-precision multiplier. The multiplication of the double precision multiplicand X and the double precision multiplier Y, which are each represented by the binary representation of 2's complement, is executed. The multiplicand X and the multiplier Y are both 2
It is a fixed-point number of word length. The multiplicand X is composed of the upper word XH and the lower word XL, and the multiplier Y is composed of the upper word YH and the lower word YL. 1 word is
It is composed of n digits (n is an even number, for example, 16). Product X × Y
Is obtained by digit-matching addition of four products XL × YL, XL × YH, XH × YL and XH × YH.

Now, the multiplicand lower word XL is an unsigned binary number, and unlike the binary number of 2's complement notation in which the most significant bit (MSB) represents the sign, all bits should be treated as significant digits. It is a thing. Multiplier lower word YL
Is also an unsigned binary number. However, in the conventional multiplier, the given multiplicand and multiplier are each represented by the two's complement of two.
As a result of treating it as a base number, if the multiplicand lower word XL having MSB of 1 is input as it is to the multiplier or the multiplier lower word YL having MSB of 1 is input as it is to the multiplier, a correct product cannot be obtained.

Therefore, conventionally, as shown in FIG. 4, in order to avoid an erroneous operation, the multiplicand lower word XL is unavoidable.
And the least significant bit (LS) of each of the multiplier lower word YL.
B) was thrown away. More specifically, the lower-order word XL of the multiplicand is right-shifted by one digit. At this time, the MSB of the multiplicand lower word XL is set to 0 and its LSB is discarded. The new multiplicand lower word XL 'thus obtained is used in place of the original multiplicand lower word XL. Further, the lower digit of the multiplier YL is shifted by one digit to the right. At this time, the MSB of the multiplier lower word YL is set to 0 and the LSB is discarded. The new multiplier lower word YL 'thus obtained is the original multiplier lower word YL.
Used in place of L. And four products XL '× YL',
The double precision multiplication result is obtained by the digit-matching addition of XL '* YH, XH * YL' and XH * YH. For the recoding process of the least significant 2 bits of the multiplier upper word YH,
The value 0 is used as a further lower bit, as in the case of recoding the least significant 2 bits of the multiplier lower word YL.

[0010]

In the conventional double precision multiplication execution method using the single single precision multiplier described above, the multiplicand lower word XL and the multiplier lower word Y are avoided in order to avoid an erroneous operation.
Since each LSB of L is thrown away, there is a problem that the operation result includes an error of maximum 2 ^{− (2n−2)} .

It is an object of the present invention to be able to perform accurate double precision multiplication using a single single precision multiplier.

[0012]

In order to achieve the above object, the present invention provides an arithmetic unit having a single single-precision multiplier, in the case where the MSB of the multiplier lower word YL is 1, the multiplier lower word. In order not to cause a problem even if the quaternary SD number which is the conversion result of YL becomes a negative number, the MSB of the multiplier lower word YL is reflected in the recoding process of the least significant 2 bits of the multiplier upper word YH. It is a thing. Further, in the arithmetic unit, the multiplicand lower word XL is treated as an unsigned binary number, and the multiplicand upper word XH is treated as a two's complement binary number.

More specifically, the double-precision multiplication executing method according to the invention of claim 1 comprises an arithmetic operation comprising a binary-corresponding binary code unit for each two-complement representation for single-precision multiplication and a multiplication processing unit. A method for performing a multiplication of a double-precision multiplicand X and a double-precision multiplier Y, each represented by a binary representation in two's complement, in a device, the method comprising the step of storing the MSB of the multiplier lower word YL; To convert the representation of the word YL into a quaternary SD representation and to process the least significant 2 bits of the multiplier lower word YL, the value 0 as a further lower bit.
And a step of recoding the lower word of the multiplier YL in the recoding section, and a partial product of one word (XL or XH) of the multiplicand X and the lower word of the multiplier YL subjected to the recoding is generated. The first multiplication result (XL ×
YL or XH xYL), converting the representation of the multiplier upper word YH into a quaternary SD representation and processing the least significant 2 bits of the multiplier upper word YH as the further lower bits. A step of recoding the multiplier upper word YH in the recoding unit using the MSB of the multiplier lower word YL, and one word (XL or XH) of the multiplicand X and the multiplier upper word YH subjected to the recoding. Generating a second partial product and adding the generated partial products together to obtain a second multiplication result (XL × YH or XH × YH) in the multiplication processing unit,
And a step of executing double precision digit-matching addition of the first and second multiplication results.

According to the second aspect of the present invention, in each of the steps of obtaining the first and second multiplication results, the multiplicand lower word XL is exceptionally unsigned 2 in the multiplication processing unit.
We decided to process it as a decimal number.

According to the third aspect of the invention, in each of the steps of obtaining the first and second multiplication results, the multiplicand upper word XH is processed as a binary number in a two's complement representation by the multiplication processing unit.

According to the invention of claim 4, the step of storing the MSB of the multiplier lower word YL and the recoding processing to the multiplier lower word YL are performed so that the step of performing the recoding processing on the multiplier upper word YH can be activated. And a step of setting a lower-order multiplication execution flag at the completion of the step of applying and the step of obtaining the first multiplication result.

The arithmetic unit according to the invention of claim 5 is
Double precision multiplicand X, each of which is a binary representation of 2's complement
And a double-precision multiplier Y, which is an arithmetic unit for performing the following multiplicand latch means, multiplier latch means, multiplier MSB latch means, selecting means, recoding means, and multiplying means. , A configuration including a digit alignment and addition means is adopted. That is, the multiplicand latch means is
The multiplicand lower word XL and the multiplicand upper word XH are selectively retained. The multiplier latch means selectively holds the multiplier lower word YL and the multiplier upper word YH. The multiplier MSB latch means holds the MSB of the multiplier lower word YL. The selecting means outputs a value of 0 when the multiplier lower word YL is held in the multiplier latch means, and outputs the multiplier MSB latch means when the multiplier lower word YL is held (in the multiplier lower word YL). MSB) is selectively output. The recoding means outputs the output of the multiplier latch means (YL or YH).
Is converted to a quaternary SD representation, and the least significant 2 bits of the output of the multiplier latch means are processed as further lower bits by the output of the selecting means (MS of 0 or YL).
B) is used to recode the output of the multiplier latch means. The multiplication means generates a partial product of the output of the multiplicand latch means (XL or XH) and the output of the recoding means, and adds the generated partial products to hold the lower multiplier word YL in the multiplier latch means. If the multiplier latch means holds the multiplier high-order word YH, the second multiplication result (XL × YH or XH × XL × YL or XH × YL) is obtained.
YH). The digit-matching addition means executes double-precision digit-matching addition of the first and second multiplication results obtained by the multiplication means.

In the sixth aspect of the present invention, when the multiplicand latch means holds the multiplicand lower word XL, the multiplying means processes the multiplicand lower word XL as an unsigned binary number and the multiplicand latch means. Upper word X
When H is retained, it is provided with a function of processing the multiplicand high order word XH as a binary number in 2's complement notation.

According to a seventh aspect of the present invention, the digit aligning and adding means is an aligner for performing a right shift process on the first multiplication result, a first multiplication result after the right shift process, and the first aligning result. An adder for executing double precision addition with the multiplication result of 2 is provided.

According to the eighth aspect of the present invention, the lower multiplication execution flag is set when the first multiplication result is calculated based on the multiplier lower word YL so as to indicate that the processing of the multiplier upper word YH can be started by the recoding means. Is further provided with status register means for storing

[0021]

According to the invention of claim 1, the multiplier lower word YL
The value 0 is used as the further lower bit for the recoding process of the least significant 2 bits of the above, and the MSB of the multiplier lower word YL is used as the further lower bit for the recoding process of the least significant 2 bits of the multiplier upper word YH. That is, the multiplier upper word YH and the multiplier lower word YL are treated as a series of signed double-precision numbers, and as a result, in the arithmetic unit having a single single-precision multiplier, the MSB of the multiplier lower word YL is one. Also, an accurate double precision multiplication result reflecting the entire lower word of the multiplier YL can be obtained.

According to the invention of claim 2, the generation of partial products
In addition, the multiplicand lower word XL is exceptionally treated as an unsigned binary number. As a result, even if the MSB of the multiplicand lower word XL is 1, the products XL × YL and XL ×
YH is calculated correctly.

According to the invention of claim 3, the generation of partial products
Upon addition, the multiplicand upper word XH is treated as a binary number in 2's complement notation. As a result, the multiplicand upper word X
Depending on the MSB value of H, the product XH xYL and XH xYH
Is calculated correctly.

According to the fourth aspect of the present invention, the lower multiplication execution flag is set at the time when the series of processes for the multiplier lower word YL is completed. If the lower-order multiplication execution flag is set, the arithmetic unit is set to an operation other than the double-precision multiplication before the remaining steps of the double-precision multiplication starting from the step of recoding the multiplier upper-order word YH are executed. Available. Further, if the set of the lower multiplication execution flag can be recognized, it is confirmed that the MSB of the multiplier lower word YL may be used as a further lower bit for the recoding process of the lowest 2 bits of the multiplier upper word YH.

According to the fifth aspect of the present invention, the value 0 is sent from the selecting means to the recoding means when the multiplier lower word YL is recoded, and the output of the multiplier MSB latch means, that is, the multiplier lower word YL is processed when the multiplier upper word YH is recoded.
MSB of each is supplied. As a result, the multiplier high-order word YH and the multiplier low-order word YL are treated as a series of signed double-precision numbers, and as a result, the multiplication means is capable of inputting a single-precision number, but is an accurate double that reflects the entire multiplier low-order word YL. The precision multiplication result is obtained.

According to the sixth aspect of the present invention, the multiplicand lower word X is generated when the partial products are generated and added by the multiplication means.
The multiplicand upper word XH is 2 as L is an unsigned binary number
Are treated as binary numbers in the complement notation. That is, as a result of the multiplicand upper word XH and the multiplicand lower word XL being treated as a series of signed double-precision numbers, the MS of the multiplicand low-order word XL can be obtained while the multiplying means is capable of inputting single-precision numbers.
Even if B is 1, an accurate double precision multiplication result that reflects the entire lower word of the multiplicand XL is obtained.

According to the invention of claim 7, in adding the first and second multiplication results sequentially obtained by the multiplication means,
The first multiplication result (XL × YL or XH for digit alignment)
XYL) is right-shifted, and the result of the right-shifting and the second multiplication result (XL × YH or XH × YH)
) And double precision addition are performed.

According to the eighth aspect of the present invention, the lower multiplication execution flag in the state register means is set when the first multiplication result based on the multiplier lower word YL is calculated. When the lower-order multiplication execution flag is set, for example, the digit-matching addition means can be used for operations other than the double-precision multiplication before executing the process of calculating the second multiplication result based on the multiplier upper-order word YH. Further, if the setting of the lower multiplication execution flag can be recognized at the start of the process of calculating the second multiplication result, it is confirmed that the output of the multiplier MSB latch means (the MSB of the multiplier lower word YL) should be supplied from the selecting means to the recoding means. To be done.

[0029]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a multiplier upper word YH in a double precision multiplication execution method according to the present invention using a single single precision multiplier.
FIG. 7 is an explanatory diagram showing a method of recoding a multiplier lower word YL.

When performing a multiplication of a double precision multiplicand X and a double precision multiplier Y, each of which is represented by a binary representation of 2's complement,
The multiplier lower word YL is recoded into a quaternary SD number according to the rules of Table 1 above. The value 0 is used as a further lower bit in the recoding process of the least significant 2 bits YL1 and YL0 of the multiplier lower word YL. Multiplier high word YH
Is also recoded into a quaternary SD number according to the rules of Table 1.
However, the least significant 2 bits YH1 and Y of the multiplier upper word YH
For the H0 recoding process, the value 0 is set as the further lower bit.
Instead, the MSB of the lower word of the multiplier YL, that is, YLn-1 is used. That is, the multiplier upper word YH and the multiplier lower word YL are treated as a series of signed double-precision numbers. As a result, when the MSB (YLn-1) of the multiplier lower word YL is 1, the conversion result of the multiplier lower word YL Is a quaternary SD
There is no problem even if the number becomes negative.

The two arithmetic units according to the embodiments of the present invention to which the recoding method of FIG. 1 is applied will be sequentially described below.

(Embodiment 1) FIG. 2 shows a first embodiment of the present invention for executing multiplication of a double precision multiplicand X and a double precision multiplier Y, each of which is represented by a binary representation of 2's complement. It is a block diagram of the arithmetic unit which concerns. Both the multiplicand X and the multiplier Y are fixed-point numbers having a 2-word length. The multiplicand X is composed of the upper word XH and the lower word XL, and the multiplier Y is composed of the upper word YH and the lower word YL. One word is composed of n digits (n is an even number, for example, 16).

In FIG. 2, reference numeral 31 is a storage device having three ports, and 32 and 33 are first and second data buses connected to the storage device 31. Multiplicand X and multiplier Y
Are stored in the storage device 31.

R1 to R7 are all latches. Of these, R1 is a 1-word length multiplicand latch for holding data on the first data bus 32, R2 is a 1-word length multiplier latch for holding data on the second data bus 33, and R3 Is a 1-bit length multiplier MSB latch for holding the MSB of the multiplier latch R2, R4 is a 2-word length multiplication result latch, and R5 and R6 are first 2-word lengths, respectively.
And a second adder input latch, R7 is a 2-word long addition result latch.

Numeral 11 is a representation of the output of the multiplier latch R2.
It is a recoding unit for performing recoding processing on the output of the multiplier latch R2 so as to convert it into a base SD expression. 12
Is a multiplication processing unit for generating a partial product of the output of the multiplicand latch R1 and the output of the recoding unit 11 and adding the generated partial products to obtain a multiplication intermediate result. The output of the multiplication processing unit 12 is held in the multiplication result latch R4. 13 is an aligner for outputting the output of the first adder input latch R5 as it is, or for performing a right shift process on the output of the first adder input latch R5, or outputting a two-word constant "0". Is. 14 is the second
Is an adder for executing double-precision addition of the output of the adder input latch R6 and the output of the aligner 13.

Reference numerals 21 to 24 are all selectors. Of these, 21 is a first selector that supplies the output of the multiplier MSB latch R3 or the 1-bit constant "0" to the recoding unit 11 for the recoding process of the least significant 2 bits. 22
Is a second selector for selectively outputting the upper word or the lower word of the addition result latch R7. Second selector 2
The output of 2 is stored in the storage device 31. Reference numeral 23 is a first adder input selector that outputs the output of the addition result latch R7 or the data on the first data bus 32 to the first adder input latch R5. 24 is a multiplication result latch R4
2 or the data on the second data bus 33 is output to the second adder input latch R6.

41 is an instruction decoding and control unit, 42 is a status register, 43 is a lower multiplication execution flag, and 44 is an AND.
It is a gate. The instruction decoding and control unit 41 has a function of decoding an instruction and setting a lower multiplication execution flag 43 provided in the state register 42. The instruction decoding and control unit 41 also includes first and second read data addresses RA1 and RA2, write data address WA, multiplication input latch enable signal E1, multiplication result latch enable signal E2, and first and second adders. Input latch enable signals E3A, E3B, addition result latch enable signal E4, multiplier MSB latch enable signal E5, first to fourth selector control signals S1 to S
4. Aligner control signal C1 and multiplicand polarity inversion signal C2 are output.

The first read data address RA1 is written for reading data to the first data bus 32, and the second read data address RA2 is written for reading data to the second data bus 33. The data address WA is provided to the storage device 31 for writing the output of the second selector 22.

The multiplication input latch enable signal E1 is commonly applied to the multiplicand latch R1 and the multiplier latch R2 so as to hold the data on the first and second data buses 32 and 33. The multiplication result latch enable signal E2 holds the output of the multiplication processing unit 12 so as to hold the multiplication result latch R.
Given to 4. The first adder input latch enable signal E3A is stored in the first adder input latch R5 so that the output of the first adder input selector 23 is held, and the second adder input latch enable signal E3B is stored in the second adder input latch enable signal E3B. It is applied to the second adder input latch R6 so as to hold the output of the adder input selector 24, respectively. The addition result latch enable signal E4 is given to the addition result latch R7 so as to hold the output of the adder 14. Multiplier MSB latch enable signal E5 is applied to multiplier MSB latch R3 so as to hold the MSB of multiplier latch R2.

The first selector control signal S1 is input to the AND gate 44 together with the lower multiplication execution flag 43. The first selector 21 selects the output of the multiplier MSB latch R3 if the output of the AND gate 44 is "1" (High), and the 1-bit constant "0" if it is "0" (Low). Second to fourth selector control signals S2, S3
S4 is used for controlling selection in the second to fourth selectors 22, 23 and 24, respectively. Second selector 22
Selects the upper word of the addition result latch R7 if the second selector control signal S2 is "1", and selects the lower word of the addition result latch R7 if "2". The third selector 23 selects the output of the addition result latch R7 if the third selector control signal S3 is "1" and the data on the first data bus 32 if it is "0". The fourth selector 24 selects the output of the multiplication result latch R4 when the fourth selector control signal S4 is "1", and selects the data on the second data bus 33 when it is "0".

The aligner control signal C1 is a 2-bit signal for controlling the operation of the aligner 13. That is, if the aligner control signal C1 is "00", the aligner 13 outputs a 2-word constant "0". If the aligner control signal C1 is "01", the aligner 13 performs the right shift process on the output of the first adder input latch R5, and outputs the result of the right shift process. Aligner control signal C1 is "1"
If it is "0", the aligner 13 receives the first adder input latch R
The output of 5 is supplied to the adder 14 as it is.

The multiplicand polarity inversion signal C2 is supplied to the multiplication processing unit 1
This is a 1-bit signal for controlling the operation of No. 2. The multiplication processor 12 treats the output of the multiplicand latch R1 as an unsigned binary number if the multiplicand polarity inversion signal C2 is "1",
If it is "0", the output of the multiplicand latch R1 is treated as a binary number of 2's complement. Specifically, the multiplicand polarity inversion signal C
2 is the MSB of the multiplicand word in the partial product generation circuit and redundant binary number addition circuit that form part of the multiplication processing unit 12;
It is used for the sign inversion control of, or as a switching signal for addition and subtraction.

The arithmetic unit of FIG. 2 sequentially executes the seven instructions A to G shown in Table 2 to obtain four products XL × YL.
, XL × YH, XH × YL and XH × YH are sequentially obtained, and the product X × Y is obtained by digit-addition thereof. Table 2 shows the flow of data in the arithmetic unit and the processing contents of the multiplication processing unit 12 and the adder 14 for each instruction.

[0044]

[Table 2]

In Table 2, RA1-0 and RA1-1
Is the read address of the multiplicand lower word XL, RA1-
2 and RA1-2 are read addresses of the multiplicand upper word XH, and RA2-0 and RA2-2 are lower multiplier word Y.
The read address of L, RA2-1 and RA2-3, are the read addresses of the multiplier upper word YH. WA-0
WA-3 is a write address of a product X × Y having a length of 4 words. In the initial state, the lower multiplication execution flag 4
3, all latch enable signals E1 to E5, all selector control signals S1 to S4, and the multiplicand polarity inversion signal C2 are assumed to be "0". Further, the aligner control signal C1 is assumed to be "00".

The operation sequence of the arithmetic unit of FIG. 2 will be described in detail below.

First, the instruction A is the instruction decoding and control section 4.
It is decoded by 1. Instruction decoding and control unit 41
Depending on the decoding result of the instruction A, RA1-0 and R1
A2-0 is supplied to the memory device 31, and the multiplication input latch enable signal E1 and the multiplier MSB latch enable signal E are supplied.
5 is set to "1" and the first selector control signal S1 is set to "1"
And the multiplicand polarity inversion signal C2 is set to "1".

The storage device 31 has RA1-0 and RA2-.
The data XL and YL designated by 0 are output to the first and second data buses 32 and 33, respectively. The data XL output to the first and second data buses 32 and 33,
YL is a multiplicand latch R1 and a multiplier latch R2, respectively.
Is held. The MSB of the data YL is held in the multiplier MSB latch R3. Even if the first selector control signal S1 becomes "1", the output of the AND gate 44 becomes "0" because the lower multiplication execution flag 43 is "0", and the first selector 21 sets the 1-bit constant "0". Select and output. The data YL held in the multiplier latch R2 is recoded in the recoding section 11 by using the output of the first selector 21 as a further lower bit of the least significant 2 bits of the data YL. The recoded data YL is supplied to the multiplication processing unit 12 together with the data XL held in the multiplicand latch R1. The multiplication processing unit 12 executes generation of partial products of both data XL and YL and addition of the generated partial products. At this time, since the multiplicand polarity inversion signal C2 is "1", the data XL is treated as an unsigned binary number. Then, the product XL × YL is supplied to the multiplication result latch R4.

Further, the instruction decoding and control unit 41 sets the lower multiplication execution flag 43 in the status register 42 to "1".
Is set, the multiplication result latch enable signal E2 is set to "1", and the aligner control signal C1 is set to "00" so that the aligner 13 outputs a 2-word constant "0". The output XL × YL of the multiplication processing unit 12 is the multiplication result latch R4.
Is held.

Next, the instruction B is the instruction decoding and control unit 4.
It is decoded by 1. Instruction decoding and control unit 41
Depending on the decoding result of the instruction B, RA1-1 and R
A2-1 is supplied to the memory device 31, the multiplication input latch enable signal E1 is set to "1", the multiplier MSB latch enable signal E5 is set to "0", and the first and fourth selector control signals S1 and S4 are set to "1". , And multiplicand polarity inversion signal C
2 is set to "1", and the second adder input latch enable signal E3B is set to "1".

The storage device 31 includes RA1-1 and RA2-.
The data XL and YH designated by 1 are output to the first and second data buses 32 and 33, respectively. The data XL output to the first and second data buses 32 and 33,
YH is a multiplicand latch R1 and a multiplier latch R2, respectively.
Is held. Since the multiplier MSB latch enable signal E5 is "0", the MSB of the data YL held in the multiplier MSB latch R3 is not updated.

The product X held in the multiplication result latch R4
L × YL is supplied to the second adder input latch R6 through the second adder input selector 24 and held there. The adder 14 performs double-precision addition of the 2-word constant output “0” of the aligner 13 and the output of the second adder input latch R6. The addition result, that is, XL × YL is
It is supplied to the addition result latch R7.

On the other hand, when the first selector control signal S1 becomes "1", the logical product (output of the AND gate 44) of the first selector control signal S1 and the lower multiplication execution flag 43 becomes "1", The first selector 21 is a multiplier MSB
The output of the latch R3, that is, the MSB of the data YL is selectively output. The data YH held in the multiplier latch R2 is recoded in the recoding section 11 by using the output of the first selector 21 as a further lower bit of the least significant 2 bits of the data YH. The recoded data YH is
It is supplied to the multiplication processing section 12 together with the data XL held in the multiplicand latch R1. The multiplication processing unit 12 executes generation of partial products of both data XL and YH and addition of the generated partial products. At this time, since the multiplicand polarity inversion signal C2 is "1", the data XL is treated as an unsigned binary number. Then, the product XL × YH is supplied to the multiplication result latch R4.

Further, the instruction decoding and control section 41 sets the lower multiplication execution flag 43 in the status register 42 to "0".
Reset, the addition result latch enable signal E4 is set to "1", the multiplication result latch enable signal E2 is set to "1", and the aligner 13 sets the first adder input latch R
The aligner control signal C1 is set to "01" so that the output of 5 can be right-shifted. The output XL × YL of the adder 14 is held in the addition result latch R7, and the output XL × YH of the multiplication processing unit 12 is held in the multiplication result latch R4.

Next, the instruction C is the instruction decoding and control unit 4.
It is decoded by 1. Instruction decoding and control unit 41
Depending on the decoding result of the instruction C, RA1-2, RA
2-2 and WA-0 are supplied to the memory device 31, the multiplication input latch enable signal E1 and the multiplier MSB latch enable signal E5 are set to "1", and the first, third and fourth selector control signals S1, S3 are provided. S4 is set to "1", the multiplicand polarity inversion signal C2 is set to "0", and the first and second adder input latch enable signals E3A and E3B are set to "1".

The storage device 31 includes RA1-2 and RA2-.
The data XH and YL designated by 2 are output to the first and second data buses 32 and 33, respectively. The data XH output to the first and second data buses 32 and 33,
YL is a multiplicand latch R1 and a multiplier latch R2, respectively.
Is held. The MSB of the data YL is held in the multiplier MSB latch R3.

Since the second selector control signal S2 is "0", the addition result XL held in the addition result latch R7 is
The lower word (XL × YL) L of × YL is written in the storage device 31 through the second selector 22. The entire addition result XL × YL is supplied to the first adder input latch R5 through the first adder input selector 23 and held there. The aligner 13 right-shifts the output of the first adder input latch R5 so that the upper word of the output XL × YL of the first adder input latch R5 shifts to the lower side. , The result of the shift process, that is, rshift (XL × YL) is output. At this time, (XL × YL) L is discarded. On the other hand, the product XL × YH held in the multiplication result latch R4 is passed through the second adder input selector 24 to the second adder input latch R4.
6 and is held here. The adder 14 performs double precision addition of the output rshift (XL * YL) of the aligner 13 and the output XL * YH of the second adder input latch R6. The addition result, that is, XL × YH + rshift (XL ×
YL) is supplied to the addition result latch R7.

On the other hand, even when the first selector control signal S1 becomes "1", the output of the AND gate 44 becomes "0" because the lower multiplication execution flag 43 is "0", and the first selector 21 has 1 bit. Selects and outputs the constant "0". The data YL held in the multiplier latch R2 is recoded in the recoding section 11 by using the output of the first selector 21 as a further lower bit of the least significant 2 bits of the data YL. The recoded data YL is supplied to the multiplication processing unit 12 together with the data XH held in the multiplicand latch R1. The multiplication processing unit 12 executes generation of partial products of both data XH and YL and addition of the generated partial products. At this time, since the multiplicand polarity inversion signal C2 is "0", the data XH is treated as a binary number in 2's complement notation. Then, the product XH * YL is supplied to the multiplication result latch R4.

Furthermore, the instruction decoding and control section 41 sets the lower multiplication execution flag 43 in the status register 42 to "1".
Is set, the addition result latch enable signal E4 is set to "1", the multiplication result latch enable signal E2 is set to "1", and the aligner 13 sets the first adder input latch R
The aligner control signal C1 is set to "10" so that the output of No. 5 can be output as it is. Output of adder 14 XL x YH +
rshift (XL × YL) is held in the addition result latch R7, and the output XH × YL of the multiplication processing unit 12 is held in the multiplication result latch R4.

Next, the instruction D is the instruction decoding and control unit 4.
It is decoded by 1. Instruction decoding and control unit 41
RA1-3 and R1 depending on the decoding result of the instruction D.
A2-3 is supplied to the memory device 31, the multiplication input latch enable signal E1 is set to "1", the multiplier MSB latch enable signal E5 is set to "0", and the first, third and fourth selector control signals S1, S3 are set. , S4 are set to "1", the multiplicand polarity inversion signal C2 is set to "0", and the first and second adder input latch enable signals E3A and E3B are set to "1".

The storage device 31 includes RA1-3 and RA2-.
The data XH and YH designated by 3 are output to the first and second data buses 32 and 33, respectively. The data XH output to the first and second data buses 32 and 33,
YH is a multiplicand latch R1 and a multiplier latch R2, respectively.
Is held. Since the multiplier MSB latch enable signal E5 is "0", the MSB of the data YL held in the multiplier MSB latch R3 is not updated.

The entire addition result XL × YH + rshift (XL × YL) held in the addition result latch R7 is the first
Is supplied to the first adder input latch R5 through the adder input selector 23 and is held there. Aligner 13
Is the output of the first adder input latch R5 XL × YH + rs
Output hift (XL x YL) as is. On the other hand, the product XH * YL held in the multiplication result latch R4 is supplied to the second adder input latch R6 through the second adder input selector 24 and held there. The adder 14 is
Output of aligner 13 XL × YH + rshift (XL × YL)
And double-precision addition of the output XH * YL of the second adder input latch R6. The addition result, that is, XH xYL
+ XL * YH + rshift (XL * YL) is supplied to the addition result latch R7.

On the other hand, when the first selector control signal S1 becomes "1", the logical product (output of the AND gate 44) of the first selector control signal S1 and the lower multiplication execution flag 43 becomes "1", The first selector 21 is a multiplier MSB
The output of the latch R3, that is, the MSB of the data YL is selectively output. The data YH held in the multiplier latch R2 is recoded in the recoding section 11 by using the output of the first selector 21 as a further lower bit of the least significant 2 bits of the data YH. The recoded data YH is
It is supplied to the multiplication processing unit 12 together with the data XH held in the multiplicand latch R1. The multiplication processing unit 12 executes generation of partial products of both data XH and YH and addition of the generated partial products. At this time, since the multiplicand polarity inversion signal C2 is "0", the data XH is treated as a binary number in 2's complement notation. The product XH x YH is the multiplication result latch R
4 is supplied.

Further, the instruction decoding and control section 41 sets the lower multiplication execution flag 43 in the status register 42 to "0".
Reset, the addition result latch enable signal E4 is set to "1", the multiplication result latch enable signal E2 is set to "1", and the aligner 13 sets the first adder input latch R
The aligner control signal C1 is set to "01" so that the output of 5 can be right-shifted. The output XH * YL + XL * YH + rshift (XL * YL) of the adder 14 is held in the addition result latch R7, and the output XH * YH of the multiplication processing unit 12 is held in the multiplication result latch R4.

Next, the instruction E is the instruction decoding and control unit 4.
It is decoded by 1. Instruction decoding and control unit 41
Supplies WA-1 to the memory device 31 in accordance with the decoding result of the instruction E, sets the multiplication input latch enable signal E1 to "0", and sets the third and fourth selector control signals S3, S.
4 is set to "1" and the first and second adder input latch enable signals E3A and E3B are set to "1".

Since the second selector control signal S2 is "0", the addition result XH held in the addition result latch R7 is
XYL + XL xYH + rshift (XL xYL) lower word {XH xYL + XL xYH + rshift (XL xY
L)} L is stored in the storage device 31 through the second selector 22.
Is written to. Same addition result XH xYL + XL xYH + r
The entire shift (XL × YL) is supplied to the first adder input latch R5 through the first adder input selector 23 and held there. The aligner 13 outputs the output XH × YL + XL × YH + rshift of the first adder input latch R5.
The output of the first adder input latch R5 is right-shifted so that the upper word of (XL × YL) is shifted to the lower side, and the result of the shift processing, that is, rs
hift {XH xYL + XL xYH + rshift (XL xYL
)} Is output. At this time, {XH xYL + XL xYH
+ Rshift (XL xYL)} L is discarded. On the other hand, the product XH xYH held in the multiplication result latch R4 is
Is supplied to the second adder input latch R6 through the adder input selector 24 and is held there. Adder 14
Is the output rshift of the aligner 13 {XH xYL + XL xY
H + rshift (XL × YL)} and the output XH × YH of the second adder input latch R6 are subjected to double precision addition. The addition result, that is, XH xYH + rshift {XH xYL + X
L * YH + rshift (XL * YL)} is supplied to the addition result latch R7.

Further, the instruction decoding and control section 41 sets the addition result latch enable signal E4 to "1", the multiplication result latch enable signal E2 to "0", and returns the aligner control signal C1 to "00". Output of adder 14 XH ×
YH + rshift {XH xYL + XL xYH + rshift (XL
× YL)} is held in the addition result latch R7.

Next, the instruction F is the instruction decoding and control unit 4.
It is decoded by 1. Instruction decoding and control unit 41
Supplies WA-2 to the storage device 31 according to the decoding result of the instruction F and sets the first and second adder input latch enable signals E3A and E3B to "0".

Since the second selector control signal S2 is "0", the addition result XH held in the addition result latch R7 is
XYH + rshift {XH xYL + XL xYH + rshift (X
L * YL)} lower word [XH * YH + rshift
{XH xYL + XL xYH + rshift (XL xYL)}]
L is written in the storage device 31 through the second selector 22.

Further, the instruction decoding and control section 41 sets the addition result latch enable signal E4 to "0" and sets the second selector control signal S2 to "1".

Next, the instruction G is the instruction decoding and control unit 4.
It is decoded by 1. Instruction decoding and control unit 41
Supplies WA-3 to the storage device 31 in accordance with the result of decoding the instruction G.

Since the second selector control signal S2 is "1", the addition result XH held in the addition result latch R7 is
XYH + rshift {XH xYL + XL xYH + rshift (X
L × YL)} upper word [XH × YH + rshift
{XH xYL + XL xYH + rshift (XL xYL)}]
H is written to the storage device 31 through the second selector 22.

As described above, 7 instructions including 4 single precision multiplication instructions (instructions A to D) are sequentially executed to obtain 4
The word length double precision multiplication result X × Y is stored in the storage device 31. Moreover, according to this embodiment, the 1-bit constant "0" is output from the first selector 21 to the recoding unit 11 when the multiplier lower word YL is recoded, and the multiplier MSB latch R3 is output when the multiplier upper word YH is recoded. That is, since the MSBs of the multiplier lower word YL are supplied, the multiplier upper word YH and the multiplier lower word YL are treated as a series of signed double-precision numbers. Further, in the generation / addition of the partial products in the multiplication processing unit 12, the multiplicand lower word XL is treated as an unsigned binary number and the multiplicand upper word XH is treated as a two's complement binary number in accordance with the multiplicand polarity inversion signal C2. That is, the multiplicand upper word XH and the multiplicand lower word XL are treated as a series of signed double precision multipliers. Therefore, according to the arithmetic unit of this embodiment, although the multiplication processing unit 12 is capable of inputting a single-precision number, unlike the conventional case, it is possible to accurately reflect the whole of the multiplicand lower word XL and the multiplier lower word YL. A double precision multiplication result is obtained.

Further, according to this embodiment, when the multiplication based on the multiplier lower word YL is executed, the lower multiplication execution flag 43 in the state register 42 is set to "1", and the multiplication based on the multiplier upper word YH is performed. Since the lower multiplication execution flag 43 is reset to "0" when it is executed, the degree of freedom in programming is increased. For example, even when the instruction J not related to the double-precision multiplication is inserted between the instruction A and the instruction B described above and the instruction decoding and control unit 41 decodes the instructions A, J, and B in this order, the instruction B
The first selector 21 outputs the multiplier MSB latch R
The output of 3 can be selected correctly. Even when the instruction K not related to the double-precision multiplication is inserted between the instruction B and the instruction C and the instruction decoding and control unit 41 decodes the instructions B, K, and C in this order, the instruction C At the time of execution, the first selector 21 can correctly select the 1-bit constant "0".

The above instructions J and K may be addition instructions using the adder 14 and its peripheral circuits. For example,
When the third and fourth selector control signals S3 and S4 are set to “0”, the storage device 31 is connected to the first and second data buses 3 and 3.
It is also possible to directly lead the two pieces of data read out on 2, 33 to the adder 14 without going through the multiplicand latch R1 and the multiplier latch R2. However, addition result latch R7
In order not to destroy the intermediate result of the double-precision multiplication held in, the other addition result latch for holding the output of the adder 14 in the case of the addition instruction is provided.

(Embodiment 2) FIG. 3 shows a second embodiment of the present invention for executing a multiplication of a double precision multiplicand X and a double precision multiplier Y, each of which is represented by a binary representation of 2's complement. It is a block diagram of the arithmetic unit which concerns. This embodiment is a preferred embodiment when the multiplication based on the multiplier upper word YH is always executed immediately after the multiplication based on the multiplier lower word YL.

R8 in FIG. 3 is a pipeline latch having a length of 2 words, and corresponds to the multiplication result latch R4 in FIG. R9 in FIG. 3 is a 2-word length accumulation result latch, and corresponds to the addition result latch R7 in FIG. In this embodiment, the arrangement of the first adder input selector 23 and the first adder input latch R5 in FIG. 2 is omitted, and the output of the accumulation result latch R9 is directly input to the aligner 13. Also, the arrangement of the second adder input selector 24 and the second adder input latch R6 in FIG. 2 is omitted, and the output of the pipeline latch R8 is directly input to the adder 14. Pipeline latch enable signal E8
Is stored in the pipeline latch R8 so as to hold the output of the multiplication processing unit 12, and the accumulation result latch R9 is held in the accumulation result latch enable signal E9 so as to hold the output of the adder 14 from the instruction decoding and control unit 41, respectively. Given.

In the present embodiment, the multiplicand latch enable signal E6 is not applied to the multiplicand latch R1 and the multiplier latch R2 but the common multiplication input latch enable signal is applied.
And the multiplier latch enable signal E7 are separated.
In addition, the first instruction output from the instruction decoding and control unit 41
The selector control signal S1 of 1 is directly supplied to the first selector 21 without passing through the AND gate. First selector 2
1 selects the output of the multiplier MSB latch R3 if the first selector control signal S1 is "1" and the 1-bit constant "0" if it is "0".

Since the other points are the same as those in FIG. 2, detailed description of the configuration will be omitted.

The arithmetic unit of FIG. 3 obtains a double precision multiplication result X × Y by sequentially executing two single precision number / double precision number multiplication instructions P and Q. The instruction P is an instruction for multiplying the single-precision multiplicand XL represented in unsigned binary representation and the double-precision multiplier Y represented in binary notation of 2's complement.
The instruction Q is an instruction for multiplying the single precision multiplicand XH expressed in binary notation of 2's complement and the double precision multiplier Y. Execution of instruction P results in two products XL × YL and XL ×
YH is sequentially obtained, and when the instruction Q is executed, two products XH
XYL and XH * YH are sequentially obtained.

The operation sequence of the arithmetic unit shown in FIG.
This is the same as the embodiment. However, at the time of executing the multiplication XL × YH subsequent to the multiplication XL × YL and at the time of executing the multiplication XH × YH subsequent to the multiplication XH × YL, the instruction decoding and control unit 41 causes the multiplicand latch enable signal E6 and the multiplier latch enable signal E7. Only the latter of and is set to "1". In this case, it is not necessary to supply the first read data address RA1 to the storage device 31.

Also in the case of this embodiment, the first selector 21
From the recode unit 11 to the multiplier lower word YL, the 1-bit constant “0” is stored in the multiplier upper word YH.
Since the output of the multiplier MSB latch R3, that is, the MSB of the multiplier lower word YL, is supplied during the recoding process of
The multiplier upper word YH and the multiplier lower word YL are treated as a series of signed double precision numbers. In addition, the multiplication processing unit 12
In generating / adding the partial product in, the multiplicand lower word XL is unsigned 2 according to the multiplicand polarity inversion signal C2.
As a base number, the multiplicand upper word XH is 2 in 2's complement notation.
Each is treated as a base number. That is, the multiplicand upper word X
H and the multiplicand lower word XL are treated as a series of signed double precision numbers. Therefore, according to the arithmetic unit of the present embodiment as well, although the multiplication processing unit 12 is capable of inputting a single precision number, unlike the conventional case, an accurate multiplication that reflects the whole of the multiplicand lower word XL and the multiplier lower word YL is performed. The precision multiplication result is obtained.

[0083]

As described above, claims 1 and 5
According to the invention, the MSB of the multiplier lower word YL is treated as a series of signed double precision numbers so that the multiplier upper word YH and the multiplier lower word YL are treated as a series of signed double precision numbers.
Since the configuration is reflected in the recoding process of the least significant 2 bits of the above, even if the MSB of the multiplier lower word YL is 1, it becomes possible to execute accurate double precision multiplication with a single single precision multiplier.

According to the second, third, and sixth aspects of the invention, the multiplicand lower word XL is treated as an unsigned binary number, and the multiplicand upper word XH is treated as a two's complement binary number. M of multiplicand lower word XL
Even if SB is 1, it becomes possible to perform accurate double precision multiplication with a single single precision multiplier.

According to the fourth and eighth aspects of the invention, since the lower multiplication execution flag is set when the series of processing for the multiplier lower word YL is completed, the series of processing for the multiplier lower word YL is Multiplier high word YH
It is possible to separate the series of processing related to.

According to the invention of claim 7, when the first and second multiplication results sequentially obtained by the single precision multiplier are added, the first multiplication result is right-shifted for digit alignment. Moreover, since the double-precision addition of the result of the right shift processing and the second multiplication result is adopted, the execution of accurate double-precision digit alignment addition is guaranteed.

[Brief description of drawings]

FIG. 1 is an explanatory diagram showing a method of recoding a multiplier upper word and a multiplier lower word in a double precision multiplication executing method according to the present invention.

FIG. 2 is a block diagram of an arithmetic unit according to the first embodiment of the present invention.

FIG. 3 is a block diagram of an arithmetic unit according to a second embodiment of the present invention.

FIG. 4 is an explanatory diagram conceptually showing a conventional double-precision multiplication executing method using a single single-precision multiplier.

[Explanation of symbols]

 R1 Multiplicand latch (multiplicand latch means) R2 Multiplier latch (multiplier latch means) R3 Multiplier MSB latch (multiplier MSB latch means) R4 Multiplication result latch R5 First adder input latch R6 Second adder input latch R7 Addition result latch R8 pipeline latch R9 accumulation result latch 11 recoding section (recoding means) 12 multiplication processing section (multiplication means) 13 aligner (digit matching addition means) 14 adder (digit matching addition means) 21 first selector (selecting means) 22 second selector 23, 24 first and second adder input selector 31 storage device 32, 33 first and second data bus 41 instruction decoding and control unit 42 status register (status register means) 43 lower multiplication execution Flag 44 AND gate C1 Aligner control signal C2 Multiplicand polarity inversion signal E1 Multiply input latch enable signal E2 Multiply result latch enable signal E3A First adder input latch enable signal E3B Second adder input latch enable signal E4 Addition result latch enable signal E5 Multiplier MSB latch enable signal E6 Multiplicand latch enable signal E7 Multiplier latch enable signal E8 Pipeline latch enable signal E9 Accumulation result latch enable signal RA1 First read data address RA2 Second read data address S1 to S4 First to fourth selector control signals WA Write data address XH Multiplicand higher Word XL Multiplicand lower word YH Multiplier upper word YL Multiplier lower word

Claims (8)

[Claims] 1. A double precision multiplicand in which a binary representation of each two's complement representation is made in an arithmetic unit including a binary corresponding recoding unit of each two's complement representation for single precision multiplication and a multiplication processing unit. A method for performing a multiplication with a double precision multiplier, the method comprising: storing the most significant bits of the multiplier low word; each digit represents a representation of the multiplier low word, where each digit is -2, -1, 0, 1;
Alternatively, a value 0 is used as a further lower bit for processing the least significant 2 bits of the lower word of the multiplier so as to convert it to a quaternary SD representation having a value of 2, and the lower part of the multiplier is recoded into the lower word of the multiplier. A step of performing processing, and a partial product of one word of the multiplicand and the lower word of the multiplier subjected to the recoding processing is generated, and the generated partial products are added to each other, whereby the first multiplication result is obtained by the multiplication processing unit. To convert the representation of the multiplier upper word into a quaternary SD representation in which each digit has a value of -2, -1, 0, 1 or 2, and the least significant 2 bits of the multiplier upper word In the processing, the most significant bit of the stored lower word of the multiplier is used as a further lower bit, and a step of performing a recoding process on the upper word of the multiplier in the recoding unit; Generating a partial product with the high-order multiplier upper word and adding the generated partial products to obtain a second multiplication result in the multiplication processing unit, and the first and second And a step of executing double-precision digit-matching addition of the multiplication result. 2. The double-precision multiplication execution method according to claim 1, wherein in the step of obtaining the first and second multiplication results, the multiplicand lower word is exceptionally processed as an unsigned binary number by the multiplication processing unit. A double-precision multiplication execution method, characterized in that each step is provided. 3. The double-precision multiplication executing method according to claim 1, wherein in the step of obtaining the first and second multiplication results, the multiplicand upper word is processed by the multiplication processing unit as a binary number represented by two's complement. A double-precision multiplication execution method, characterized in that each step is provided. 4. The method of performing double-precision multiplication according to claim 1, wherein the most significant bit of the lower word of the multiplier is stored to indicate that the step of recoding the upper word of the multiplier can be activated. A double precision multiplication execution method further comprising the step of setting a lower multiplication execution flag at the completion of the step of recoding the lower word of the multiplier and the step of obtaining the first multiplication result. 5. An arithmetic unit for executing a multiplication of a double precision multiplicand and a double precision multiplicand, each of which is represented by a binary representation of two's complement, wherein the multiplicand lower word and the multiplicand upper word are selectively selected. A multiplicand latch means for holding, a multiplier latch means for selectively holding the multiplier lower word and the multiplier upper word, and a multiplier M for holding the most significant bit of the multiplier lower word
The SB latch means and the output of the multiplier MSB latch means are selected and output when the multiplier lower word is held in the multiplier latch means and the output of the multiplier MSB latch means is selected when the multiplier upper word is held in the multiplier latch means. For selecting the output of the multiplier latch means and each digit is -2, -1,
The output of the selecting means is used as a further lower bit for converting into a quaternary SD representation having a value of 0, 1 or 2 and for processing the least significant 2 bits of the output of the multiplier latch means, Recoding means for subjecting the output of the multiplier latch means to recoding processing, a partial product of the output of the multiplicand latch means and the output of the recoding means, and adding the generated partial products to add the multiplier latch Multiplication means for obtaining a first multiplication result when the multiplier lower word is held in the means, and second multiplication result when the multiplier upper word is held in the multiplier latch means; A digit-matching addition means for executing double-precision digit-matching addition of the first and second multiplication results obtained by the means. 6. The arithmetic unit according to claim 5, wherein when the multiplicand latch unit holds a multiplicand lower word, the multiplying unit processes the multiplicand lower word as an unsigned binary number, and the multiplicand latch. An arithmetic unit having a function of processing a multiplicand upper word as a binary number in a two's complement representation when the multiplicand upper word is held in the means. 7. The arithmetic unit according to claim 5, wherein the digit-matching and adding means includes an aligner for performing a right shift process on the first multiplication result, and a first multiplication after the right shift process. An arithmetic unit comprising: a result and an adder for executing a double precision addition with the second multiplication result. 8. The arithmetic unit according to claim 5, wherein the first lower order is based on the lower multiplier word to indicate that the processing of the upper multiplier word by the recoding means can be started.
An arithmetic unit further comprising state register means for storing a lower-order multiplication execution flag which is set when the multiplication result is calculated.