JPH08288855A - Method and device for digital signal switching - Google Patents

Abstract

PURPOSE: To suppress the occurrence of noise at the time of switching between different signal systems by inserting the one-bit portion of data to the switching point in accordance with the result of discrimination using data before and after the switching point and delaying data after the switching point. CONSTITUTION: The signal supplied from an input terminal 2 is delayed in a delay line part 3 by a prescribed extent and is supplied to a selected terminal (a). The signal supplied from an input terminal 5 is delayed in a delay line part 6 by a prescribed extent and is supplied to a one-sample latch part 7. A digital signal switching device 1 performs switching between data of the system passing the delay line part 3 and data of the system passing the delay line part 6 after inserting the one-bit portion of data to the switching point designated by a user. A discrimination circuit 8 discriminates the binary state of the one-bit portion of data to be inserted to the switching point. The one- sample latch part 7 delays the one-bit portion of data after the switching point by one sample.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal switching method and apparatus for switching signals of two different systems.

[0002]

2. Description of the Related Art For example, a method of digitizing an audio signal and recording, reproducing and transmitting the same is conventionally carried out by recording and reproducing on an optical disk, a digital audio tape (DAT) or the like, and by digital audio broadcasting by satellite broadcasting or the like. ing. In a digital audio transmission apparatus for recording, reproducing and transmitting such digital audio data, conventionally, when digitizing an audio signal, a sampling frequency is 48 kHz, 44.1 kHz, etc., and a quantization bit number such as 16 bits is used. Has been prescribed.

However, in such a conventional digital audio transmission apparatus, the number of quantization bits of digital audio data generally defines the dynamic range of a demodulated audio signal. Therefore, for example, in order to transmit a higher quality audio signal, it is necessary to increase the number of quantization bits from the current 16 bits to 20 or 24 bits or the like. However, once the format is specified, it is not possible to easily increase the number of quantization bits, so that it is not possible to extract a higher quality audio signal from these devices.

By the way, a method called sigma delta (ΣΔ) modulation has been proposed as a method for digitizing a voice signal (Acoustic Society of Japan, Vol. 46, No. 3, (199).
0) pp. 251-257, "AD / DA converter and digital filter (Yoshio Yamazaki)", etc.).

FIG. 18 shows, for example, that the input audio signal is Σ
FIG. 3 is a block diagram of a ΣΔ modulation circuit that performs Δ modulation processing to obtain digital data in 1-bit units. In FIG. 18, the input audio signal from the input terminal 51 is supplied to the integrator 53 through the adder 52. This integrator 53
Is supplied to the comparator 54, is compared with the midpoint potential of the input audio signal, and is quantized by, for example, 1 bit for each sample period. The frequency during the sampling period (sampling frequency) is 48kHz,
A frequency that is 64 times or 128 times that of 4.1 kHz is used. Quantization is 2 bits or 4
It may be a bit.

This quantized data is a 1-sample delay unit 55.
And is delayed by one sample period. This delay data is converted into an analog signal by, for example, a 1-bit D / A converter 56 and supplied to the adder 52, and the input terminal 51
Is added to the input audio signal from. Then, the quantized data output from the comparator 54 is taken out to the output terminal 57. Therefore, according to the ΣΔ modulation processing performed by this ΣΔ modulation circuit, as described in the above-mentioned document, by sufficiently increasing the frequency of the sampling period (sampling frequency), for example, even a small number of bits of 1 bit is high. A dynamic range audio signal can be obtained. Moreover, it is possible to have a wide transmittable frequency band. Further, since the ΣΔ modulation circuit has a circuit configuration suitable for integration and the accuracy of A / D conversion can be obtained relatively easily, it has been conventionally used often in an A / D converter. . The ΣΔ modulated signal can be converted back into an analog audio signal by passing through a simple analog low pass filter. Therefore, Σ
The Δ modulation circuit can be applied to a recorder that handles high quality data and data transmission by making the most of these characteristics.

By the way, in the digital audio transmission apparatus using the ΣΔ modulation circuit, a digital audio transmission apparatus (hereinafter, referred to as a multi-bit digital audio transmission apparatus) that handles a digital signal in a multi-bit format such as 16 bits described above. It is difficult to realize signal processing in the amplitude direction, such as fade processing, equalization processing, filter processing, crossfade processing, and mixing processing, which are types of attenuation processing that could be realized with. I was not able to take advantage of the features of wide band and high dynamic range.

For example, the fade processing includes a fade-out processing for gradually decreasing the level of a reproduced audio signal with time and a fade-in processing for gradually increasing the level of an audio signal from zero level. Such a fade process is common as a signal process in the amplitude direction of an audio signal.

Therefore, a case where the fade process is performed by the multi-bit digital audio transmission device will be described with reference to FIG. In FIG. 19, a multi-bit digital audio signal of, for example, 16 bits from the input terminal 61 is a multiplier 6
2 to the output terminal 63. Here, for example, when a control signal designating a fade start timing and a speed is supplied to the control signal input terminal 64, the control signal is supplied to the control circuit 65 to generate an arbitrary fade signal. Then, this fade signal is applied to the coefficient generator 6
By being supplied to 6, a coefficient is generated which gradually reduces the level of the audio signal to zero level, for example.
This coefficient is supplied to the multiplier 62.

As a result, the level of the audio signal of the multi-bit digital audio signal supplied to the digital signal input terminal 61 is output to the output terminal 63 at a specified speed from the timing specified by the control signal, for example. A signal that is gradually lowered and muted to zero level is taken out, and the above fade-out processing is performed. It is also possible to perform a fade-in process of gradually increasing the level of the audio signal from zero level by reversing the order of generation of the coefficients.

However, as described above, such processing cannot be performed on the ΣΔ-modulated digital audio signal. That is, since the 1-bit digital data obtained by the ΣΔ modulation process also has the amplitude information represented as a 1-bit pattern on the time axis, the multiplication is performed by the multiplier 62 as in the conventional case, and the amplitude operation process is realized. Was difficult.

On the other hand, for example, as shown in FIG. 20, it is considered to convert 1-bit digital data obtained by ΣΔ modulation into a signal format such as a conventional CD or DAT by using a low-pass filter for processing. To be That is, in FIG. 20, for example, the 1-bit ΣΔ signal supplied to the input terminal 71 is supplied to the low-pass filter 72 and converted into, for example, a 16-bit multi-bit digital audio signal. The converted digital audio signal is supplied to the multiplier 73.

Further, for example, a control signal designating the start timing and speed of the fade is supplied to the control signal input terminal 74, and this control signal is supplied to the control circuit 75 to generate an arbitrary fade signal. By supplying the fade signal to the coefficient generator 76, for example, a coefficient that gradually reduces the level of the audio signal to zero level is generated, and the coefficient is supplied to the multiplier 73.

As a result, the multiplier 73 extracts the digital audio signal whose level is controlled by the coefficient from the coefficient generator 76 from the multi-bit digital audio signal from the low pass filter 72. Then, this digital audio signal is further supplied to the ΣΔ modulator 77, and is again converted into, for example, a 1-bit ΣΔ signal, and the reconverted ΣΔ signal is output terminal 8
It is taken out to 0.

Thus, the output terminal 80 is connected to the input terminal 71.
With respect to the ΣΔ signal from, the level of the audio signal is gradually reduced at a specified speed from the timing specified by the control signal, and a signal of which the level is zero is taken out, and so-called fade-out processing is performed. In addition,
For example, the fade-in process of gradually increasing the level of the audio signal from the zero level can be performed by reversing the order of generation of the coefficients. That is, according to this apparatus, it is possible to perform processing such as fade in the same manner as in the past.

[0016]

By the way, when this apparatus is used, the ΣΔ signal supplied to the input terminal 71 is always converted into a 16-bit multi-bit digital audio signal by the low-pass filter 72. That is, in this device, the ΣΔ signal is processed by the low-pass filter 72 and the ΣΔ modulator 77 even when processing such as fading is not performed.
Pass through. For this reason, the characteristics of the signal become the same as those of the conventional CD, DAT, etc., and the characteristics of the original ΣΔ modulation such as wide band and high dynamic range cannot be utilized.

Therefore, as shown in FIG. 21, when the amplitude operation such as the fade process is not performed, the switch 78 is used.
The original ΣΔ signal supplied to the selected terminal A of the switch is derived from the output terminal 80 via the delay device 79, and is supplied to the selected terminal B of the switch 78 only when the amplitude operation is performed. It was considered that the ΣΔ signal re-modulated by the ΣΔ modulator 77 should be derived from the output terminal 80.

However, the two ΣΔ signals switched by the switch 78 are signals of two different systems modulated on the time axis by different ΣΔ modulators although they have almost the same analog audio signal component. For,
If it was switched directly, a large noise was generated at the switching point, which was not practical.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a digital signal switching method and apparatus capable of suppressing the occurrence of noise when switching signals of two different systems.

[0020]

A digital signal switching method according to the present invention uses data before and after the switching point in order to solve the above problems when switching signals of two different systems at a predetermined switching point. Depending on the result of the determination, one bit of data is inserted at the switching point, and the data after the switching point is delayed.

Further, the digital signal switching device according to the present invention makes a determination using the data before and after the switching point in order to solve the above problem when switching signals of two different systems at a predetermined switching point. The determination means and the switching signal processing means for inserting one bit of data based on the result of the determination means are provided.

[0022]

[Function] An energy level difference generated when signals of two different systems are switched is derived from data before and after the switching point, and one bit of data is inserted in a form of correcting this,
It is possible to suppress the generation of noise at the switching point.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of a digital signal switching method and device according to the present invention will be described below with reference to the drawings. This embodiment is a digital signal switching device that switches two different ΣΔ signals at predetermined switching points.

First, as shown in FIG. 1, the digital signal switching device 1 has a determination circuit 8 for performing determination using data before and after the switching point, and 1 bit according to the determination result of the determination circuit 8. 1 sample latch section 7 which is a switching signal processing means for inserting minute data.

When one of the two systems is the A system and the other is the B system, the signal of the A system supplied through the input terminal 2 is delayed by the delay line section 3 by a predetermined signal processing, and the switch 4 is operated. Is supplied to one of the selected terminals a. The B-system signal supplied via the input terminal 5 is delayed by the predetermined other signal processing in the delay line section 6 and supplied to the 1-sample latch section 7. The output of the 1-sample latch unit 7 is supplied to the other selected terminal b of the switch 4. By the switching connection of the movable piece c of the switch 4, the output of the delay line section 3 or the output of the 1-sample latch section 7 is derived via the output terminal 11.

Here, the digital signal switching apparatus 1 has the data D _A0 , D _A1 , D _A2 , D _A3 , D _A4 , and D _{A5 of the} A system shown in FIG. ,
D _A6 , D _A7 , D _A8 , D _A9 , D _A10 , and D _A11, and the B system data D _B0 shown in FIG. 2B via the delay line unit 6,
D _B1 , D _B2 , D _B3 , D _B4 , D _B5 , D _B6 , D _B7 , D _B8 , D
A switching point P designated by the user between _B9 , D _B10 , and D _B11
After inserting 1-bit data D _X into C, switching is performed as shown in FIG.

The determination circuit 8 switches in the delay line section 3 in accordance with a switching control signal supplied through the control signal terminal 9, that is, a control signal indicating the position of the switching point designated by the user. For example, 1-bit data D _A5 before the point P _C and 1-bit data D _B6 after the switching point P _C in the delay line section 6 should be used to insert at the switching point P _C. The binary state “0” or “1” of 1-bit data D _X is determined. In the following, this binary state "0" or "1"
The description will proceed with "-1" or "1".

When the decision circuit 8 decides that the binary state of the 1-bit data D _X to be inserted is "-1", the decision circuit 8 returns 1
A reset signal is supplied to the sample latch unit 7, and a set signal is supplied when it is determined to be "1".

When the set signal is supplied from the determination circuit 8, the 1-sample latch unit 7 generates the 1-bit insertion data D _X which is "1" and supplies it to the other selected terminal b of the switch 4. Supply. Also, one sample latch unit 7
When the reset signal is supplied from the determination circuit 8,
The 1-bit insertion data D _X which is “−1” is generated and supplied to the other selected terminal b of the switch 4. The 1-sample latch unit 7 delays the 1-bit data D _B6 after the switching point by 1 sample. Therefore, in the switch 4, the switching point P specified by the user is set.
The 1-bit data D _B6 after _C can be delayed by 1 sample, and then the 1-bit data D _X which is "1" or "-1" can be inserted therein. When the switching control signal is not supplied to the control signal terminal 9, the determination circuit 8 connects the movable piece c of the switch 4 to one of the selected terminals a, and the data of the A system shown in FIG. Is supplied to the output terminal 11.

Here, the decision circuit 8 determines the switching point P.
_The binary state “1” of the 1-bit insertion data D _X is calculated according to the result of the number estimation operation of “1” and “−1” in the data block of a predetermined number of samples including the data before and after _C.
Alternatively, the judgment of "-1" is made. This applies the operating principle of an interpolator for digital data, which can be described with reference to FIGS.

First, the digital data interpolating device 80 will be described.

The digital data interpolating device 80 is
A defective data block that could not be corrected by normal error correction processing is interpolated. This digital data interpolating device 80
Of the moving average processing circuit 87 and the moving average processing circuit 87 are multiplication means for multiplying the defective data block by a constant coefficient and multiplying the data before and after the defective data block by a changing coefficient. Based on the number estimation arithmetic circuit 88 for estimating the number of "1" and "-1" constituting the defective data block from the output and the result estimated by the number estimation arithmetic circuit 88, the interpolation data of the defective data block And an interpolation data generation circuit 89 for determining the array pattern of and generating the interpolation data.

Usually, in a digital audio recording / reproducing apparatus such as a digital tape recorder, a sync signal and an error correction code added by an ECC adding circuit are used at the time of recording to detect a transmission error occurring during recording / reproducing at the time of reproducing. Can be corrected. The recording format in this case is, as shown in FIG. 4, that 1-bit digital data, which is 1-bit quantized data, is divided into every 4 pieces such as data D _{0 to} D ₃ , and every 4 pieces are synchronized. Signals S ₀ and S ₁ and error correction codes P ₀ and P ₁ are added. As described above, the transmission error that occurs during recording and reproduction can be detected and corrected by the synchronization signal and the error correction codes P ₀ and P ₁ added by the ECC adding circuit.

However, at the time of recording / reproducing, for example, in the error correction process in the sync separation and error correction circuit, a defective data block including defective data that cannot be corrected as 4-bit 1-bit digital data may occur. This may cause failure of the digital audio recording / reproducing apparatus and its peripheral devices, damage of the magnetic tape as a recording medium, or disconnection in data transmission.

For this reason, the digital data interpolating device 80 uses a coefficient of a constant value for the defective data block consisting of four 1-bit digital data and the data before and after the defective data block over the width of the defective data block. , And the preceding and following data are respectively multiplied by changing coefficients to estimate the number of defective data blocks “1” and “−1” and maintain the total energy amount of the four 1-bit digital data. In this state, the interpolation process for determining the array pattern of "-1" and "1" is performed.

The digital data interpolator 80 delays a delay circuit 82 for delaying 4-bit unit 1-bit digital data supplied from an unillustrated sync separation and error correction circuit through an input terminal 81, and a delay circuit 82. An interpolation processing unit 83 for performing the above-described interpolation processing on the generated 1-bit digital data in units of four, and a selector for selectively switching and outputting the non-interpolation data from the delay circuit 82 or the interpolation data from the interpolation processing unit 83. And 84.

Here, the interpolation processing section 83 comprises a moving average processing circuit 87, a number estimation calculation circuit 88, and an interpolation data generation circuit 89.

The selector 84 has one selected terminal a to which the non-interpolated data from the delay circuit 82 is supplied, the other selected terminal b to which the interpolation data from the interpolation processing section 83 is supplied, The movable piece c whose connection is switched to one selected terminal a or the other selected terminal b in accordance with the interpolation on / off control signal supplied from the sync separation and error correction circuit via the control signal terminal 85. Become.

The operation principle of the interpolation processing unit 83 will be described. For example, the 1-bit digital data reproduced from the magnetic tape by the reproducing head of the digital audio recording / reproducing apparatus has four 1-bit digital data D ₁₂ , D ₁₃ , D ₁₄ , as shown in FIG. It is assumed that a defective data block B _b composed of D ₁₅ has occurred.

First, the moving average processing circuit 87 corrects the correct 11 before the defective data block B _b shown in FIG.
1-bit digital audio data D _{1 to} D ₁₁
Is subjected to a 2-step moving average filtering process of 4 taps and 8 taps to derive a moving average value M _A at the point P _A shown in FIG. Here, the 4-tap moving average processing means D _{1 to} D ₄ , D _{2 to} D ₅ , D _{3 to} D for 1-bit digital audio data D _{1 to} D ₁₁ shown in FIG.
_{6, D 4 ~D 7, D} 5 ~D 8, D 6 ~D 9, D 7 ~D 10, D 8 ~
This is an averaging process of moving with 4 taps like D ₁₁ , and eight 4-tap moving averaging process outputs as shown in FIG. 5B are obtained. The moving average processing circuit 36 further performs an 8-tap moving average processing on these eight 4-tap moving average processing outputs to obtain an 8-tap moving average processing output as shown in FIG. The moving average value M _A at the point P _A shown in (D) is derived.

The moving average processing circuit 87 also performs the above-described two-step moving average processing on the 11 correct 1-bit digital audio signals D _{17 to} D ₂₇ after the defective data block B _b to obtain P _B. The moving average value M _B of the points is derived.

Next, the moving average values M _A and M _{B of} these two points
The value M _C ′ at the P _C point is calculated by linear interpolation using M _C ′ = (M _A + M _B ) / 2.

Here, 1 including the defective data block B _b
The moving average value M _C is also derived from one piece of 1-bit digital data D _{9 to} D ₁₉ . This moving average value M _C can be calculated by using the FIR filter shown in FIG. 7 as follows: M _C = D ₉ × k ₀ + D ₁₀ × k ₁ + D ₁₁ × k ₂ + D ₁₂ × k ₃ + D ₁₃ × k ₄ + D ₁₄ × k ₅ + D ₁₅ × k ₆ + D ₁₆ × k ₇ + D ₁₇ × k ₈ + D ₁₈ × k ₉ + D ₁₉ × k ₁₀ .

The above-mentioned 2 by the moving average processing circuit 87
In the step-wise moving average processing, 1-bit digital data D
_{9 to} D ₁₉ , D _{9 to} D ₁₂ , D _{10 to} D ₁₃ , D _{11 to} D ₁₄ ,
D _{12 to} D ₁₅ , D _{13 to} D ₁₆ , D _{14 to} D ₁₇ , D _{15 to} D ₁₈ , D
₁₆ is subjected to moving average processing of four-tap and so to D _19, to give the 4-tap moving average processing output of eight as shown in (B) Figure _5, the additional four-tap moving average process output eight these 8 tap moving average processing is performed. Therefore, the moving average value M _C is M _C = D ₉ + D ₁₀ + D ₁₁ + D ₁₂ + D ₁₀ + D ₁₁ + D ₁₂ + D ₁₃ + D ₁₁ + D ₁₂ + D ₁₃ + D ₁₄ + D ₁₂ + D ₁₃ + D ₁₄ + D ₁₅ + D ₁₃ + D ₁₄ + D ₁₅ + D ₁₆ + D ₁₄ + D ₁₅ + D ₁₆ + D ₁₇ + D ₁₅ + D ₁₆ + D ₁₇ + D ₁₈ + D ₁₆ + D ₁₇ + D ₁₈ + D ₁₆ = D ₉ × 1 + D ₁₀ × 2 + D ₁₁ × 3 + (D ₁₂ + D ₁₃ + D ₁₄ + D ₁₅ ) × 4 + D ₁₆ × 4 + D ₁₇ × 3 + D ₁₈ × 2 + D ₁₉ × 1.

Here, the unknowns are the error data D ₁₂ , D ₁₃ , D _{14 of} the defective data block B _b shown in FIG.
Although it is D ₁₅ , the coefficients k ₃ to k ₆ corresponding to these terms become a constant value “4” as shown in FIG. As shown in FIG. 6B, the coefficients k _{0 to} k
₂ increases in the order of k ₀ = 1, k ₁ = 2, k ₂ = 3, and rises to the right as a whole. The coefficients k _{7 to} k ₁₀ are k ₇ = 4,
As a result, k ₈ = 3, k ₉ = 2, k ₁₀ = 1 and so on. The moving average processing circuit 87 uses the coefficient shown in FIG. 6B to perform the two-stage moving average processing.

Therefore, the four error data D ₁₂ ,
Even if the arrangement pattern of “1” and “−1” for D ₁₃ , D ₁₄ , and D ₁₅ is not known, the moving average value M _C can be determined by the number of “1” or “−1”. Estimating the number of "1" or "-1" is the number estimation arithmetic circuit 8
8 This number estimation arithmetic circuit 88 is obtained by setting M _C ≈M _C ′, (D ₁₂ + D ₁₃ + D ₁₄ + D ₁₅ ) ≈ (M _C ′ − (D ₉ × 1 + D ₁₀ × 2 + D ₁₁ × 3 + D _{16 × 4 + D 17 × 3 +} D 18 × 2 + D 19 × 1)) / 4 of estimating the number of "1" or "-1" from the equation.

In the above equation, the number estimation calculation circuit 88
Is D ₁₂ + D ₁₃ + D ₁₄ + D ₁₅ ≈4 --->"1": 4 "-1": 0 D ₁₂ + D ₁₃ + D ₁₄ + D ₁₅ ≈2 --->"1": 3 " -1 ": 1 piece D ₁₂ + D ₁₃ + D ₁₄ + D ₁₅ ≈0 --->" 1 ": 2 pieces" -1 ": 2 pieces D ₁₂ + D ₁₃ + D ₁₄ + D ₁₅ ≈-2 ---->" 1 "":1""-1": 3 D ₁₂ + D ₁₃ + D ₁₄ + D ₁₅ ≈ -1 --->"1": 0 "-1": 4 "1" and "-1" Can estimate the number of

In this way, the moving average processing circuit 87 performs the moving average processing so that the coefficient value becomes constant over the error data width, so that the number estimation calculation circuit 88 can easily make "1" and "1" in the error data. The number of "-1" can be estimated. In addition, here, although 2-step moving average processing of 4 taps and 8 taps is performed for an error of 4 bit width, the number of bit widths, the number of taps, and the number of stages are not limited to this.

As described above, if the number estimation arithmetic circuit 88 estimates the numbers of "1" and "-1" in the error data, the total energy amount of the four 1-bit digital data is maintained. It becomes possible to do. Therefore, the interpolation data generation circuit 89 uses the "1" and "-1".
It is only necessary to determine the array pattern of "1" and "-1" of the interpolation data and generate the interpolation data while maintaining the energy amount determined by the number of. For example, if the number of "1" and "-1" estimated by the number estimation arithmetic circuit 88 is two, the interpolation pattern is -1, -1,1,1,1-1, -1, -1, 1 1, −1, −1, 1 1, 1, −1, 1, −1 1, 1, −1, −1, and the above five array patterns are applied to the defective data block B _b at the maximum. Just look.

That is, as an example of the interpolation data generating circuit 89, a value obtained by linearly interpolating between P _{A and} P _{B of} FIG. 5D is used as a reference value of the moving average value, and the moving average value of D _{2 to} D ₁₂ is used. D ₁₂ is determined from the above, and D _{3 to} D ₁₃ are similarly determined using the determined D _12.
The data is determined by D ₁₃ from the moving average value of. At this time, when the number of "1" and "-1" obtained previously is reached on the way, the remaining bits are filled so that this number is protected.

In this way, the interpolation processing unit 83 performs the interpolation processing on the defective data block B _b , and the selector 84
To the selected terminal b. Then, as described above, the digital data interpolating device 80 receives the interpolating ON control signal from the sync separation and error correction circuit (not shown) via the control signal terminal 85, as described above.
Is connected to the selected terminal b, and the interpolation data is output from the output terminal 86.

The operation principle of the interpolation processing unit 83 has been described above. Next, a specific operation of the digital data interpolation device 80 including the interpolation processing unit 83 will be described with reference to the flowchart of FIG. Since the digital data interpolating device 80 performs the above interpolation processing under the control of an interpolation processing control circuit (not shown), the flow chart of FIG. 8 shows the flow of control performed by the interpolation processing control circuit.

First, as shown in step S1, the interpolation processing control circuit instructs the moving average processing circuit 87 to select a plurality of "1" and "-1" that can be taken in a data block for four pieces of 1-bit audio data. Each of the number patterns is multiplied by the constant coefficient shown in FIG. _6B to calculate a plurality of candidate values M _C2 'corresponding to the defective data block B _b .

Next, in step S2, the interpolation processing control circuit determines whether or not the interpolation ON control signal is supplied to the control signal terminal 85 from the sync separation and error correction circuit.
When it is determined that the interpolation ON control signal is supplied, the process proceeds to step S3, and the interpolation control circuit causes the moving average processing circuit 87 to obtain the moving average values M _A and M _B shown in FIG. 5C.

Next, the process proceeds to step S4, the interpolation processing control circuit, the moving average processing circuit 87, the previous data D ₉ of the defective data block B _b shown in (A) of FIG. 6, D _10, D
₁₁ and the coefficient k ₀ , k ₁ , k ₂ having the upward slope as shown in FIG. 6B, the calculation D ₉ × k ₀ + D ₁₀
Perform × k ₁ + D ₁₁ × k ₂ . Then, the calculation result is M _C1 '.

Next, proceeding to step S5, the interpolation processing control circuit causes the moving average processing circuit 87 to display the data D ₁₆ , D ₁₇ , D ₁₈ , and D ₁₉ after the defective data block B _b , as shown in FIG. The calculation D ₁₆ × k ₇ + D ₁₇ × using the coefficients k ₇ , k ₈ , k ₉ , and k ₁₀ having a downward slope as shown in B).
Perform k ₈ + D ₁₈ × k ₉ + D ₁₉ × k ₁₀ . Then, the calculation result is M _C3 '.

Next, in step S6, the interpolation processing control circuit calculates the interpolation data candidate M _C '. Here, the interpolation data candidate M _c 'is a plurality of candidate values M corresponding to the defective data block B _b portion obtained in step S1.
_{One of C2} 'and the calculation result M obtained in step S4
_It can also be represented as the sum of _C1 'and the calculation result M _C3 ' obtained in step S5. Therefore, the processing proceeds to step S7, and the interpolation processing control circuit instructs the number estimation calculation circuit 88 to have M _C1 '+
M _C3 '-M _c ' is calculated, and the nearest "1" or "-" is selected from the plurality of candidate values M _C2 'obtained in step S1.
Estimate one with a number pattern of 1 ".

Then, in step S8, the interpolation processing control circuit causes the interpolation data generation circuit 89 to calculate the total of four 1-bit digital data based on one estimated from the plurality of candidate values M _C2 '. In the state where the energy amount of 1 is maintained, the interpolation data in which the arrangement pattern of "1" and "-1" is determined is generated.

As described above, the interpolation processing control circuit controls each part of the digital data interpolating device 80 to perform the interpolation processing.

Therefore, the digital data interpolation device 80
Even if defective data that cannot be completely corrected by error correction processing is generated during recording / reproduction of 1-bit digital data, the 1-bit digital data can be interpolated in units of defective data blocks. In addition, the digital data interpolation device 80
Calculates the number of "1" and "-1" and then determines the array pattern, so that the calculation can be simplified.

Although the digital data interpolating device has been described above, the decision circuit 8 shown in FIG. 1 utilizes the operating principles of the moving average processing circuit 87 and the number estimation calculation circuit 88 in the interpolation processing unit 83 shown in FIG. However, according to the result of the number estimation calculation of “1” and “−1” in the data block of a predetermined number of samples including the data before and after the switching point, 1
Binary state of bit insertion data D _X , "1" or "-"
1 ”is determined.

The detailed operation of the decision circuit 8 will be described below.
This will be described with reference to the flowchart of FIG. In addition,
5 and 6 are also used by replacing the bad data block B _b with the unknown data block B _b . That is, it is assumed that the unknown data block B _b is composed of 4-bit data in which 1-bit data is inserted at the switching point P _C. As an example, the case where the unknown data block B _b is D ₁₂ , D ₁₃ , D ₁₄ , and D ₁₅ will be described.

First, as shown in step S11, it is assumed that the user issues a data switching request. this is,
The switching control signal is sent to the determination circuit 8 via the control signal terminal 9.
It turns out by being supplied to.

Next, as shown in step S12, the decision circuit 8 calculates the moving average value M _C ′ of the unknown data block B _b from the delay line data of the A and B systems. Specifically, as shown in FIG. 5, first, the correct 11 pieces of 1-bit digital audio data data D _{1 to} D ₁₁ before the unknown data block B _b are divided into two stages of 4 taps and 8 taps. Applying the moving average filter process, P
Calculates a moving average value M _A for point _A, also subjected to moving average processing of the two stages unknown data block B after the right eleven each of 1-bit digital audio data data D _{b 17} to D _27, The moving average value M _B of the P _B points is calculated,
_A moving average value M _C ′ is derived by linear interpolation using the moving average value M _A and the moving average value M _B.

Next, in step S13, the determination circuit 8
1 includes an unknown data block B _b as shown in FIG.
Of the bit digital audio data D _{9 to} D ₁₉ ,
1-bit digital audio data D ₉ , D ₁₀ , D ₁₁ before the unknown data block B _b and D ₁₆ , D ₁₇ , D after the unknown data block B _b
The solution N _A of the number estimation calculation is derived from ₁₈ , D ₁₉ and the moving average value M _C ′. Specifically, first, 11 pieces of 1-bit digital data D ₉ ~ containing unknown data block B _b
The moving average value M _C is also derived from D ₁₉ .

M _C = D ₉ × k ₀ + D ₁₀ × k ₁ + D ₁₁ × k ₂ + D ₁₂ × k ₃ + D ₁₃ × k ₄ + D ₁₄ × k ₅ + D ₁₅ × k ₆ + D ₁₆ × k ₇ + D ₁₇ × k ₈ + D ₁₈ × k ₉ + D ₁₉ × k ₁₀ .

In the above two-stage moving average processing, 1
Bit digital data D _{9 to} D ₁₉ , D _{9 to} D ₁₂ ,
D _{10 to} D ₁₃ , D _{11 to} D ₁₄ , D _{12 to} D ₁₅ , D _{13 to} D ₁₆ , D
₁₄ is subjected to moving average processing of four-tap and so _{~D 17, D 15 ~D 18,} D 16 ~D 19, to give the 4-tap moving average processing output of eight as shown in (B) Figure 5 _{, And} these 4
Eight taps moving average processing was performed on eight outputs. Therefore, the moving average value M _C is M _C = D ₉ + D ₁₀ + D ₁₁ + D ₁₂ + D ₁₀ + D ₁₁ + D ₁₂ + D ₁₃ + D ₁₁ + D ₁₂ + D ₁₃ + D ₁₄ + D ₁₂ + D ₁₃ + D ₁₄ + D ₁₅ + D ₁₃ + D ₁₄ + D ₁₅ + D ₁₆ + D ₁₄ + D ₁₅ + D ₁₆ + D ₁₇ + D ₁₅ + D ₁₆ + D ₁₇ + D ₁₈ + D ₁₆ + D ₁₇ + D ₁₈ + D ₁₆ = D ₉ × 1 + D ₁₀ × 2 + D ₁₁ × 3 + (D ₁₂ + D ₁₃ + D ₁₄ + D ₁₅ ) × 4 + D ₁₆ × 4 + D ₁₇ × 3 + D ₁₈ × 2 + D ₁₉ × 1.

Here, the unknown number is the unknown data block B _b.
Error data D ₁₂ , D ₁₃ , D ₁₄ , and D ₁₅ of the above, the coefficients k ₃ to k ₆ corresponding to these terms are constant values “4” as shown in FIG. Becomes Note that FIG.
As shown in FIG. 7B, the coefficients k _{0 to} k ₂ are k ₀ = 1 and k ₁
= 2, k ₂ = 3, and so on, and overall it goes up to the right. The coefficients k _{7 to} k ₁₀ are k ₇ = 4, k ₈ = 3, k ₉ =
2, k ₁₀ = 1 and so on, and as a whole, it falls to the right.

Therefore, four unknown data D ₁₂ , D ₁₃ ,
2 value of D _14, D _15, it is possible to obtain the number of "1" and "-1". Estimating the number of "1" or "-1" is the number estimation calculation. The solution N _A of the number estimation operation is
From the above, N _A = - obtained in _{(M C '(D 9 ×} 1 + D 10 × 2 + D 11 × 3 + D 16 × 4 + D 17 × 3 + D 18 × 2 + D 19 × 1)) / 4.

Next, in step S14, the determination circuit 8
Calculates the sum of the unknown data D ₁₂ , D ₁₃ , D ₁₄ , and D ₁₅ , that is, the solution N _B of D ₁₂ + D ₁₃ + D ₁₄ + D ₁₅ .

Next, in step S15, the determination circuit 8
Calculates the N _B -N _A, derives the determination result N _C. For example, if N _B is 3 and the actual data is (1, 1, 0, 1), then in this data, 1 is 3 and 0 is 1, so N _A should be 2. Is. Therefore, N _C
= 1, which means that the energy shift caused by connecting discontinuous data has a difference of half the weight of the data inversion for one bit. Therefore, the 1-bit insertion data in this case is "-1".
Is determined.

Next, in step S16, the determination circuit 8
The switching of the switch 4 is controlled so that “−1” is inserted from the one-sample latch unit 7 to the switching point P _C in accordance with the determination result of 1. Switching point of the data to P _C "-
By inserting "1" data for 1 bit, it is possible to subtract half the energy for the data inversion for 1 bit, and it is possible to suppress the generation of noise as shown in FIG. 10C. . In addition, (B) of FIG.
The switching process in this embodiment is not performed, and
The generation state of noise when the system data is switched is schematically shown. Further, FIG. 10A shows the case without switching. That is, according to this embodiment, two different
The energy level difference that occurs when the system signal is switched is derived from the data before and after the switching point, and by inserting 1-bit data in a form that corrects this, the state is almost the same as the state without switching. As described above, the generation of noise at the switching point can be suppressed.

Next, another embodiment will be described. The other embodiment is also a digital signal switching device that switches signals of two different systems at predetermined switching points.

A schematic configuration of another embodiment is shown in FIG. Here, the same components as those in the embodiment shown in FIG. 1 are designated by the same reference numerals. A digital signal switching device of another embodiment inserts a decision circuit 8 for making a decision using the data before and after the switching point P _C and 1-bit data according to the decision result of the decision circuit 8. Or, without inserting, pass through as it is, or at least one bit of data immediately after the switching point is inverted without inserting, or by inserting the above 1-bit digital data,
And switching signal processing means for performing switching processing for inverting at least one bit of data.
The switching signal processing means includes a 1-sample latch unit 7
And a switch 4 and a switch 10.

The switch 4 has three selected terminals a, b,
c. The signal of the A system from the delay line unit 3 is supplied to the selected terminal a. The B-system signal from the delay line section 6 is supplied to the selected terminal b. The output signal from the one-sample latch unit 7 is supplied to the selected terminal c. The movable piece of the switch 4 is switched by the output of the determination circuit 8.

The switch 10 also comprises three selected terminals d, e, f. The output of the switch 4 is supplied to the selected terminal d. "1" is supplied to the selected terminal e. Further, "-1" is supplied to the selected terminal f. The movable piece of the switch 10 is also switched by the output of the determination circuit 8. Then, the output of the switch 10 is derived from the output terminal 11.

1 sample latch section 7, switch 4,
As described above, the switching signal processing means including the switch 10 has at least 1 according to the determination result of the determination circuit 8.
Insert and switch the data for one bit, switch it without inserting it, switch it by inverting the one-bit data immediately after the switching point without inserting it, or insert the above-mentioned one-bit data. , And at least one bit of data is inverted and switched.

The reason why 1-bit data is inserted and switched is that when switching signals of two different systems, noise of half the energy is apt to occur with respect to 1-bit data inversion. In this case, the half of the energy is subtracted by inserting 1-bit data of "1" or "-1".

If no noise occurs at the time of switching, it is not necessary to deduct the half energy by inserting 1-bit data of "1" or "-1".

Further, if it is known that energy noise of 1 bit of data inversion is generated at the time of switching, it is possible to cancel the noise at all by inverting 1 bit immediately after the switching point.

As described above, the digital signal switching device of the other embodiment performs the switching process while causing the switching signal processing means to select the above four states. In this case, it is the determination circuit 8 that determines the above four states.

The judgment circuit 8 in the delay line section 3 responds to the switching control signal supplied through the control signal terminal 9, that is, the control signal indicating the position of the switching point P _C designated by the user. Switching point P _C above
2 before the above, for example, the data D _A5 for 1 bit,
By using, for example, 1-bit data D _B6 after the switching point P _C in the delay line section 6, it is determined which of the four states the switching signal processing means should perform at the switching point P _C. To do.

The decision made by the decision circuit 8 is similar to the decision circuit of the embodiment shown in FIG. 1 above, that is, "1" and "-" in a data block of a predetermined number of samples including data before and after the switching point. According to the number estimation calculation result of "1", which of the above four states is to be performed at the switching point P _C is determined. Here, a specific description of the number estimation calculation process will be omitted.

Next, the operation of the switching signal processing means according to the judgment result of the judgment circuit 8 will be described with reference to Table 1 below, the block diagram of FIG. 11 and the flowchart of FIG. To do. The description of steps S11 to S14 in the flowchart of FIG. 9 is omitted.

[0085]

[Table 1]

First, the determination result N _{C in} step S15 of the flowchart of FIG. 9 showing the operation of the determination circuit 8 is 0.
The case will be described. When the determination result N _C is 0, the above N _A and the above N _B are equal, so the switching point P
_It can be judged that noise does not occur due to switching at _C. In this case, the determination circuit 8 does not allow the switching signal processing means to insert data for 1 bit or invert data for 1 bit immediately after the switching point. That is, the determination circuit 8 switches the movable piece of the switch 4 from the selected terminal a to the selected terminal b (indicated as a → b in the figure), and the switch 1
The movable piece of 0 is left connected to the selected terminal d.

Next, the case where the determination result N _C is 1 will be described. When the determination result N _C is 1, when switching between two different systems, the energy shift due to connecting discontinuous data is a difference of half the weight of the data inversion for 1 bit. It occurs in the positive direction. Therefore, in this case, the determination circuit 8 causes the switching signal processing means to insert the 1-bit data D _X as “−1”. That is, the determination circuit 8 switches the movable piece of the switch 4 from the selected terminal a to the selected terminal c,
1 by the 1-sample latch unit 7 immediately after the switching point P _C
Delay 1 bit of data and switch 1
The movable point of 0 is connected to the selected terminal f, and the switching point P
Insert "-1" immediately after _C.

Next, the case where the determination result N _C is 2 will be described. When the determination result N _C is 2, when switching between two different systems, the energy shift due to the connection of discontinuous data is a positive direction as a difference in the magnitude of the weight of 1-bit data inversion. Occurs in. Therefore, in this case, the determination circuit 8, the switching signal processing means, for inverting the 1-bit data immediately after the switching point P _C from "1" [-1 ". That is, the determination circuit 8 switches the movable piece of the switch 4 from the selected terminal a to the selected terminal b, connects the movable piece of the switch 10 to the selected terminal f, and outputs one bit immediately after the switching point P _C. The data of is inverted from "1" to "-1".

Next, a case where the determination result N _C is 3 will be described. When the determination result N _C is 3, when switching between two different systems, the energy shift due to the connection of discontinuous data is equal to the weight of 1 bit of data inversion and 1 bit Occurs in the positive direction as a difference obtained by adding half the weight of the data inversion. Therefore, in this case, the determination circuit 8 causes the switching signal processing means to insert the 1-bit data D _X into the switching point P _C as “−1” (“−1”), and
It is necessary to invert 1-bit data immediately after the switching point P _C from “1” to [−1]. That is, the determination circuit 8 uses the movable piece of the switch 4 as the selected terminal a.
To the selected terminal c, the 1-sample latch unit 7 delays one bit of data immediately after the switching point P _C by 1 sample, connects the movable piece of the switch 10 to the selected terminal f, and switches the switching point. injects the "-1" immediately after P _C, further, inverts the 1-bit data immediately after the switching point P _C from "1" [-1 ".

Next, a case where the determination result N _C is 4 will be described. When the determination result N _C is 4, when switching between two different systems, the energy shift due to the connection of discontinuous data is a positive direction as a difference in the magnitude of the weight of the 2-bit data inversion. Occurs in. Therefore, in this case, the determination circuit 8, the switching signal processing means, inverts the 2-bit data immediately after the switching point P _C from "1" [-1 ". That is, the determination circuit 8 switches the movable piece of the switch 4 from the selected terminal a to the selected terminal b, and connects the movable piece of the switch 10 to the selected terminal f for two samples.

Next, the case where the determination result N _C is 5 will be described. When the determination result N _C is 5, when switching between two different systems, the energy shift due to the connection of discontinuous data is equal to the weight of the data inversion for 2 bits and 1 bit. Occurs in the positive direction as a difference obtained by adding half the weight of the data inversion. Therefore, in this case, the determination circuit 8 causes the switching signal processing means to insert the 1-bit data D _X into the switching point P _C as “−1” (“−1”), and
It is necessary to invert the 2-bit data immediately after the switching point P _C from “1” to [−1]. That is, the determination circuit 8 uses the movable piece of the switch 4 as the selected terminal a.
To the selected terminal c, the 1-sample latch unit 7 delays one bit of data immediately after the switching point P _C by 1 sample, connects the movable piece of the switch 10 to the selected terminal f, and switches the switching point. injects the "-1" immediately after P _C, further, inverts the 2-bit data immediately after the switching point P _C from "1" [-1 ".

Next, the case where the determination result N _C is -1 will be described. When the determination result N _C is −1, when switching between two different systems, the difference in energy due to connecting discontinuous data is a difference of half the weight of the data inversion for one bit. And occurs in the positive and negative directions. Therefore, in this case, the determination circuit 8 needs to insert the 1-bit data D _X into the switching signal processing means as “1”. That is, the determination circuit 8
The movable piece of the switch 4 is switched from the selected terminal a to the selected terminal c, and the 1-sample latch unit 7 delays the data of 1 bit immediately after the switching point P _C by 1 sample, and the movable piece of the switch 10 is changed. It is connected to the selected terminal e and "1" is inserted immediately after the switching point P _C.

Next, the case where the determination result N _C is −2 will be described. When the determination result N _C is −2, when switching between two different systems, the energy shift due to the connection of discontinuous data is negative as the difference in the weight of 1-bit data inversion. Occurs in the direction.
Therefore, in this case, the determination circuit 8, the switching signal processing means, for inverting the 1-bit data immediately after the switching point P _C in the 1 "from" -1 ". That is, the determination circuit 8 switches the movable piece of the switch 4 from the selected terminal a to the selected terminal b, connects the movable piece of the switch 10 to the selected terminal e, and outputs one bit immediately after the switching point P _C. Data of "1" is inverted from "-1" to "1".

Next, the case where the determination result N _C is -3 will be described. When the determination result N _C is −3, when switching between two different systems, the difference in energy due to connecting discontinuous data is 1 bit to the weight of the data inversion for 1 bit. It occurs in the negative direction as a difference obtained by adding half the weight of the minute data inversion. Therefore, in this case, the determination circuit 8, the switching signal processing means, the data D _X of 1 bit to the switching point P _C causes inserted as "1", one bit of data immediately after the switching point P _C Must be inverted from "-1" to [1]. That is, the determination circuit 8
Switches the movable piece of the switch 4 from the selected terminal a to the selected terminal c, delays one bit of data immediately after the switching point P _C by one sample by the one sample latch section 7, and causes the movable piece of the switch 10 to move. the so connected to the fixed terminal e, to insert a "1" immediately after the switching point P _C, further, the 1-bit data immediately after the switching point P _C "-
Invert from "1" to "1".

Next, a case where the determination result N _C is -4 will be described. When the determination result N _C is −4, when switching between two different systems, the energy shift due to the connection of discontinuous data is negative as a difference in the magnitude of the weight of the 2-bit data inversion. Occurs in the direction.
Therefore, in this case, the determination circuit 8, the switching signal processing means, inverts the 2-bit data immediately after the switching point P _C in the 1 "from" -1 ". That is, the determination circuit 8 switches the movable piece of the switch 4 from the selected terminal a to the selected terminal b, and connects the movable piece of the switch 10 to the selected terminal e for two samples.

Next, the case where the determination result N _C is -5 will be described. If the determination result N _C is 5, it is different 2
When switching the system, the energy shift due to the connection of discontinuous data should be equal to the weight of the data inversion for 2 bits and half the weight of the data inversion for 1 bit. The added difference occurs in the negative direction. Therefore, in this case, the determination circuit 8, the switching signal processing means, the data D _X of 1 bit to the switching point P _C causes inserted as "1", two bits of data immediately after the switching point P _C From "-1" to [1]
Need to be reversed. That is, the determination circuit 8 causes the movable piece of the switch 4 to switch from the selected terminal a to the selected terminal c, and causes the one-sample latch unit 7 to switch the switching point P.
Delay 1 bit of data immediately after _C by 1 sample,
The movable piece of the switch 10 to connect the fixed terminal e, to insert a "1" immediately after the switching point P _C, further, the 2-bit data immediately after the switching point P _C from "-1" [1 Invert. "

As described above, in the digital signal switching device according to the other embodiment, the switching point P by the determination circuit 8 is set.
1 by the judgment using 1 bit data before and after _C
Insert and switch the data for one bit, switch it without inserting it, switch it by inverting the data for one bit immediately after the switching point without inserting it, or switch it without inserting it, and Switching signal processing is performed to determine whether or not to switch the data for one bit, or to switch the insertion of the data for one bit and the inversion of the data for one bit or two bits at the same time. It is possible to switch signals with high quality.

The delay line sections 3 and 6 of the digital signal switching device of the embodiment shown in FIG. 1 and the digital signal switching device of the other embodiment shown in FIG.
Performs predetermined digital signal processing. FIG. 12 shows details of the digital signal processing circuit 6 that performs the above digital signal processing. That is, here, the delay line unit 6 is the digital signal processing circuit 6, and the delay line unit 3 is the delay unit 3 that delays the ΣΔ signal already obtained by the ΣΔ modulation. The digital signal switching device 1 including the digital signal processing circuit 6 is referred to as a digital signal processing device 17.

This digital signal processing device 17 has a ΣΔ already obtained by ΣΔ modulation via the input terminal 12.
A signal is input. The ΣΔ signal is supplied to the digital signal processing circuit 6 and the delay device 3.

The digital signal processing circuit 6 has an input terminal 1
Multiplier 13 which is an arithmetic means for performing an arithmetic operation on, for example, 1-bit digital data which is a ΣΔ signal supplied from 2 by controlling a multi-bit signal according to the 1-bit digital data, and this multiplier 13 And a ΣΔ modulation section 14 which is a minority bit conversion means for converting the output of 1 to 1-bit digital data again. Here, the multiplier 13 multiplies the 1-bit digital data by a multi-bit multiplication coefficient of 16 bits, which is a multi-valued multiplication coefficient generated by the coefficient generator 15 according to the 1-bit digital data. It is a multiplication means.

The coefficient generator 15 generates the above 16-bit multi-bit multiplication coefficient according to the command signal supplied to the control circuit 16. The control circuit 16 is supplied with a command signal for executing signal processing in the amplitude direction selected by the user, for example, fade processing. Then, the control circuit 16 causes the coefficient generator 15 to generate a multi-bit multiplication coefficient based on the command signal for executing the fade process.

The multi-bit output from the multiplier 13,
For example, 16-bit digital data is sent to the ΣΔ modulator
Is supplied to the adder 21 shown in FIG. The ΣΔ modulator 14 includes, in addition to the adder 21, an integrator 22 that performs integration processing on the addition output of the adder 21, and the integrator 22.
And a quantizer 23 for quantizing the data transmitted through 1 to 1-bit digital data for each sample period.
And a delay unit 24 for delaying the output of No. 3 by one sample period. The quantized output of the quantizer 23 is fed back to the adder 21 as a negative sign via the delay device 24,
It is added (and consequently subtracted) to the multiplication output of the multiplier 13.
Then, the 1-bit digital data which is the quantized output output from the quantizer 23 is taken out from the output terminal 18. The 1-bit digital data extracted from the output terminal 18 is the 1-sample latch unit 7 and the switch 4
Of the selected terminal b.

Here, the multiplier 13 has a binary state of the 1-bit digital data, that is, "1" or "-".
1 ”, as shown in FIG.
The 1-bit digital data is multiplied by a positive or negative 16-bit multi-bit multiplication coefficient. That is, the coefficient generator 1 is based on the command signal supplied to the control circuit 16.
The multi-bit multiplication coefficient generated by 5 is multiplied by the 1-bit digital data as a positive or negative multi-bit multiplication coefficient according to the binary state of the 1-bit digital data.

Here, the signal processing performed by the multiplier 13 on the 1-bit digital data is signal processing in the amplitude direction, such as fade processing, equalization processing, etc., which is a kind of attenuation processing. The processing performed in 13 will be described in a simplified manner, for example, signal processing that reduces the amplitude of the input signal to 1/2.

For example, the processing result of the digital signal processing circuit 6 in the case where the multiplier 13 is made to perform the operation for halving the amplitude of the input signal will be described with reference to FIG. FIG. 15A is a signal waveform diagram when 1-bit digital data supplied to the input terminal 12 is returned to an analog signal through an analog low-pass filter. FIG. 15B is a signal waveform diagram when the 1-bit digital data obtained by the signal processing performed by the digital signal processing circuit 6 is returned to an analog signal. That is, although the input and output bit lengths are the same 1 bit, the patterns are greatly different, and the amplitude of the analog audio signal obtained by passing through a simple analog filter is 1/2.

As described above, in the digital signal processing circuit 6, the multi-bit multiplication coefficient corresponding to the attenuation processing generated by the coefficient generator 15 or the mixing processing is applied to the multiplier 13 as a 1-bit input digital signal. Since the arithmetic operation is performed by controlling according to the binary state of the digital data, and the multi-bit multiplication output that is the arithmetic output is converted again into the 1-bit digital data that is the minority bit digital signal,
Wide band that a few bit digital signal has during transmission,
Utilizing the feature of high dynamic range, it realizes the transmission of high quality audio signals.

Then, the digital signal processing device 17
Can realize a process of switching the ΣΔ signal delayed by the delay device 3 and the ΣΔ signal that has been subjected to the fade process by being multiplied by the multi-bit multiplication coefficient while suppressing the generation of noise.

The digital signal processing device 17 ΣΔ-modulates the input audio signal to record it on the magnetic tape in the form of 1-bit digital data, reproduces the 1-bit digital data from the magnetic tape and outputs an analog audio signal. It is preferably applied to a digital audio recording / reproducing apparatus.

In this digital audio recording / reproducing apparatus, the input audio signal is subjected to ΣΔ modulation processing to obtain 1-bit digital data, and the 1-bit digital data is recorded together with a synchronization signal and an error correction code for every predetermined number of units. It comprises a recording section 30 as shown and a reproducing section 40 as shown in FIG. 17 for reproducing 1-bit digital data for each predetermined number of units reproduced from the magnetic tape 39 of the recording section 30. The digital signal processing device 17 is
Although provided in the reproducing unit 40, the recording unit 30 will be described first for convenience of description.

As shown in FIG. 16, in this recording section 30, the input audio signal from the input terminal 31 is added by the adder 3
2 to the integrator 33. The signal from the integrator 33 is supplied to the comparator 34, is compared with, for example, the midpoint potential (“0V”) of the input audio signal, and is quantized by 1 bit for each sampling period. Here, the frequency of the sampling period (sampling frequency) is 48 kHz of the conventional,
A frequency that is 64 times or 128 times that of 44.1 kHz is used.

This quantized data is a 1-sample delay unit 25.
And is delayed by one sample period. This delay data is supplied to the adder 32 through the 1-bit digital / analog (D / A) converter 36 and added to the input audio signal from the input terminal 31. As a result, the comparator 34 outputs quantized data in which the input audio signal is ΣΔ modulated. The quantized data output from the comparator 34 is the synchronization signal and the error correction code (E
It is supplied to the CC) addition circuit 37, and, for example, a synchronization signal and an error correction code are added to the quantized data for each predetermined number of samples.

In this recording format, as shown in FIG. 4, 1-bit digital data such as data D is recorded.
₀ and divided every four and so on to D _3, are added a synchronizing signal S _0, S ₁ and error correction codes P _0, P ₁ per this four 1-bit digital data. With this synchronization signal and the error correction codes P ₀ and P ₁ added by the ECC adding circuit 37,
It is possible to detect and correct transmission errors that occur during recording and reproduction.

Next, in the reproducing section 40 shown in FIG. 17, the reproducing head 41 reproduces the 1-bit digital data recorded on the magnetic tape 39. Since this 1-bit digital data is recorded in a format to which the sync signal and the error correction code are added every four data,
When supplied to the sync separation and error correction circuit 42, the sync signal is separated and subjected to error correction processing to extract only 1-bit digital data in units of 4 in which the above-mentioned input audio signal is ΣΔ modulated. This 1-bit digital data is supplied to the digital signal processing device 17.

The 1-bit digital data is processed by the digital signal processing device 17 as described above. The 1-bit digital data signal-processed by the digital signal processing device 17 is returned to the analog audio signal by the analog filter 43. This analog audio signal is taken out from the monitor terminal 44.

The re-ΣΔ modulation 1-bit digital data output from the digital signal processing device 17 is
A digital filter 45, which is a decimation filter, converts the signal into an arbitrary signal format such as CD or DAT. The signal converted into the arbitrary format is used as a reproducing system 46 of a digital recorder of an arbitrary format, a reproducing system 47 of a CD or DAT, or a DC.
It is supplied to a normal D / A converter 49 through the C reproducing system 48 and the like. Then, an analog audio signal is taken out from the output terminal 50.

Therefore, in the digital audio recording / reproducing apparatus to which the digital signal processing apparatus using the digital signal switching apparatus of the present embodiment is applied, the ΣΔ modulated digital signal of a few bits is multiplied by the multi-bit multiplication coefficient. As a result, it is possible to reproduce an audio signal in which the ΣΔ signal subjected to the fade process is switched while suppressing the generation of noise.

[0117]

As described above, according to the digital signal switching method of the present invention, one bit of data is inserted into the switching point according to the result of the determination using the data before and after the predetermined switching point, and the switching is performed. Since the data after the point is delayed, it is possible to suppress the generation of noise when switching signals of two different systems at the switching point.

Further, in the digital signal switching device according to the present invention, the judging means makes a judgment using the data before and after the predetermined switching point, and the switching signal processing means makes one bit worth based on the result of the judging means. Since the data is inserted, noise can be suppressed when the signals of two different systems are switched at the switching point.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of a digital signal switching device as an embodiment of a digital signal switching method and device according to the present invention.

FIG. 2 is a schematic diagram for explaining a switching operation of the digital signal switching device.

FIG. 3 is a block diagram showing a schematic configuration of a digital data interpolating device to which the decision circuit of the digital signal switching device applies the principle operation.

FIG. 4 is a recording format diagram of digital data.

FIG. 5 is a timing chart for explaining the operation of the interpolation processing unit of the digital data interpolation device.

FIG. 6 is a diagram for explaining coefficients when obtaining a moving average value of a defective data block.

FIG. 7 is an F used when an interpolation processing unit obtains a moving average value.
It is a circuit diagram which shows an IR filter.

FIG. 8 is a flowchart showing a specific operation of the digital data interpolation device.

FIG. 9 is a flowchart showing a detailed operation of the determination circuit of the digital data switching apparatus according to the above embodiment.

FIG. 10 is a characteristic diagram for explaining an effect of the digital data switching device.

FIG. 11 is a block diagram showing a schematic configuration of a digital data switching apparatus which is another embodiment of the digital data switching method and apparatus according to the present invention.

FIG. 12 is a block diagram showing a schematic configuration of a digital signal processing circuit included in a digital data switching device according to another embodiment.

FIG. 13 is a block diagram showing a detailed configuration of a ΣΔ modulator of the digital signal processing circuit.

FIG. 14 is a schematic diagram for explaining an operation of a multiplier which constitutes the digital signal processing circuit.

FIG. 15 is a characteristic diagram showing a processing result of the digital signal processing circuit.

FIG. 16 is a block diagram showing a schematic configuration of a recording unit of a digital audio recording / reproducing apparatus to which a digital signal processing unit including the digital signal processing circuit can be applied.

FIG. 17 is a block diagram showing a schematic configuration of a reproducing section of the digital audio recording / reproducing apparatus.

FIG. 18 is a block diagram showing a schematic configuration of a general ΣΔ modulation circuit.

FIG. 19 is a block diagram showing a schematic configuration of a signal processing unit that performs signal processing in the amplitude direction on a multi-bit digital audio signal.

FIG. 20 is a block diagram showing a schematic configuration of a conventional 1-bit digital data signal processing unit that performs signal processing in the amplitude direction on a 1-bit digital signal that is a ΣΔ signal.

FIG. 21 is a block diagram showing a schematic configuration of a conventional digital data switching device.

[Explanation of symbols]

 3 Delay Line Section 4 Switch 6 Delay Line Section 7 1 Sample Latch Section 8 Judgment Circuit

Claims (11)

[Claims] 1. A digital signal switching method for switching signals of two different systems from a predetermined switching point, wherein one bit of data is stored in accordance with a result of determination using data before and after the switching point. A digital signal switching method, characterized in that the data is inserted at a switching point and data after the switching point is delayed. 2. The digital according to claim 1, wherein it is not necessary to insert the 1-bit data into the switching point according to the result of the determination using the data before and after the switching point. Signal switching method. 3. The insertion of the data of 1 bit into the switching point is unnecessary according to the result of the determination using the data before and after the switching point, and at least 1 bit after the switching point. 2. The digital signal switching method according to claim 1, wherein the data in step 1 is inverted. 4. The digital signal switching method according to claim 1, wherein the two different systems of signals are subjected to two different sigma-delta modulation processes. 5. A digital signal switching device for switching signals of two different systems from a predetermined switching point, the determination means performing determination using data before and after the switching point, and a result of the determination means. And a switching signal processing means for inserting 1-bit data accordingly. 6. The determination means makes a determination based on a result of estimating the number of signals representing binary in a data block of a predetermined number of samples including data before and after the switching point. Item 5. The digital signal switching device according to item 5. 7. The switching signal processing means also generates the 1-bit data.
The described digital signal switching device. 8. The switching signal processing means delays the last data of the preceding and following data according to the result of the judging means, and then inserts the one bit data by a changeover switch. 6. The method according to claim 5, wherein
The described digital signal switching device. 9. The digital signal switching device according to claim 5, wherein the switching signal processing means does not need to insert the one-bit data into the switching point according to the determination result. . 10. The switching signal processing means eliminates the need to insert the 1-bit data into the switching point according to the determination result, and sets 1 after the switching point.
6. The bit data is inverted, and the bit data is inverted.
The described digital signal switching device. 11. The switching signal processing means inserts the 1-bit data at the switching point and inverts at least 1-bit data after the switching point according to the determination result. The digital signal switching device according to claim 5, wherein