JPH08288820A - Logic circuit - Google Patents

Abstract

PURPOSE: To provide a logic circuit which can prevent such a malfunction that is caused when the data are erroneously set in an internal register. CONSTITUTION: A logic circuit 1 includes h 1st register 1, a 2nd register 2, an AND gate circuit 3 which outputs a write signal to the register 2 when the 8th bit data of the register 1 are set at '1' and outputs no write signal to the register 2 when the 8th bit data of the register 1 are set at '0', and an AND gate circuit 4 which uses the 7th bit data of the register 1 and a reset signal as the input signals. When both registers 1 and 2 are reset by application of a power supply, the circuit 3 outputs no write signal to the register 2 since the 8th bit data of the register 1 are set at '0'. Therefore, it is impossible to set the register 2 before the register 1 is set. When the 7th and 8th bit data of the register 1 are set at '1', the circuit 3 can output a write signal to the register 2 and also can set the data in the register 2 since the reset state of the register 2 is canceled.

Description

Detailed Description of the Invention

[0001]

The present invention relates to logic circuits.

[0002]

2. Description of the Related Art Conventionally, logic ICs such as gate arrays
The logic circuit constituting the above has a plurality of internal registers.
A data bus and a data write signal line are connected to each internal register.

Data input through a data bus by a control device such as a CPU is set in an internal register according to a data write signal. When data is set in the internal register when the power is turned on or when the operation mode is changed, the operation mode of the logic circuit is selected, and the logic IC can perform various operations.

Since each internal register of the conventional logic circuit is independent, each internal register can set data at an arbitrary timing.

[0005]

However, due to the recent increase in the integration degree of logic ICs, one logic IC has been integrated.
It became possible to realize many functions and modes, and caused the following problems.

That is, in a logic circuit having a higher degree of integration of logic ICs, the data set in the registers have a circuit configuration in which they are related to each other and influence each other. The order may be predetermined, the setting data of one register may affect the data setting to the other register, or the setting data of one register may cause the other register to be unable to set data. is there.

Even in such a case, in the conventional logic circuit, the data setting operation of each internal register is independent and can be set at any timing, so that the data setting is performed in an incorrect order. Alternatively, data can be set in the other register that cannot be set by the setting data in one register. Therefore, when data is set by mistake, there is a problem that the logic circuit malfunctions without a means for knowing that the data has been set incorrectly.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a logic circuit capable of preventing malfunction due to erroneous data setting in an internal register.

[0009]

In order to achieve the above object, a logic circuit according to claim 1 of the present invention has a plurality of registers, and an internal operation is selected according to data set in the registers. The logic circuit includes a data setting permission unit that permits data setting in the second register by the data set in the first register among the plurality of registers.

According to a second aspect of the present invention, in the logic circuit according to the first aspect, when the data set in the first register is not data permitting data setting in the second register, the second circuit is set. It is characterized in that a reset means for resetting the register is provided.

According to a third aspect of the present invention, there is provided a logic circuit having a plurality of registers, the internal operation of which is selected according to data set in the registers. Data setting permission means for permitting data setting to the second register after data setting has been performed.

According to a fourth aspect of the logic circuit, in the logic circuit according to the first or third aspect, the data setting is performed by writing a plurality of bits of data in one write operation.

In the logic circuit according to a fifth aspect, in the logic circuit according to the first aspect, the data setting permission means uses a predetermined one bit or a plurality of bits of the data set in the first register. It is characterized in that data setting to the second register is permitted.

[0014]

In the logic circuit according to the first aspect of the present invention, when the internal operation is selected in accordance with the data set in the register, the second data is set in the first register by the data setting permission means. Allows data setting to the register of.

In the logic circuit according to the third aspect, when the internal operation is selected according to the data set in the register,
After the data setting is performed in the first register by the data setting permission means, the data setting in the second register is permitted.

[0016]

Embodiments of the logic circuit of the present invention will be described.

[First Embodiment] FIG. 1 is a circuit diagram showing the structure of a logic circuit according to the first embodiment. In the figure, 1 is a first register in which 8-bit data is set, and 2 is a second register in which 8-bit data is set.

The third register 3 outputs the second register write signal to the second register 2 when the 8th bit data of the first register 1 is "1", and the 8th bit of the first register 1 is output. It is an AND gate circuit that controls the write of the second register 2 so that the second register write signal is not output to the second register 2 when the data is “0”. An AND gate circuit 4 receives the 7th bit data of the first register 1 and the reset signal as input signals.

As described above, the data of the 7th bit and the 8th bit of the first register 1 is related to the circuit for setting the data of the second register 2, and the 7th bit and the 8th bit of the first register 1 are related. When the bit data is "0", data cannot be set in the second register 2.

The operation of the logic circuit having the above configuration will be described. When the power of the system using the logic IC is turned on, the reset signal is input and the first register 1 and the second register 2 are reset, and all are "0".
Is output. Since the 8th bit data of the first register 1 is “0”, the AND gate circuit 3 does not output the second register write signal. Therefore, the second register 2 cannot be set prior to the first register 1.

The data of the first register 1 is set and
When the 1st and 8th bits are set to "1", the AND gate circuit 3 can output the second register write signal to the second register 2 and also release the reset of the second register 2. The second register 2
It becomes possible to set data to.

After setting the data in the second register 2,
When the data “0” is set in the 7th bit of the first register 1, a reset signal is input to the second register 2 via the AND gate circuit 4, so that the second register 2
Is reset. As a result, 7 of the first register 1
It is possible to prevent "0" of the bit data and the setting data of the second register 2 from existing at the same timing.

[Second Embodiment] The logic circuit according to the second embodiment will be described below. FIG. 2 is a circuit diagram showing the configuration of the logic circuit of the second embodiment. In the figure, 1 is a first register in which 8-bit data is set, and 2 is a second register in which 8-bit data is set. A write control circuit 5 outputs the second register write signal to the second register 2 when the first register write signal is detected.

FIG. 3 is a circuit diagram showing the configuration of the write control circuit 5. In the figure, 51 is a D type flip-flop circuit (DF / F), and 52 is an AND gate circuit.

The operation of the logic circuit of the second embodiment having the above configuration will be described. When the system using the logic IC is powered on, a reset signal is input and the first register 1 and the second register 2 are reset. In addition, the DF / F 51 that constitutes the write control circuit 5
Is also reset, and the output Q of the DF / F 51 becomes "L". As a result, the output of the AND gate circuit 52 is always "L", and the second register write signal is not output.

When the data setting operation of the first register 1 is performed, the DF / F 51 inputs the first register write signal as a clock signal, so that the output Q becomes "H". This enables the AND gate 52 to output the second register write signal to the second register 2. Therefore, the second register 2 cannot set data before setting the data in the first register 1, and always sets the data after setting the data in the first register 1.

[0027]

According to the logic circuit of the first aspect of the present invention, when the internal operation is selected according to the data set in the register, it is set in the first register by the data setting permission means. Since the data setting to the second register is permitted by the data, the circuit operation that occurs when the specific bit of the first register and the setting of the second register are set at the same time or when they are not set in the correct order The above problems can be easily avoided. Therefore, it is possible to prevent malfunction due to erroneous data setting in the internal register.

According to the logic circuit of the second aspect, the reset means for resetting the second register when the data set in the first register is not the data permitting the data setting of the second register. Since it is provided, it is possible to reliably prevent erroneous data setting in the second register.

According to the logic circuit of the third aspect, when the internal operation is selected in accordance with the data set in the register, the first setting is performed after the data setting is performed by the data setting permission means. Since the data setting to the second register is permitted, it is possible to easily avoid the problem in the circuit operation that occurs when the data is not set in the correct order. Therefore, it is possible to prevent malfunction due to erroneous data setting in the internal register.

According to the logic circuit of the fourth aspect, since the data setting is performed by writing the data of a plurality of bits by one time, the data setting time can be suppressed to a short time.

According to the logic circuit of the fifth aspect, the data setting permission means sends the data set in the first register to the second register according to predetermined 1-bit or plural-bit data. Since the data setting of is permitted, it is possible to give permission according to various functions and modes.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of a logic circuit according to a first embodiment.

FIG. 2 is a circuit diagram showing a configuration of a logic circuit according to a second embodiment.

FIG. 3 is a circuit diagram showing a configuration of a write control circuit 5.

[Explanation of symbols]

 1 1st register 2 2nd register 3 and 4 AND gate circuit 5 Write control circuit

Claims (5)

[Claims] 1. A logic circuit having a plurality of registers, the internal operation of which is selected according to the data set in the registers, wherein the first register of the plurality of registers is set by the data set in the first register. 2. A logic circuit characterized by comprising data setting permission means for permitting data setting to the second register. 2. A reset means for resetting the second register when the data set in the first register is not data permitting data setting in the second register. The logic circuit according to item 1. 3. A logic circuit having a plurality of registers, the internal operation of which is selected according to the data set in the registers, wherein data setting is performed in a first register of the plurality of registers. A logic circuit characterized by further comprising data setting permission means for permitting data setting to the second register later. 4. The logic circuit according to claim 1, wherein the data setting is performed by writing a plurality of bits of data in one write operation. 5. The data setting permission means sets the second data according to a predetermined 1-bit or a plurality of bits of data set in the first register.
2. The logic circuit according to claim 1, wherein the setting of data in the register is permitted.