JPH08263456A - Diagnostic controller - Google Patents

Diagnostic controller

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Publication number
JPH08263456A
JPH08263456A JP6285195A JP6285195A JPH08263456A JP H08263456 A JPH08263456 A JP H08263456A JP 6285195 A JP6285195 A JP 6285195A JP 6285195 A JP6285195 A JP 6285195A JP H08263456 A JPH08263456 A JP H08263456A
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JP
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Patent type
Prior art keywords
card
control
diagnostic
fault
processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP6285195A
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Japanese (ja)
Inventor
Atsushi Hiraiwa
敦司 平岩
Original Assignee
Kofu Nippon Denki Kk
甲府日本電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Abstract

PURPOSE: To accelerate fault processing by providing specified connection memories in respective parallelly connected cards, reporting fault generation to a diagnostic processor(DGP) at such a time and parallelly performing diagnostic control inside the cards corresponding to an instruction from the DGP for each card.
CONSTITUTION: Respective CPU cards are composed of CPUs 2-1 to 2-4, system control parts 2-5 and diagnostic control parts 2-6 equipped with control memories 2-7 and the control memory 2-7 stores the respective routines of reset processing, initializing processing, constitution control processing, fault processing and diagnostic processing. When any fault is generated at the CPU inside the CPU card during ordinary operation, the fault processing routine in the control memory 2-7 is started and the generation of the fault is reported to a DGP 1-6. The DGP 1-6 discriminates the degree of that fault and outputs the instruction corresponding to this degree, and the control memory 2-7 parallelly performs diagnostic control inside the card for each card based on the instruction from the DGP 1-6.
COPYRIGHT: (C)1996,JPO

Description

【発明の詳細な説明】 DETAILED DESCRIPTION OF THE INVENTION

【0001】 [0001]

【産業上の利用分野】本発明は、診断制御装置、特にそれぞれが複数のCPUを搭載する複数のカードと診断プロセッサ(以下DGPと記す)をバス接続して構成された情報処理装置における診断制御装置に関する。 The present invention relates to a diagnostic controller, in particular each with a plurality of cards for mounting a plurality of CPU (hereinafter referred to as DGP) Diagnostic Processor diagnostic controller in the information processing apparatus that is configured by the bus connection apparatus on.

【0002】 [0002]

【従来の技術】従来、情報処理装置に分野では、シングルプロセッサによる性能が重視されていた為、密結合単位にDGPが存在し、またCPUが少なかった為、密結合を構成する各CPUとDGP間には個別に診断バスがあり、診断制御はこの診断バスを使うことによりDGP Conventionally, in the field to the information processing apparatus, since the performance of single processor has been emphasized, there is DGP in tight coupling unit, also since CPU was small, the CPU of the tightly coupled and DGP between has separate diagnostic bus, the diagnostic control DGP using this diagnostic bus
から直接可能であった。 It was possible directly from.

【0003】しかし、CPUを複数個搭載したカードをバス接続などにより並列接続させた情報処理装置では、 However, the card in which a plurality equipped with CPU in the information processing apparatus is connected in parallel by a bus connection,
DGPと各CPU間に診断バスを1対1に接続させるには、物理的に限度ある。 To connect the diagnostic bus to one-to-one between DGP and the CPU, physically certain limit. そこで、従来、各カード内にハードウエアによる診断制御部を設け、DGPからの指示を受けそれに応じた制御をハードウエアのみで行っている。 Therefore, conventionally, the diagnosis control unit by hardware provided in each card is performed only by hardware receiving control accordingly an instruction from DGP.

【0004】 [0004]

【発明が解決しようとする課題】上述した従来の診断制御装置では、DGPからの代表的な処理としてリセット、処理設定、構成制御、障害処理だけを考えても診断制御部をオールハードウエアで構成した場合、DGP− In [0006] Conventional diagnostic control apparatus described above, the reset as a typical process from DGP, process setting, configuration configuration control, it is considered only fault handling diagnostics control unit with all hardware If you, DGP-
CPU間の中継点に過ぎず、制御はDGPからこまめに指示を送り、処理内容によってはその都度正常に完了したことを確認するリプライを受けなければならない為、 Not only to the relay point between the CPU, control sends a diligently instructions from DGP, because that is by processing the contents shall receive a reply to confirm that you have completed successfully each time,
同時に複数のカードに対し行える処理は限られ、2つ以上のカードに違った処理を出す場合は、DGPで先の処理が完了したことを確認してからだすケースが大半でC At the same time the process that allows for multiple cards is limited, two or more when issuing a different process to the card, C the majority of cases where issues after confirming that the previous process is completed in DGP
PUの数が多ければ多いほど処理が遅れるという問題点がある。 Processing as a large number The more of PU there is a problem that delayed.

【0005】 [0005]

【課題を解決するための手段】本発明の装置は、演算部とシステム制御部により構成される中央処理部を1カード上に複数個搭載させ、該カードを並列接続させた情報処理装置における診断制御装置において、各カード内に障害処理と診断制御を行うルーチンを格納する制御記憶を設け、障害発生時に前記ルーチンを起動させることにより診断プロセッサへの報告を行うと共に、DGPからの指示によりカード内の診断制御をカード毎に並行して行う。 Apparatus of the present invention In order to achieve the above object, according to the central processing unit constituted by the arithmetic unit and the system controller is a plurality mounted on a card, diagnosis in an information processing device with parallel connected the card in the control device, a control store for storing routines for performing diagnosis control and fault processing in each card provided with a report of its diagnostic processor by activating the routine in the event of a failure, the card according to an instruction from the DGP perform diagnosis control of the parallel to each card.

【0006】 [0006]

【作用】本発明は、制御記憶を設けることによりDGP DETAILED DESCRIPTION OF THE INVENTION The present invention, DGP by providing control store
とCPUカード間でリセット、初期設定、構成制御等の処理を特定のCPUに対し継続的に行ったり、1つの処理のみを行えるコマンドを設け、DGPからはケースに応じて必要なコマンドを発行することにより診断制御部内の制御記憶を起動させることにより行い、DGPは送ったコマンドが正常に処理されたことを示す正常リプライが一定時間内に戻ったことにより処理が完了したことを認識できる。 Reset between CPU card, initialization, or perform processing of the configuration control and the like continuously for a particular CPU, a command that allows only one process provided and issues the necessary commands depending on the case from DGP performed by activating the control store in the diagnosis control unit by, DGP can recognize that the process is completed by normal reply indicating that the sent command was processed successfully returns within a predetermined time.

【0007】又、通常運用中、CPUカード内で何らかの障害が発生した場合も診断制御部内の制御記憶を起動させ、その障害が直ちにシステムを停止すべく重度な障害であるか、一部のCPUのみを論理的にシステムから切り離すことによりシステムの運用は継続的に行える軽度の障害であるかを判別させ、重度な障害時にはDGP [0007] Also, during normal operation, or if there is any failure in the CPU card has occurred also to activate the control store in the diagnosis controller is a serious obstacle in order to stop the fault immediately system, a portion of the CPU only logical operation system by disconnecting from the system causes the determination whether a mild disorder performed continuously, and during severe disorders DGP
にシステム停止を指示し、軽度な障害時には切り離したCPUを報告し、CPUの診断制御についてはDGPからのコマンド処理で行う。 To instruct the system stop, reporting a CPU disconnected during mild impairment, the diagnostic control of the CPU performs a command process from DGP.

【0008】 [0008]

【実施例】次に本発明の実施例について図面を参照して説明する。 It will be described with reference to the accompanying drawings embodiments of EXAMPLES The present invention will now.

【0009】図2は本発明の一実施例を示す図であり、 [0009] Figure 2 is a diagram showing an embodiment of the present invention,
それぞれが4つのCPUを搭載させたCPUカード1− CPU cards each of which is equipped with four CPU 1-
1〜1−4と、主記憶1−5を構成する1枚のカードをバス接続させ、各カード1−1〜1−5と診断プロセッサ1−6間に専用パスを設けている。 And 1~1-4, and main memory 1-5 one card constituting by bus connection and the dedicated path is provided between the diagnostic processor 1-6 and each card 1-1 to 1-5.

【0010】各CPUカードの構成は同一であり、図1 [0010] The configuration of each CPU card is the same, as shown in FIG. 1
に示すように、4つのCPU2−1〜2−4と、システム制御部2−5と、制御記憶2−7を備えた診断制御部2−6とにより構成される。 As shown in, composed of four CPU2-1~2-4, a system control unit 2-5, the diagnosis control unit 2-6 having a control store 2-7. 診断制御部2−6内の制御記憶2−7は図3に示すように、リセット処理3−1、 Control store 2-7 of the diagnostic control unit 2-6, as shown in FIG. 3, the reset process 3-1,
初期設定処理3−2、構成制御処理3−3、障害処理3 Initialization process 3-2, the configuration control process 3-3, fault handling 3
−4、診断処理3−5の各ルーチンを記憶する。 -4, storing each routine diagnostic process 3-5. 更に、 In addition,
CPUで障害が発生した場合の処理フローを図4及び図5に示す。 The processing flow when a failure occurs in the CPU shown in FIGS.

【0011】通常稼働中、CPUカード1−1内のCP [0011] During normal operation, CP in the CPU card 1-1
U2−1で障害が発生した場合、同一カード1−1内の障害処理ルーチン3−4が起動し、診断制御部2−6へ障害発生が報告され、診断制御部内の制御記憶2−7に起動がかかり、発生した障害がシステムを停止すべく重度な障害であった場合、制御記憶2−7からはDGP1 If a failure occurs in U2-1, start failure processing routine 3-4 in the same card 1-1, failure to diagnosis control unit 2-6 is reported, the control store 2-7 of the diagnosis control unit start-consuming, if the failure that has occurred is a serious obstacle in order to stop the system, from the control store 2-7 DGP1
−6に対しシステム停止指示が出され、DGP1−6が認知すると共にシステムダウンとなる。 -6 system stop instruction is issued to, the system down with DGP1-6-perceived.

【0012】一方、発生した障害がCPU2−1のみを論理的にシステムから切り離すことによりシステムの継続的な運用に支障を来さない軽度な障害である場合、制御記憶2−7からはDGP1−6に対し切り離すユニット(この場合、CPU2−1)を報告する。 Meanwhile, if the failure that has occurred is a mild disorder not hindrance to continuous operation of the system by disconnecting only CPU2-1 from logically systems, from the control store 2-7 DGP1- unit to separate for 6 (in this case, CPU2-1) report. DGP1− DGP1-
6は、各カード内の診断制御部に対しCPU2−1がシステムから切り離されたことを報告する。 6, CPU 2-1 to the diagnosis controller in each card to report that it was disconnected from the system. 各カード内の診断制御部では、制御記憶部内の構成制御ルーチン3− The diagnosis control unit in each card, configuration control routine in the control store 3-
3が起動しCPU2−1とのインタフェースを論理的に切り離す。 3 is logically disconnect the interface of the CPU2-1 start. 更に、CPUカード1−1の制御記憶2−7 Further, the control storage of the CPU card 1-1 2-7
はCPU2−1の障害情報を主記憶1−5の障害情報格納領域に送出する。 Sends the failure information CPU2-1 the fault information storing area of ​​the main storage 1-5.

【0013】DGP1−6は、全カードからのリプライを受けるとCPUカード1−1内の診断制御部2−6に対しCPU2−1のリセットを指示する。 [0013] DGP1-6 receives a reply from all cards to the diagnosis control unit 2-6 in the CPU card 1-1 instructs the reset of the CPU 2-1. CPUカード1−1の診断制御部2−6より制御記憶2−7内のリセット処理ルーチン3−1が起動しCPU2−1がリセットされる。 Diagnosis control unit 2-6 from the control store reset processing routine 3-1 in 2-7 starts CPU2-1 the CPU card 1-1 is reset.

【0014】DGP1−6はCPUカード1−1の診断制御部2−6よりリプライを受けると、CPUカード1 [0014] DGP1-6 receives a reply from the diagnosis control unit 2-6 of the CPU card 1-1, CPU card 1
−1内の診断制御部2−6に対しCPU2−1へのFW To diagnosis control unit 2-6 in the -1 FW to CPU2-1
ロードを指示する。 To indicate the load. CPUカード1−1の診断制御部2 Diagnosis control unit 2 of the CPU card 1-1
−6より制御記憶2−7内の初期設定処理ルーチン3− Initialization processing routine of the control store within 2-7 than -6 3-
2が起動し、CPU2−1へFWがロードされる。 2 starts, FW is loaded into CPU2-1.

【0015】DGP1−6はCPUカード1−1の診断制御部2−6よりリプライを受けると、CPUカード1 [0015] DGP1-6 receives a reply from the diagnosis control unit 2-6 of the CPU card 1-1, CPU card 1
−1内の診断制御部2−6に対しCPU2−1へのテストプログラム起動を指示する。 To diagnosis control unit 2-6 in the -1 to indicate a test program started to CPU 2-1. CPUカード1−1の診断制御部2−6より制御記憶内2−7の診断処理ルーチン3−5が起動し、CPU2−1ではテストプログラムが実行される。 Start diagnostic routine 3-5 in the control storage in 2-7 from the diagnosis controller 2-6 of the CPU card 1-1, the CPU2-1 test program is executed. テストプログラム実行において障害の再発の有無をDGP1−6へ報告する。 To report the presence or absence of a recurrence of a disorder to DGP1-6 in the execution test program.

【0016】DGP1−6は障害再発によりCPU2− [0016] DGP1-6 is due to a failure recurrence CPU2-
1に固定障害有りと見なし以降CPU12−1切り離し状態で運用を継続する。 Continue to operate in CPU12-1 disconnected state and later considered that there is a fixed failure to 1. 又、障害再発無であればCPU In addition, CPU if Mu failure recurrence
2−1の再度組み込み可能と見なし全カードの診断制御部2−6に対し、CPU2−1のシステムへの組み込みを報告する。 To diagnosis control unit 2-6 of the entire card again regarded as possible incorporation of 2-1, reports the incorporation into CPU2-1 system. 各カード内の診断制御部2−6より制御記憶部2−7内の構成制御ルーチン3−3が起動しCPU Configure start control routine 3-3 diagnostic controller 2-6 control storage unit 2-7 from within each card CPU
2−1とのインタフェースが論理的に接続される。 2-1 and interfaces are logically connected. これ以降、システムは障害発生以前と同状態で稼働する。 After this, the system is running in the previous failure and the same state.

【0017】以上、図4に示すフローに沿って1つの障害発生時の処理過程を説明したが、2つの障害が同時に起きた場合、図4に示すリセット処理ルーチン、処理設定処理ルーチン、診断処理ルーチンは同時に起動させることも可能である。 [0017] Having described the process when one failure along the flow shown in FIG. 4, when two failures occur simultaneously, the reset processing routine shown in FIG. 4, the process setting routine, the diagnostic process routine is also possible to start at the same time.

【0018】 [0018]

【発明の効果】以上説明したように本発明は、グループ(カード)単位のCPUに診断制御専用の制御記憶を設けたことにより、所望のCPUに対しDGPが必要とする処理をコマンドを発行するだけで可能である。 The present invention described above, according to the present invention, by providing a diagnostic control dedicated control store in the group (card) units of the CPU, and issues a command processing required by the DGP to desired CPU it is possible in only. 又、本発明はCPUを複数個並列接続させたシステムにおいては、異なるグループで発生した障害においては、その処理を個別に実行できる為、従来に比べて障害処理が高速化される。 Further, the present invention is in a system with a plurality connected in parallel CPU, in the failure occurring in different groups, since it executes the processing individually, fault processing than the conventional is faster.

【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS

【図1】図2に示した各CPUカードの詳細図である。 1 is a detailed view of the CPU card shown in FIG.

【図2】本発明の一実施例のブロック図である。 2 is a block diagram of an embodiment of the present invention.

【図3】図2に示した制御記憶部内に保持する制御ルーチンの一例を示す図である。 3 is a diagram showing an example of a control routine for holding the control store portion shown in FIG.

【図4】本発明における障害発生時の処理フローチャートである。 4 is a process flowchart at the time of fault occurrence in the present invention.

【図5】本発明における障害発生時の図4に続く処理フローチャートである。 5 is a flowchart subsequent to FIG. 4 in the event of a failure in the present invention.

【符号の説明】 DESCRIPTION OF SYMBOLS

1−1〜1−4 CPUカード 1−5 主記憶 1−6 診断プロセッサ(DGP) 2−1〜2−4 CPU 2−5 システム制御部 2−6 診断制御部 2−7 制御記憶。 1-1 to 1-4 CPU card 1-5 main storage 1-6 diagnostic processor (DGP) 2-1~2-4 CPU 2-5 system control unit 2-6 diagnosis controller 2-7 control store.

Claims (2)

    【特許請求の範囲】 [The claims]
  1. 【請求項1】 演算部とシステム制御部により構成される中央処理部を1カード上に複数個搭載させ、該カードを並列接続させた情報処理装置における診断制御装置において、各カード内に障害処理と診断制御を行うルーチンを格納する制御記憶を設け、障害発生時に前記ルーチンを起動させることにより診断プロセッサへの報告を行うと共に、前記診断プロセッサからの指示によりカード内の診断制御をカード毎に並行して行う診断制御装置。 1. A plurality is mounted constituted central processing unit on one card by the computing unit and the system controller, the diagnostic controller in the information processing apparatus was connected in parallel to said card, failure processing in each card the control store for storing routines for performing diagnosis control and provided, together with a report of its diagnostic processor by activating the routine in the event of a failure, parallel diagnosis control in the card for each card by an instruction from the diagnostic processor diagnostic control device that was carried out.
  2. 【請求項2】 前記障害が重障害か否かを前記カード内で判断して前記診断プロセッサに報告し、該診断プロセッサは重障害ならシステムを停止し、重障害でなければ障害プロセッサへは障害情報の出力、他のプロセッサへは障害プロセッサの切り離しを指示することを特徴とする請求項1記載の診断処理装置。 2. A report whether the fault is grave fault to the diagnostic processor to determine within the card, the diagnostic processor stops if grave fault system, failure to failure processor if not grave fault output information, diagnostic apparatus according to claim 1, wherein the instructing the fault isolation processor to another processor.
JP6285195A 1995-03-22 1995-03-22 Diagnostic controller Granted JPH08263456A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6285195A JPH08263456A (en) 1995-03-22 1995-03-22 Diagnostic controller

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Application Number Priority Date Filing Date Title
JP6285195A JPH08263456A (en) 1995-03-22 1995-03-22 Diagnostic controller

Publications (1)

Publication Number Publication Date
JPH08263456A true true JPH08263456A (en) 1996-10-11

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Application Number Title Priority Date Filing Date
JP6285195A Granted JPH08263456A (en) 1995-03-22 1995-03-22 Diagnostic controller

Country Status (1)

Country Link
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008003652A (en) * 2006-06-20 2008-01-10 Hitachi Ltd Diagnosis method for circuit board, circuit board and cpu unit
JP2008293276A (en) * 2007-05-24 2008-12-04 Sony Corp Digital cinema reproduction system, showing suspension corresponding method, and program
US8230260B2 (en) 2010-05-11 2012-07-24 Hewlett-Packard Development Company, L.P. Method and system for performing parallel computer tasks

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02244252A (en) * 1989-03-17 1990-09-28 Hitachi Ltd One-chip multiprocessor containing bus arbiter and comparator
JPH04149660A (en) * 1990-10-09 1992-05-22 Oki Electric Ind Co Ltd Multiprocessor system
JPH0535706A (en) * 1991-07-31 1993-02-12 Nec Corp Multiprocessor system
JPH05120129A (en) * 1991-05-15 1993-05-18 Internatl Business Mach Corp <Ibm> Memory system

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02244252A (en) * 1989-03-17 1990-09-28 Hitachi Ltd One-chip multiprocessor containing bus arbiter and comparator
JPH04149660A (en) * 1990-10-09 1992-05-22 Oki Electric Ind Co Ltd Multiprocessor system
JPH05120129A (en) * 1991-05-15 1993-05-18 Internatl Business Mach Corp <Ibm> Memory system
JPH0535706A (en) * 1991-07-31 1993-02-12 Nec Corp Multiprocessor system

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008003652A (en) * 2006-06-20 2008-01-10 Hitachi Ltd Diagnosis method for circuit board, circuit board and cpu unit
US7870428B2 (en) 2006-06-20 2011-01-11 Hitachi, Ltd. Method of diagnosing circuit board, circuit board, and CPU unit
JP2008293276A (en) * 2007-05-24 2008-12-04 Sony Corp Digital cinema reproduction system, showing suspension corresponding method, and program
US8230260B2 (en) 2010-05-11 2012-07-24 Hewlett-Packard Development Company, L.P. Method and system for performing parallel computer tasks

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