JPH08249891A - Nonvolatile memory - Google Patents

Abstract

PURPOSE: To simultaneously specify desired plural memory blocks in accordance with a situation and to shorten erasing time and the like by enabling selecting combination of selecting signal lines. CONSTITUTION: A row decoder 2' receives a signal NN externally specifying the number of memory blocks constituting an erasing unit other than row address signals A4 -A7 and a control signal CTL, and inputs it to a block numbers setting circuit 25. When the CTL indicates erasing, each pair of signal A4 '-A7 ' is generated in accordance with NN based on the signals A4 -A7 , and they are converted to word signals WL1-WL6 through NAND circuits LA1-LA16, NOT circuits LB1-LB16, and transistors LC1-LC16. One of any word signals is selected when performing read-out and write-in, and in the case of erasing, only NN numbers are simultaneously selected, and memory blocks of NN pieces are specified as an erasing unit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-volatile memory, and more particularly to a non-volatile memory in which memory cells are selected by addressing.

[0002]

2. Description of the Related Art A flash memory is a non-volatile memory and is composed of a plurality of blocks. A block is a minimum unit memory block for erasing data. The block size is determined by the device configuration of the flash memory and is not standardized.

In a flash memory, data is erased not only when erasing data stored in a memory cell but also when rewriting data stored in a memory cell. Due to the nature of the memory cell having a floating gate, in order to rewrite data, it is necessary to write data in the memory cell after erasing data once.

For example, when image data is stored in a flash memory, the data is read or written in units of image data of one frame. 1
The image data of the frame is encoded into a fixed size of 8 Kbytes, for example. In this case, the image data of 8 Kbytes is accessed every time.

For example, if the block size, which is the erase unit, is 4 Kbytes, data is erased with 4 Kbytes as the minimum unit size. In order to rewrite the image data of 8 Kbytes, it is necessary to erase the data of two blocks first. In order to erase the data of two blocks, it is necessary to specify two block addresses. 8
To rewrite the K-byte image data, first, two blocks of data are erased, and then new 8 K-byte image data is written.

[0006]

When the unit of data stored in the flash memory is a fixed amount, the same number of blocks of data may be erased at all times. However, since the block size is determined by the device specifications of the flash memory, it is difficult to specify the block size that matches the size of image data.

When it is desired to erase a data amount larger than the block size, it is necessary to specify a plurality of block addresses, so that it takes a long time to erase the data. An object of the present invention is to provide a non-volatile memory in which the size of the memory block can be changed according to the usage environment.

[0008]

The non-volatile memory of the present invention is a non-volatile memory that generates a selection signal for selecting a memory cell based on an address signal supplied from the outside. A combination setting means capable of changing and setting the combination of the selection signals generated in the above, and a selection signal generating means for generating the selection signal in a combination according to the setting of the combination setting means based on the address signal. .

[0009]

Since the selection signal lines can be selected in a predetermined combination, when the address signal is designated from the outside, the memory cell regions of different sizes can be specified according to the use environment. For example, when erasing data,
If it is set to always select one selection signal line, one predetermined memory block is specified, and if it is specified that two selection signal lines are simultaneously selected, two predetermined memory blocks are specified.

[0010]

FIG. 2 is a schematic diagram showing the structure of a non-volatile memory according to an embodiment of the present invention. The memory cell array 1 is
It is a two-dimensional memory cell matrix. Each memory cell can store data “1” or “0”,
It is specified by addresses A0 to A7 supplied from the outside. A0 indicates the least significant bit and A7 indicates the most significant bit.

The addresses A0 to A3 are column addresses, and the addresses A4 to A7 are row addresses. Each memory cell of the two-dimensional memory cell array 1 has a row address A4 ...
A matrix is designated by A7 and column addresses A0 to A3.

The column addresses A0 to A3 are input to the column decoder 3. The column decoder 3 is a 4-line / 16-line decoder, inputs the address signal lines A0 to A3 of 4 lines, and outputs the decoded signal to 16 bit lines BL of which only one line is at a high level. .

The row addresses A4 to A7 are input to the row decoder 2. The row decoder 2 is a 4 line / 16 line decoder. The row decoder 2 causes the four lines of addresses A4 to A7 to have word lines WL1 to WL16 in which only one of the 16 lines is at a high level.
It is decoded into the signal above. The memory cell array 1 is specified by the word line WL and the bit line BL which become high level.

In the case of a flash memory, data is usually written or read in units of memory cells connected to one word line. Since 16 bit lines BL are connected to one word line,
The unit of reading and writing is 16 bytes. Actually 25
Although it is about 6 bytes, the case of 16 bytes will be described below for the sake of clarity.

The memory block BA1 is the minimum unit for erasing data. Here, a case where the data erasing unit and the reading / writing unit are the same will be described. The data erase unit and the read / write unit do not have to be the same,
Generally, the data erasing unit is larger and is about 4 Kbytes, but thereafter, the memory block BA1 which is a data erasing unit is 16 bytes, and the read / write unit is the same.
A case of 6 bytes will be described.

Data is erased in units of memory blocks. For example, when the word line WL1 is selected by the row decoder 2, the memory block BA1 is erased. Similarly, by selecting 16 word lines WL1 to WL16, the corresponding memory blocks BA1 to BA16 are erased.

Conventionally, data can be erased only in units of memory blocks. In this embodiment,
Data can be erased by designating the size of the memory block, which is twice or four times, as the erase unit.

FIG. 1 is a conceptual diagram showing an erase unit of the nonvolatile memory according to this embodiment. FIG. 1 (A) divides the entire memory area into 16 parts, FIG. 1 (B) divides the entire memory area into 8 parts, and FIG. 1 (C) divides the entire memory area into 4 parts, and erases data in units of each divided area. 3 shows a non-volatile memory for performing.

FIG. 1A shows a nonvolatile memory in which 1/16 of the total memory is used as an erase unit. 1/16 of all memory
16 erase units BA1 to BA
16 are generated. The erase units BA1 to BA16 have the same size as the memory block (16 bytes), and are the minimum erase units. It is not possible to create an erase unit smaller than a memory block.

The row addresses A4 to A7 of 4 lines are decoded into the word signals WLA1 to WLA16 of 16 lines by the row decoder 2 as described above. The memory cell is specified by setting any one of the word signals WLA1 to WLA16 to the high level. For example,
If the word signal WLA1 is set to the high level, the erase unit B
A1 is specified and 16 bytes of data is erased.

FIG. 1B shows a non-volatile memory in which 1/8 of the entire memory is an erase unit. Eight erase units BB1 to BB8 are generated by dividing the entire memory into 1/8. The erase units BB1 to BB8 are twice as large as the memory block (32 bytes).

Actually, row addresses A4 to A of four lines are used.
7 is input to the row decoder 2 and is decoded into 8-line word signals WLB1 to WLB8 based on the row address A5 to A7 of the upper 3 bits. The memory cell is specified by setting any one of the word signals WLB1 to WLB8 to the high level. For example, if the word signal WLB1 is set to the high level, the erase unit BB
1 is specified, and 32 bytes of data are erased.

FIG. 1C shows a non-volatile memory in which 1/4 of the entire memory is an erase unit. By dividing the entire memory into 1/4, four erase units BC1 to BC4 are generated. The erase units BC1 to BC4 are four times as large as the memory block (64 bytes).

Although row addresses A4 to A7 of 4 lines are actually input to the row decoder 2, word signals WL of 4 lines are generated based on the row addresses A6 to A7 of the upper 2 bits.
Decode to C1 to WLC4. Word signal WLC1 ~
A memory cell is specified by setting any one of WLC4 to a high level. For example, if the word line WLC1 is set to the high level, the erase unit BC1 is specified and 64 bytes of data are erased.

FIG. 3 is a conceptual diagram showing an erase unit of the nonvolatile memory according to this embodiment. By dividing the entire memory into 16, 16 erase units BA1 to BA16 are generated. The erase units BA1 to BA16 have the same size (16 bytes) as the memory block.

When the entire memory is divided into eight, four, two, and one, eight erasing units BB1 to BB8 and 4 respectively.
Erase units BC1 to BC4, two erase units BD1 to
BD2 and one erase unit BE1 are generated. Erase units BB1 to BB8, BC1 to BC4, BD1 to BD2, B
E1 has a size of 32 bytes, 64 bytes, 128 bytes, and 256 bytes, respectively.

In a normal use state of the nonvolatile memory, the memory block serves as an erase unit, and 16 erase units BA
1 to BA16 are set. Row addresses A4 to A7 and erase units BA1 to B when erasing data
The relationship of A16 is shown below. However, each address signal A4
A to A7 represent a high level by “H” and a low level by “L”.

[0028]

[Table 1]

Next, the case where the erase unit is set to 8 will be described. To set eight erase units BB1 to BB8, the address signal A4 is fixed to "H" regardless of the addresses A4 to A7. This allows BA1 and BA
2 is simultaneously specified as the erase unit BB1. Similarly, BA3 and BA4, BA5 and BA6, BA7 and BA
8, BA9 and BA10, BA11 and BA12, BA13
And BA14 and BA15 and BA16 are a set of erasing units BB2, BB3, BB4, BB5, BB6, and BB, respectively.
7, identified as BB8.

To set four erase units BC1 to BC4, the address signal A is set regardless of the addresses A4 to A7.
4, A5 is fixed to "H". This allows BB1 and B
B2 is simultaneously specified as the erase unit BC1. Similarly, BB3 and BB4, BB5 and BB6, BB7 and BB8
Are specified as erasing units BC2, BC3, and BC4 in each set.

In order to set the two erase units BD1 and BD2, the address signal A is set regardless of the addresses A4 to A7.
Fix 4, A5 and A6 to "H". This allows BC
1 and BC2, BC3 and BC4 are respectively identified as erase units BD1 and BD2 in pairs.

To set one erase unit BE1, the address lines A4 and A are set regardless of the addresses A4 to A7.
Fix 5, A6 and A7 to "H". This allows BD
1 and BD2 are specified as an erase unit BE1 in combination.

As described above, according to this embodiment, regardless of the row addresses A4 to A7 supplied from the outside, the arbitrary bits from the lower bits of the address signals A4 to A7 are fixed to "H", so that 16 Any erase unit from division to one division can be set. External row address A4
When .about.A7 is supplied, it is possible to erase data in an area having an arbitrary size. Also, depending on the usage environment,
The size of the erase unit can be changed to a desired value.

A circuit configuration for realizing the above nonvolatile memory will be described below. FIG. 4 is a block diagram showing the overall configuration of the non-volatile memory. The booster circuit 5 generates a high voltage by boosting. The write / erase control circuit 6 is connected to the booster circuit 5 and receives a control signal CTL and write data Din supplied from the outside. The control signal CTL is a signal for instructing data reading, writing, erasing, and the like.

The addresses A0 to A7 are stored in the address buffer 4. The column address A0 to A3 is the column decoder 3
, And the row addresses A4 to A7 are supplied to the row decoder 2. The column decoder 3 outputs 16 signal lines for controlling the transistor 12 to select the bit line BL. The transistor 12 is an n-channel MOS transistor. By turning on the transistor 12, the drain and source are brought into conduction, and the bit line BL can be selected.

The row decoder 2 outputs a 16-line signal for controlling the memory cell 13 via the control gate booster circuit 8 to select the word line WL. The memory cell 13 is a memory cell arranged in the memory cell array 1 and is an EEPROM.

The control signal CTL is input to the row decoder 2. A high voltage is input to the control gate booster circuit 8 from the booster circuit 5, and the high voltage is supplied to the control gate of the memory cell according to the decoding of the row decoder 2 to perform writing or the like. Further, the column decoder 3 is also supplied with a high voltage from the booster circuit 5, and the control signal CT is externally supplied.
L is supplied.

The write / erase control circuit 6 controls the control signal C.
The gate of the n-channel MOS transistor 11 is controlled according to TL. For example, if the write data Din is “0”, the transistor 11 is turned on, and if the write data Din is “1”, the transistor 11 is turned off.

The transistor 11 is connected to the transistor 12. The transistor 12 is controlled by the column decoder 3, and the write data Din is supplied to a predetermined memory cell 13. The method of writing to the memory cell 13 will be described later.

The sense amplifier circuit 7 is connected to the source / drain of the transistor 11, amplifies the data stored in the memory cell 13, and outputs the read data Do to the outside.
Output as ut.

FIG. 5 is a circuit diagram showing a structure of row decoder 2 of FIG. The row decoder 2 has a division number setting circuit 20 for determining the size of the erase unit. The number of divisions of all the memories can be set depending on whether or not writing is performed in the transistor Tr1 in the division number setting circuit 20.

The row decoder 2 also has a control signal generating circuit 23. The control signal generation circuit 23 controls the control signal CT.
Input L and output signals -E, M, -B, -PE.
The control signal CTL includes signals for instructing read, write, and erase.

The control signal generation circuit 23 controls the control signal CTL.
The following signal levels are output according to the type. However, the high level is, for example, 5 V and is represented by “H”.
The low level is, for example, 0 V and is represented by "L". "H
/ L "indicates that it may be a high level or a low level and may be an arbitrary level.

[0044]

[Table 2]

The row address signal lines A4 to A7 are each an enhancement type n-channel transistor Tra4.
~ Signal line A4 'via the source / drain of Tra7
~ A7 '.

The row address signal lines A4 to A7 are
The respective NOT circuits LD4 to LD7 are level-inverted and connected to the signal lines -A4 to -A7, respectively. The signal lines -A4 to -A7 are connected to the signal lines -A4 'to -A7' via the sources / drains of the enhancement type n-channel transistors Trb4 to Trb7.

The signal -PE generated by the control signal generating circuit 23 is input to the gates of the transistors Tra4 to Tra7 and the transistors Trb4 to Trb7. The signal lines A4 'to A7' and -A4 'to -A7' are 16 NAND circuits LA1 to LA1 in a predetermined combination.
6 input terminals.

The NAND circuit LA1 has a signal -A4 ',
-A5 ', -A6', -A7 'are input. NAND
The circuit LA1 has address signals A4 to A7 = "0000".
"L" is output only when Otherwise, "H" is output. Note that “0000” indicates a higher-order bit signal from the left to the right, and the right end indicates the signal A.
7

The NAND circuit LA2 has the signals A4 ',-
A5 ', -A6', -A7 'are input. The NAND circuit LA2 outputs "L" only when the address signals A4 to A7 = "1000", and otherwise outputs "L".
Output "H". However, "1000" means A4 =
"1" and A5 to A7 = "0" are shown.

The NAND circuit LA16 has signals A4 ',
A5 ', A6', A7 'are input. NAND circuit L
A16 outputs "L" only when the address signals A4 to A7 = "1111", and otherwise,
Output "H". NAND circuits LA3 to LA other than the above
Similarly, four signals of a predetermined combination are input to A15.

As described above, only one of the 16 NAND circuits LA1 to LA16 outputs "L" according to the address signals A4 to A7. Other than that,
Output "H".

The output terminals of the NAND circuits LA1 to LA16 are connected to the input terminals of the NOT circuits LB1 to LB16, respectively. The output terminals of the NOT circuits LB1 to LB16 are connected to the word lines WL1 to WL16 via the sources / drains of the depletion type n-channel transistors LC1 to LC16, respectively. Word line W
L1 to WL16 are connected to the memory cell array 1.

Next, the division number setting circuit 20 will be described.
In the figure, only the division number setting circuit 20 connected to the signal lines -A4, -A4 'with the transistor Tr4 sandwiched is shown, but a similar circuit 20 has seven other transistors Tra4 to Tra7, The signal lines corresponding to Trb5 to Trb7 are also connected.

Since the eight division number setting circuits 20 all have the same circuit configuration, the portion connected to the transistor Trb4 will be described as an example. The node N2 of the division number setting circuit 20 is connected to the signal line -A4, and the node N4 is connected to the signal line -A4 '.

The signals -E, M, -B are signals generated by the control signal generation circuit 23 described above, and the control signal CT
The level is set as shown in Table 2 according to the type of L.
The signal -E is supplied to the node N1. Node N1
It is connected to the ground terminal via the n-channel transistor Tr2 and the non-volatile transistor Tr1. The non-volatile transistor Tr1 is an EEPROM. The signal M is supplied to the gate of the transistor Tr2. The signal -B is supplied to the gate of the transistor Tr1.

The nodes N1 and N2 are connected to the NOR circuit 2
1 is connected to the input terminal. The output terminal of the NOR circuit 21 is the node N3. The node N3 has a NOT circuit 22.
Connected to the input terminal of. The node N4 has a NOT circuit 2
2 output terminals.

The transistor Tr1 is a transistor for setting the number of divisions that determines the size of the erase unit.
The transistor Tr1 has a total of eight division number setting circuits 20.
There are eight pieces, so eight pieces are provided correspondingly. The division number is set depending on whether or not writing is performed in each transistor Tr1.

Writing to Tr1 is performed by the following signal settings. M = “L” −B = 20V By setting the signal M to “L”, the transistor T
r2 is turned off. When the signal -B is set to a high voltage of about 20V, electrons are injected into the floating gate of the transistor Tr1 and the writing state is set.

On the other hand, the data erase of Tr1 is performed by the following signal settings. M = “L” −B = “L” Substrate of Tr1 = 20V By setting the signal M to “L”, the transistor T
r2 is turned off. When the signal -B is set to "L" and a high voltage of about 20 V is applied to the substrate (or well) of the transistor Tr1, electrons are emitted from the floating gate of the transistor Tr1 and the erase state is set.

The relationship between the number of divisions and the transistor Tr1 is shown below. The number of divisions is the address signal lines A4 to A7, -A
Eight transistors T provided corresponding to 4 to -A7
It depends on the write state of r1. The ∘ mark indicates a state where the transistor Tr1 is written, and the X mark indicates a state where the transistor Tr1 is not written.

[0061]

[Table 3]

Next, the operation of the division number setting circuit 20 will be described for each type of the control signal CTL.

FIG. 6 is a diagram for explaining the operation of the division number setting circuit 20 at the time of reading and writing. Table 2
As shown in, the signal −E = “L” and the signal M = “L” are set in both reading and writing. The transistor Tr2 has a signal M supplied to its gate.
Is "L", it is turned off. When the transistor Tr2 is off, although not shown, the node N1 becomes "L", which is the same as the signal -E, regardless of the writing state of the transistor Tr1.

The node N2 has the same level as the inverted signal -A4 of the input address signal A4, and is "L" or "H".
Take one of the levels. The nodes N1 and N2 are connected to the input terminals of the NOR circuit 21. Node N
1 has the level fixed to "L", and the node N2
Is a node whose level can change. Node N3 is
The output terminal of the NOR circuit 21 has a level opposite to that of the node N2.

The node N3 is connected to the input terminal of the NOT circuit 22. The node N4 is an output terminal of the NOT circuit 22 and has a level opposite to that of the node N3. That is, the node N4 takes the same level as the node N2.

The above level changes are shown together. The nodes N3 and N4 take the following levels according to the level of the node N2 (signal-A4). However, the node N1
It is fixed at "L".

[0067]

[Table 4]

Next, referring to FIG. 5, a description will be given of reading and writing. As shown in Table 4, the node N2 and the node N4 are irrespective of the state of the transistor Tr1.
Will always be at the same level. Also, the transistor Trb
Whether node 4 is on or off, node N2 and node N4 are at the same level. Therefore, the transistor Trb4
The signal-PE that controls the signal-PE need not be considered. However, the signal-PE has an important meaning when erasing data described later.

Since the node N4 and the node N2 are at the same level, the signal line -A4 (node N2) and the signal line -A4 '.
(Node N4) is at the same level. The following relationships are established during reading and writing.

A4 '= A4-A4' =-A4 A5 '= A5-A5' =-A5 A6 '= A6-A6' =-A6 A7 '= A7-A7' =-A7

Therefore, the input address signals A4 to A7
Accordingly, as described above, the NAND circuits LA1 to LA1 are
Only one of 6 becomes "L". The difference between reading and writing is that the transistors LC1 to L
This is the level of the signal -PE input to the gate of C16. As shown in Table 2, the signal -PE is set to "H" during reading and set to "L" during writing.

First, reading will be described. For example, when only the NAND circuit LA1 outputs “L”,
The NOT circuit LB1 outputs "H". Transistor L
"H" is supplied to the source / drain of C1. Since the signal -PE = "H" is supplied to the gate of the transistor LC1, the transistor LC1 is turned on. When the transistor LC1 is turned on, the output of the NOT circuit LB1 =
"H" is transmitted to the word line WL1. Word line W
Since L1 is connected to the gate of the memory cell, when the word line WL1 becomes “H”, data can be read from the memory cell.

On the other hand, at the time of reading, when the NAND circuit LA1 becomes "H", the output of the NOT circuit LB1 becomes "L" and the word line WL1 becomes "L". When the word line WL1 becomes "L", the memory cell is off, so that no data is read.

Next, writing will be described. For example, when only the NAND circuit LA1 outputs “L”,
The NOT circuit LB1 outputs "H". Transistor L
The signal -PE = "L" is supplied to the gate of C1.
As described with reference to FIG. 4, a high voltage of about 17 V generated by the booster circuit 5 at the time of writing is applied to the word line WL. The output of the NOT circuit LB1 is "H" (about 5V). The gate of the transistor LC1 is "L" (= -P
E) and the source becomes "H" like the output of the NOT circuit LB1, so it is turned off. When the transistor LC1 is off, the high potential of the word line WL1 is maintained. Since the drain of the memory cell is at “H”, when a high voltage is applied to the control gate to which the word line WL1 is connected, data writing is performed on the memory cell.

On the other hand, at the time of writing, when the NAND circuit LA1 becomes "H", the output of the NOT circuit LB1 becomes "L" (about 0V). Although the gate of the depletion type transistor LC1 is "L" (= -PE), the source thereof is "L" like the output of the NOT circuit LB1.
So turn it on. The transistor LC1 is turned off when the source is “H” when the gate is “L” and turned on when the source is “L”. When the transistor LC1 is turned on and the drain current flows, the potential of the word line WL1 becomes “L”. Word line W
When L1 is "L", writing is not performed in the memory cell to which the word line WL1 is connected.

In the above, the reading and writing of data have been described. Next, the data erasing of the memory cell will be described. FIG. 7 is a diagram for explaining the operation of the division number setting circuit 20 when erasing data. Figure 7
7A shows a state where the transistor Tr1 has not been written, and FIG. 7B shows a state where the transistor Tr1 has been written.

As shown in Table 2 in FIG. 7A, at the time of erasing, the signal -E = "H" and the signal M = "H" are set. The transistor Tr2 is turned on because the signal M supplied to the gate is "H". Transistor Tr
No. 1 is in a non-written state, and electrons are accumulated in the floating gate FG, so that it is turned on when the signal -B = "H" is supplied to the control gate CG. When the transistors Tr1 and Tr2 are both turned on, the signal -E =
Even if "H" is supplied, the node N1 becomes "L".

The node N2 has the same level as the inverted signal -A4 of the input address signal A4, and is "L" or "H".
Take one of the levels. The nodes N1 and N2 are connected to the input terminals of the NOR circuit 21. Node N
1 is fixed to "L", and the node N2 is a node whose level can change. The node N3 is an output terminal of the NOR circuit 21 and has a level opposite to that of the node N2.

The node N3 is connected to the input terminal of the NOT circuit 22. The node N4, which is the output terminal of the NOT circuit 22, has a level opposite to that of the node N3. That is, the node N4 takes the same level as the node N2.

The above level changes are shown together. The nodes N3 and N4 take the following levels according to the level of the node N2 (signal-A4). However, the node N1
It is fixed at "L".

[0081]

[Table 5]

In FIG. 7B, when erasing is performed,
Similar to (A), the signal −E = “H” and the signal M = “H” are set. The transistor Tr2 is turned on because the signal M supplied to the gate is "H". Transistor T
Since r1 is in a written state and electrons are accumulated in the floating gate FG, it is off even when the signal −B = “H” is supplied to the control gate CG. When the transistor Tr1 is off, the node N1 receives the signal −
It becomes "H" like E.

The node N2 has the same level as the inverted signal -A4 of the input address signal A4, and is "L" or "H".
Take one of the levels. The nodes N1 and N2 are connected to the input terminals of the NOR circuit 21. Node N
Reference numeral 3 is an output terminal of the NOR circuit 21, and since the node N1 is fixed to "H", it becomes "L" regardless of the level of the node N2. Since the node N3 of the node N4 which is the output terminal of the NOT circuit 22 is "L",
It is fixed at "H".

The above level changes are shown together. The nodes N3 and N4 take the following levels according to the level of the node N2 (signal-A4). However, the node N1
It is fixed at "H".

[0085]

[Table 6]

The above is the division number setting circuit 2 at the time of erasing.
The configuration of 0 has been described. Next, in the row decoder 2 of FIG. 5, description will be given at the time of erase. When erasing, the transistor T
Depending on whether r1 is in the unwritten state or the written state,
The behavior is different.

When the transistor Tr1 is in the unwritten state, as shown in Table 5, the node N2 and the node N4 are always at the same level as in the reading and writing. The transistor Trb4 has a gate signal −
Since PE is "L" (Table 2), it is turned off. Node N
When 4 and the node N2 are at the same level, the following relationships are established as in the reading and writing.

-A4 '=-A4 When all of the eight transistors Tr1 corresponding to the eight division number setting circuits 20 are in the unwritten state, the following relations hold and the input address signals A4 to A7 are satisfied.
Only one of the NAND circuits LA1 to LA16 becomes "L", and the erase unit becomes 16.

A4 '= A4-A4' =-A4 A5 '= A5-A5' =-A5 A6 '= A6-A6' =-A6 A7 '= A7-A7' =-A7

On the other hand, when the transistor Tr1 is in the writing state, as shown in Table 6, the node N4 is always "H" regardless of the level of the node N2. Since the gate signal -PE is "L" (Table 2), the transistor Trb4 is turned off, and the signal line -A4 and the signal line -A are turned on.
4'is cut off. Since the node N4 is always "H", the signal line -A4 'becomes "H" regardless of the level of the signal line -A4. -A4 '= "H"

When only the two transistors Tr1 corresponding to the signal lines A4, -A4 are put in the write state, as shown in Table 3, the following relationship holds and the erase unit becomes eight.

A4 '= "H" -A4' = "H" A5 '= A5-A5' =-A5 A6 '= A6-A6' =-A6 A7 '= A7-A7' =-A7

Next, referring to FIG. 5, a description will be given of data erasing. At the time of erasing, for example, the NAND circuit LA1
When only one outputs "L", the NOT circuit LB1 outputs "H". At the time of erasing, as shown in Table 2, the signal -PE is set to "L". Transistor LC1
Is turned off because the gate is supplied with the signal -PE = "L" and the source is supplied with "H" from the NOT circuit LB1. At the time of erasing, a high voltage of about 17 V generated by the booster circuit 5 (FIG. 4) is applied to the word line WL. Since the transistor LC1 is off, the word line WL
A high potential of 1 is maintained. Since the drain of the memory cell is at "L", when the high voltage is applied to the control gate to which the word line WL1 is connected, the data in the memory cell is erased.

On the other hand, when the NAND circuit LA1 becomes "H", the output of the NOT circuit LB1 becomes "L" (about 0).
V). The transistor LC1 has a signal -P at its gate.
E = “L” is supplied, but NOT circuit LB1 is used as the source
Since "L" is supplied from, it turns on. When the transistor LC1 is turned on, a drain current flows and the potential of the word line WL1 becomes "L". Word line WL
When 1 is "L", data erase of the memory cell to which the word line WL1 is connected is not performed.

As described above, the eight transistors Tr1
The size of the erasing unit can be changed by setting the write state to the unwritten state. However,
Even if the size of the erase unit is changed, the size of the read unit and the write unit does not change. Since the size of the erasing unit can be freely set, when erasing a plurality of memory blocks at all times, it is not necessary to set the addresses of the plurality of memory blocks, and the erasing time can be shortened.

The case has been described above where the size of the erase unit is determined by fixing the lower arbitrary bits of the address signals A4 to A7 to a predetermined signal level regardless of the address signals A4 to A7.

Next, a row decoder capable of determining the size of the erase unit by designating the number of memory blocks included in the erase unit will be described. FIG. 8 is a circuit diagram showing a row decoder capable of externally specifying the number of memory blocks included in an erase unit.

The row decoder 2'includes address signals A4 to A4.
In addition to 7 and the control signal CTL, the number NN of memory blocks forming the erase unit is externally received and input to the block number setting circuit 25.

The block number setting circuit 25 controls the control signal CT.
When L indicates reading or writing, the signals A4 to A7 are directly changed to the signals A4 'to A as in the previous embodiment.
7 ', and an inverted signal of the signals A4 to A7.
Output as A4 'to -A7'.

When the control signal CTL indicates data erasing, the signals A4 'to A7' and -A4 'to -A7' are generated based on the signals A4 to A7 according to the block number NN. When the number of blocks NN is 1, the signals A4 'to A7' are read in the same manner as in the above reading or writing.
And -A4 'to -A7' are generated. Number of blocks NN is 2
, The signals A4 'and -A4' are fixed at "H".

Similarly, when the number of blocks NN is 4, 8 and 16, the signals A4 'to A5' and -A4 ', respectively.
~ -A5 ', signals A4'-A6' and -A4 '-A
6 ', the signals A4' to A7 'and -A4' to -A7 'are fixed at "H".

The signals A4'-A7 'generated as described above
And -A4 'to -A7' are NAND as in the previous embodiment.
Circuits LA1 to LA16, NOT circuits LB1 to LB16,
The word signal W is transmitted through the transistors LC1 to LC16.
Converted to L1 to WL16.

Only one of the word signals WL1 to WL16 is selected at the time of reading and writing. During data erasing, the number of blocks NN is simultaneously selected, and NN memory blocks are specified as one erasing unit. The user can freely set the size of the erase unit by externally designating the number NN of memory blocks constituting the erase unit.

Although the case where the size of the erasing unit is changed has been described above, the reading unit or the writing unit can be changed in the same manner as changing the size of the erasing unit. Further, not only the row decoder but also the column decoder can be used.

The read unit, write unit and erase unit do not have to have the same size. For example, the erase unit may be eight times as large as the write unit.

The present invention has been described above with reference to the embodiments.
The present invention is not limited to these. For example, it will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.

[0107]

As described above, according to the present invention,
Since the selection signal lines can be selected in a predetermined combination, for example, when erasing data, it is possible to specify a plurality of memory blocks at the same time by designating an address signal once. Can be shortened.

[Brief description of drawings]

FIG. 1 is a conceptual diagram showing an erase unit of a nonvolatile memory according to an embodiment. FIG. 1 (A) divides the entire memory area into 16 parts, FIG. 1 (B) divides the entire memory area into 8 parts, and FIG. 1 (C) divides the entire memory area into 4 parts, and erases data in units of each divided area It is a figure which shows the non-volatile memory which performs.

FIG. 2 is a schematic diagram showing a configuration of a nonvolatile memory according to the present embodiment.

FIG. 3 is a conceptual diagram showing an erase unit of the nonvolatile memory according to the present embodiment.

FIG. 4 is a block diagram showing the overall configuration of a nonvolatile memory according to this embodiment.

5 is a circuit diagram showing a configuration of a row decoder shown in FIG.

FIG. 6 is a diagram for explaining an operation of a division number setting circuit at the time of reading and writing.

FIG. 7 is a diagram for explaining the operation of the division number setting circuit when erasing data. FIG. 7A shows the transistor Tr1.
Shows the unwritten state, and FIG. 7B shows the written state of the transistor Tr1.

FIG. 8 is a circuit diagram showing a row decoder capable of externally specifying the number of memory blocks included in an erase unit.

[Explanation of symbols]

 1 memory cell array 2, 2'row decoder 3 column decoder 4 address buffer 5 booster circuit 6 write / erase control circuit 7 sense amplifier circuit 8 control gate booster circuit 11, 12 MOS transistor 13 memory cell 20 division number setting circuit 21 NOR circuit 22 NOT circuit 23 Control signal generation circuit 25 Block number setting circuit Tr1 EEPROM Tr2 MOS transistor LA NAND circuit LB NOT circuit LC depletion type MOS transistor LD NOT circuit BA memory block WL word line BL bit line

Claims (6)

[Claims] 1. An address signal (A4) supplied from the outside.
To A7) is a non-volatile memory that generates selection signals (WL1 to WL16) for selecting a memory cell based on A7), and changes and sets a combination of selection signals generated based on an address signal and stores the combination. And a selection signal generating means for generating a selection signal in a combination according to the setting of the combination setting means based on an address signal. 2. The non-volatile memory according to claim 1, wherein the selection signal generating means generates a selection signal using a NAND circuit which receives a combination of an address signal and an inverted signal of the address signal as an input. 3. The combination setting means is means for setting and storing a combination of selection signals when erasing data in a memory cell, and the selection signal generating means is fixed when reading and writing data in the memory cell. 3. The non-volatile memory according to claim 1, wherein the selection signals of the selected combination are generated, and when the data of the memory cell is erased, the selection signal is generated by the combination according to the setting of the combination setting means. 4. An address signal (A4) supplied from the outside.
To A7) is a non-volatile memory that generates selection signals (WL1 to WL16) for selecting a memory cell on the selection signal line based on the number of selection signal lines selected simultaneously among the selection signal lines ( Non-volatile memory having selection number setting means capable of changing and setting NN) and selection signal generating means for generating selection signals for simultaneously selecting a number corresponding to the setting of the selection signal setting means based on an address signal. . 5. The selection number setting means is means for setting the simultaneous selection number of selection signal lines when erasing data in a memory cell, and the selection signal generating means is for reading and writing data in the memory cell. Sometimes, a selection signal for simultaneously selecting a certain number of selection signal lines is generated, and at the time of erasing data in a memory cell, a selection signal for simultaneously selecting a number of selection signal lines according to the setting of the selection number setting means is generated. Item 4. The non-volatile memory according to item 4. 6. An address signal (A4) supplied from the outside.
To A7), a memory cell selection method for generating a selection signal (WL1 to WL16) for selecting a memory cell on a selection signal line, which is based on an address signal at the time of data reading and writing of the memory cell. A method of selecting a memory cell for a non-volatile memory, comprising the step of selecting a fixed number of selection signal lines and selecting a variable number of selection signal lines when erasing data in the memory cells.