JPH08223173A - Back pressure type atm switch - Google Patents

Abstract

PURPOSE: To improve traffic characteristics and to accelerate the switching of cells. CONSTITUTION: The transfer held state of the cell based on buffer full signals from an output buffer is monitored. A held cell abandoning part (a counter 54, a counter value comparator circuit 55 and a memory control circuit 52) for abandoning the cells of which transfer is held when the transfer held state matches with prescribed conditions is provided in an input buffer 11. Then, the input buffer 11 provided with the held cell abandoning part transfers the resective cells stored after the held cells to the corresponding output buffer after abandoning the held cells.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a back pressure type ATM (Asynchronous Transfer).
Mode; asynchronous transfer mode) switch,
The present invention relates to a back pressure type ATM switch that enables fast cell exchange with low cell loss.

[0002]

2. Description of the Related Art Among ATM switches, there is a back pressure type ATM switch for the purpose of efficiently using an input buffer and an output buffer. In this back pressure type ATM switch, when a predetermined number of cells transferred from the input buffer are accumulated in the output buffer,
A "back pressure signal (buffer full signal)" can be sent from the output buffer to the input buffer to stop (hold) the transfer of cells from the input buffer.

Regarding such a back-pressure type ATM switch, for example, "Technical Research Report Exchange System of Institute of Electronics, Information and Communication Engineers" (SSE) dated April 1994.
94-4) "Performance evaluation of ATM LAN switch with back pressure function" by Osaki et al., And by Mr. Fan in "Technical Research Report Exchange System of the Institute of Electronics, Information and Communication Engineers" (SSE93-6) dated June 1993. ATM switch capable of expanding buffer capacity: XATOM "and the like. The back pressure type ATM switch will be described below.

FIG. 7 shows a conventional back pressure type ATM.
It is a block diagram which shows the structural example of a switch. In FIG. 7, 101 to 104 are input lines, 201 to 204 are output lines, 11b to 14b are input buffers for the respective input lines 101 to 104, and 21 to 24 are output lines 201 to 20.
Output buffer for each 4 and 30 are input buffers 11b to 14
b and the output buffers 21 to 24, a self-routing switch (denoted as SW in the figure) 110 to 140
Is a signal line connecting the input buffers 11b to 14b and the self-routing switch 30. Reference numerals 210 to 240 are output buffers 21 to 24 and the self-routing switch 30.
Signal lines 21-1 to 24-4 connecting with and are signal lines for returning a back pressure signal (buffer full signal) from the output buffers 21 to 24 to the input buffers 11b to 14b.

The input buffers 11b to 14b have a function of stopping (holding) the cell transfer to the output buffers 21 to 24 which are sending out the buffer full signal. The cell written in the memory in the input buffers 11b to 14b at the earliest time is called the leading cell. The head cell maintains the head until it is transferred to the desired destination, and the FIFO (First
When performing In First Out control,
The cells written after the head cell are not output until the head cell is output.

FIG. 8 is an explanatory diagram showing an example of traffic characteristics of the back pressure type ATM switch shown in FIG. In this figure, the horizontal axis is the output buffer size, and the vertical axis is the buffer size required to satisfy the desired cell loss probability CLP (10 ⁻⁵ , 10 ⁻⁶ ). The buffer size is the input buffer size per line,
This is the sum of the output buffer size per line. Black circles in the figure are characteristics when back pressure is not used. From this figure, it can be seen that the adoption of the back pressure algorithm deteriorates the traffic characteristics. This is so-called HOL (Head of Line) blocking, in which each cell written in the memory in the input buffer after the second is blocked even when the cell can be output to the desired destination because the first cell is not output. caused by.

In addition, the input buffer is not a FIFO control but a RIRO (Random InRandom Ou).
When t) control is adopted, in the RIRO operation, a cell aiming at an output buffer that is not buffer full is searched from the memory and output. Therefore, it is possible to suppress deterioration of cell loss characteristics due to HOL blocking. However, in general,
The adoption of such a search algorithm increases the hardware scale and limits the cell read speed. As described above, in the conventional ATM switch adopting the back pressure, the FIFO control deteriorates the traffic characteristics due to the HOL blocking, and the RIRO control limits the cell read speed from the input buffer and retrieves the read cell. There will be an increase in the hardware scale for doing so.

[0008]

The problem to be solved is that the conventional technique cannot avoid HOL blocking in the FIFO control. The purpose of the present invention is to
It is an object of the present invention to provide a back pressure type ATM switch that solves the problems of the conventional techniques, has excellent traffic characteristics with simple control, and enables high-speed cell switching.

[0009]

In order to achieve the above object, the back pressure type ATM switch of the present invention comprises:
(1) A reserved cell discard unit that monitors the transfer pending state of a cell based on the buffer full signal from the output buffer and discards the cell that has been transfer pending when this transfer pending state matches a predetermined condition. The input buffer provided in the input buffer and provided with the reserved cell discarding unit is characterized in that after discarding the reserved cell, each cell accumulated after the reserved cell is transferred to the corresponding output buffer. Also,
(2) In the back-pressure type ATM switch according to (1) above, the reserved cell discard unit counts the cell transfer suspension time based on the buffer full signal from the output buffer of the cell output destination, and the counter 54. The counter value comparison circuit 55 that compares the count value of the counter 54 with a preset threshold value, and the comparison result of the counter value comparison circuit 5 show that the count value of the counter 54 exceeds the preset threshold value. In this case, at least the memory control circuit 52 for discarding the reserved cell is provided. (3) In the backpressure type ATM switch according to (1) above, the reserved cell discard unit includes the maximum number (Q) of cells that can be stored in the input buffer and the number of cells that are currently stored in the input buffer (Q). a threshold value generating circuit 57 for obtaining a difference (Q-q) with respect to q, and when the difference (Q-q) becomes smaller than a preset threshold value (k) (Q
-Q <k) has at least a memory control circuit 52a for discarding reserved cells.

[0010]

In the present invention, in the input buffer, for example,
The hold time of the first cell that has held (stopped) the transfer based on the buffer full signal from the output buffer is monitored, and when this held time exceeds a preset time (threshold), this first cell is discarded. To do. Alternatively, the number of cells being accumulated in the input buffer is monitored, and when the number of accumulated cells increases to a predetermined number, the leading cell that causes accumulation (transfer suspension) is discarded. In this way, by discarding the first cell of the transfer hold target, the transfer of the second accumulated cell can be started, and the HOL blocking can be avoided. As a result, deterioration of traffic characteristics due to HOL blocking in the back pressure type ATM can be prevented.

[0011]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a back pressure type ATM of the present invention.
FIG. 2 is a block diagram showing a first embodiment of a configuration of an input buffer according to the present invention provided in a switch, and FIG. 2 is a back pressure type ATM switch of the present invention including the input buffer in FIG. 1 according to the present invention. It is a block diagram which shows the 1st Example of a structure. Hereinafter, in this example, a 4 × 4 switch will be described.

In FIG. 2, 101 to 104 are input lines, 201 to 204 are output lines, 11 to 14 are input buffers, 21 to 24 are output buffers, and 30 is a self-routing switch for connecting the input buffer and the output buffer ( (In the figure, referred to as SW) 110 to 140 are signal lines connecting the input buffers 11 to 14 and the self-routing switch 30, and 210 to 240 are output buffers 21 to 2.
4 and the self-routing switch 30. Signal lines 21-1 to 24-4 are signal lines for returning a back pressure signal from the output buffers 21 to 24 to the input buffers 11 to 14, and 300 is an input buffer 11 to 11. 14, signal lines 601 to 604 are input to the input buffer 11.
14 to 14, signal lines 701 to 704 are input to the output buffers 21 to 24.

Each of the output buffers 21 to 24 receives all the input buffers 11 to 11 when, for example, the number of accumulated cells increases beyond a value (threshold value) set from each of the signal lines 701 to 704.
The buffer full signal toward the signal line 14 is transmitted to the signal lines 21-1 to 21-2.
Transfer via 4-4. Each of the input buffers 11 to 14 has a function of stopping the cell transfer to the output buffers 21 to 24 which are sending out the buffer full.

FIG. 3 is a block diagram showing a configuration example of the self-routing switch in FIG. In FIG. 3, cells input through the signal lines 110 to 140 are routed based on the addresses set at the respective cross points and output to the signal lines 210 to 240 which are the desired destinations. Hereinafter, the input buffers 11 to 1 according to the present invention
4 will be described with reference to FIGS. 1 and 4.

In FIG. 1, 101 is an input line and 110
Is a signal line that connects the output of the input buffer 11 and the self-routing switch 30, 300 is a signal line to which a cell read clock is input, 601 is a signal line to which the threshold value according to the present invention is input, and 51 is a signal line. A memory for temporarily accumulating cells input from 101, a memory control circuit 52 for writing and reading address control of cells, an address comparison circuit 53, a counter 54 according to the present invention, and 55 a present invention. Counter value comparison circuit according to
56-1 and 56-2 are delay circuits, and 611 and 61.
2 is a signal line connecting the memory 51 and the memory control circuit 52, and 613 is a memory control circuit 52 and the address comparison circuit 5.
2, signal lines 21-1 to 24-1 connected to the output buffers 21 to 24 in FIG.
4 is a signal line connecting the address comparison circuit 53 and the counter 54, and 615 is a counter 54 and the counter value comparison circuit 5.
5 is a signal line for connecting with 5, and 618 is a counter value comparison circuit 5
5 is a signal line connecting the memory control circuit 52 to each other, 616 is a signal line connecting the delay circuit 56-2 to the counter 51,
A signal line 617 connects the delay circuit 56-1 and the counter value comparison circuit 55.

The counter 54 and the counter value comparison circuit 5
5 and the memory control circuit 52 constitute a reserved cell discard unit according to the present invention. The operation of the input buffer having such a structure according to the present invention will be described below with reference to FIG. FIG. 4 is a flowchart showing an operation example of the input buffer in FIG. 1 according to the present invention. This input buffer is premised on a FIFO operation. That is, the cells are read from the memory according to the order of the cells written to the memory. Hereinafter, the cell written in the memory at the earliest time is called the leading cell.

First, when a cell read clock is input through the signal line 300 in FIG. 1 (step 40)
1), the address comparison circuit 53 of FIG. 1 determines whether the output destination of the leading cell is buffer full (step 40).
2). Here, the cell read clock is input, for example, in a unit of time required for reading one cell (cell read cycle). The output destination of the leading cell is input from the memory control circuit 52 to the address comparison circuit 53 through the signal line 613 in FIG. Furthermore, all output buffer states are shown in FIG.
Is input to the address comparison circuit 53 from the outside through.

Output destination of the start address (output buffer)
Generates a back pressure (BP) signal (step 403), the reading of the first cell is postponed until the reading cycle of the next cell, and the count value of the counter 54 of FIG. 1 is incremented by “1” (step). 40
4). This count value is transferred to the counter value comparison circuit 55 through the signal line 615 in FIG. This count value means a holding time from the time when the head cell reaches the head. The count value may be incremented even if the head cell cannot be output to the desired output line due to collision.

In FIG. 1, the counter value comparison circuit 55 is
The count value from the counter 54 is compared with the threshold value input through the signal line 601 (step 40).
5). If the count value exceeds the threshold value, the counter value comparison circuit 55 in FIG.
The data is transferred to the memory control circuit 52 through the signal line 618, and the memory control circuit 52 discards the head cell (step 4).
06). As a result, the cell written second in the memory 51 in FIG. 1 becomes the head cell. Similarly, (n +
The 1) th cell is shifted to the nth. At the time of discarding the first cell, the memory control circuit 52 in FIG. 1 resets the counter 54 via the signal line 630 and sets the count value output from the counter 54 to the signal line 615 to zero (0) (step 407). ).

On the other hand, if the back pressure signal is not input in step 402 or if the output destination of the leading cell is not buffer full in step 403, the address comparison circuit 53 in FIG. 1 sends the permission signal through the signal line 631. It returns to the memory control circuit 52, and the memory control circuit 52 transfers the read signal to the memory 51 through the signal line 612 and sends the head cell through the signal line 110 (step 408). After reading the first cell in this manner or outputting to the desired output line, the memory control circuit 52 in FIG.
Resets the count value of the counter 54 to zero through the signal line 630 (step 409). By the above operation, the maximum holding time from the time when the head of the head cell is reached is limited. The threshold value input through the signal line 601 in FIG. 1 may be, for example, “switch scale + k” (k: natural number). FIG. 5 shows an example of traffic characteristics obtained from the result of this operation.

FIG. 5 is an explanatory view showing an example of traffic characteristics of the back pressure type ATM switch shown in FIG. The traffic characteristic example shown in FIG. 5 is a result obtained by simulation. The horizontal axis represents the output buffer, and the vertical axis represents the required cell loss probability CLP (10 ⁻⁵ , 10 ⁻⁶ ) in order to satisfy the requirement. Buffer size. The buffer size is the sum of the input buffer size per line and the output buffer size per line.

When the output buffer is completely full,
This output buffer transfers the buffer full signal to all input buffers. In FIG. 5, the broken line shows the traffic characteristics of the conventional example, and the solid line shows the characteristics of the present embodiment when the maximum holding time is 16 cell hours. In this example, the maximum holding time is the total of the time when the output of the desired output buffer is stopped by the back pressure signal and the time when the desired output line cannot be reached due to collision. Also, the black circles in FIG.
This is the characteristic when back pressure is not used. As described above, the first embodiment having the configuration shown in FIG. 1 has excellent characteristics as compared with the conventional switch using the back pressure, and has the same characteristics as the switch not using the back pressure. It has excellent characteristics.

Next, a second embodiment of the present invention will be described. FIG. 6 is a block diagram showing a second embodiment of the configuration of the input buffer according to the present invention provided in the back pressure type ATM switch of the present invention. In FIG. 6, 101 is an input line, 110 is a signal line for connecting the output of the input buffer 11a and the self-routing switch 30, and 300
Is a signal line for inputting a cell read clock, 51 is a memory for temporarily accumulating cells input from the signal line 101, 52a is a memory control circuit for performing address control of writing and reading of cells, and 53 is an address comparison circuit. , 57 is a threshold value generation circuit according to the present invention, 611 and 612 are signal lines connecting the memory 51 and the memory control circuit 52a, 613 is a signal line connecting the memory control circuit 52a and the address comparison circuit 53, 21 -1 to 24-4 are signal lines connected to the output buffers 21 to 24, 618 and 619 are signal lines connecting the memory control circuit 52a and the threshold value generation circuit 57, and 617 is a threshold value generation circuit 5.
7 is a signal line input from the outside.

In the second embodiment, the threshold generation circuit 5
7 and the memory control circuit 52a constitute a reserved cell discard unit according to the present invention, and the "threshold value of the leading cell discard" given from the outside in the first embodiment in FIG.
Based on the value input from the signal line 617, the input buffer 1
It is generated inside 1a. The memory control circuit 52a sends the current cell storage amount (q) to the threshold value generation circuit 57.
Transfer through the signal line 619. Threshold generation circuit 57
Generates a head cell discard signal based on the cell accumulation amount (q) and the value (k) input through the signal line 617, and outputs the signal to the signal line 618. When the head cell discard signal is input, the memory control circuit 52a discards the head cell and (n +
1) Shift the nth cell. As the leading cell discard algorithm, when the maximum number of storable cells (Q) in the memory 51, the current number of stored cells (q), and the value (k) set from the signal line 617 are used, "Q- q
When <k ”is satisfied, the first cell is discarded.

As described above with reference to FIGS. 1 to 6, in the back pressure type ATM switch of this embodiment, in the input buffer, for example, the transfer is suspended (stopped) based on the buffer full signal from the output buffer. The holding state of the leading cell, for example, the holding time and the number of accumulated cells due to the holding are monitored, and when the holding time or the number of accumulated cells exceeds a preset threshold value, the leading cell is discarded. In this way, by discarding the first cell that has caused the transfer suspension, the transfer of the second accumulated cell can be started, and the input buffer can be transferred to the FIF.
It is possible to avoid the HOL blocking that has conventionally occurred when the O type is adopted.

As a result, deterioration of traffic characteristics due to HOL blocking in the back pressure type ATM can be prevented, excellent traffic characteristics can be obtained by simple control, and high-speed cell switching becomes possible. The present invention is not limited to the embodiments described with reference to FIGS. 1 to 6, and various modifications can be made without departing from the scope of the invention.

[0027]

According to the present invention, the back pressure type A
In the TM switch, the HOL blocking that has conventionally occurred due to the FIFO control input buffer can be avoided by simple control, the traffic characteristics can be improved, and the cell switching speed can be increased.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the configuration of an input buffer according to the present invention provided in a back pressure type ATM switch according to the present invention.

2 is a block diagram showing a first embodiment of the configuration of the backpressure type ATM switch of the present invention including the input buffer shown in FIG. 1 according to the present invention.

FIG. 3 is a block diagram showing a configuration example of a self-routing switch in FIG.

4 is a flowchart showing an example of operation of the input buffer in FIG. 1 according to the present invention.

5 is an explanatory diagram showing an example of traffic characteristics of the back pressure type ATM switch in FIG.

FIG. 6 is a block diagram showing a second embodiment of the configuration of the input buffer according to the present invention provided in the back pressure type ATM switch of the present invention.

FIG. 7 is a block diagram showing a configuration example of a conventional back pressure type ATM switch.

8 is an explanatory diagram showing an example of traffic characteristics of the back pressure type ATM switch in FIG.

[Explanation of symbols]

11-14, 11a, 11b-14b: input buffer,
21-24: output buffer, 30: self-routing switch, 51: memory, 52, 52a: memory control circuit, 53: address comparison circuit, 54: counter, 55:
Counter value comparison circuits, 56-1, 56-2: delay circuits,
57: threshold value generation circuit, 101-104: input line,
110 to 140: signal lines, 201 to 204: output lines,
210-240: signal line, 21-1-24-4: signal line, 300: signal line, 601-604, 611-61
8, 630, 631: signal line, 701 to 704: signal line

Claims (3)

[Claims] 1. According to the order of cells written and accumulated in an input buffer from an input line, the cells are switching-transferred to a corresponding output buffer and output to an output line, and at the same time, from the output buffer to the input buffer. A back pressure type ATM switch for sending a buffer full signal to suspend transfer of a cell from the input buffer to the output cell, wherein the input buffer receives the buffer full signal from the output buffer. The transfer hold state is monitored, and when the transfer hold state matches a predetermined condition, a hold cell discarding unit for discarding the transfer hold cell is provided, and the input including the hold cell discarding unit is provided. The buffer, after discarding the reserved cell, stores each cell accumulated after the reserved cell according to the accumulation order,
A back pressure type ATM switch which transfers to the corresponding output buffer. 2. The back pressure type A according to claim 1, wherein (subordinate claim = detailed configuration of reserved cell discarding means (1)).
In the TM switch, the holding cell discarding means counts a cell transfer holding time based on a buffer full signal from an output buffer of an output destination of the cell, a count value of the counter means, and a preset value. If the count value of the counter means exceeds the preset threshold value as a result of comparison by the counter value comparing means for comparing the threshold value with the threshold value, the reserved cell is discarded. A back pressure type ATM switch comprising at least a memory control means. 3. The back pressure type A according to claim 1, wherein (subordinate claim = detailed configuration of reserved cell discarding means (2)).
In the TM switch, the reserved cell discarding means is a difference (Q-) between the maximum number (Q) of cells that can be stored in the input buffer and the number (q) of cells that are being stored in the input buffer.
q) and the difference (Q-q) becomes smaller than a preset threshold value (k) (Q-q <k)
And at least a memory control means for discarding the reserved cell.
TM switch.