JPH08191284A - Method and device for atm/stm conversion in - Google Patents

Abstract

PURPOSE: To realize a system which shortens the phase adjustment time required at the time of reconstituting an inputted ATM cell into an STM signal. CONSTITUTION: Only a VC is extracted from an AU or TU signal in an inputted reception ATM signal and is written in a delay fluctuation absorbing buffer 4. At this time, the start byte of the VC is found by an AU pointer or the TU signal, and a flag 14 is set to this byte. At the time of constituting an STM frame 3, the flag 14 is used to generate a new AU pointer or TU pointer, and it is inserted into an AU pointer or TU pointer area in the STM frame. Consequently, the phase adjustment time is shortened in comparison with output of the inputted AU or TU pointer itself because only the VC of the AU or TU signal is written in the delay fluctuation absorbing buffer 4 and the new AU or TU pointer adapted to the STM frame to be outputted is generated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ATM / STM conversion method and apparatus, more specifically, an asynchronous transfer mode (asynchronous transfer mode "Asynchronous transfer mode").
TransferMode "(hereinafter abbreviated as" ATM ") An ATM signal that arrives via a network is transferred in a synchronous transfer mode (synchronous transfer module" Synchronous Transport Module ").
The present invention relates to a method and apparatus for converting an STM signal suitable for a network.

[0002]

2. Description of the Related Art STM networks and ATM networks have been internationally studied and standardized as effective transmission networks for high-speed digital signals. It is said that the ATM network will be the major one in the future, but it is also considered to form a communication network combining the STM network and the ATM network in order to make the best use of the features of each network or to share it with existing equipment. (For example, the bibliography of the Institute of Electronics, Information and Communication Engineers BI Vol. J76-B.
-I No. 2 pp. 150-161, 1993
February). When forming a communication network in which the STM network and the ATM network are combined, it is necessary to convert the transmission format in the nodes that form the connection unit. For example, as shown in FIG. 17, the STM signal is transmitted between the node 1 and the node 6 through the STM network between the nodes 2 and 3, the ATM network between the node 3 and the node 4, and the STM network between the node 4 and the node 5. Is transmitted in the direction of the arrow, the STM signal at node 3 is
A process of converting to a TM signal is required. Also, node 4
In, it is necessary to convert the ATM signal into the STM signal.

The STM signal is ITU-T Recommendation G707-7.
It is based on the STM-1 frame structure defined in 09. S
The TM-1 frame has 9 rows × 27 as shown in FIG.
It has a frame structure of 0 bytes, and 9 bytes of each of the 1st to 3rd lines on the left side and 9 bytes of each of the 4th to 9th lines are a section overhead (abbreviated as SOH) management information area, 9th of the 4th line on the left side. It has a frame phase information area called an AU pointer of bytes and an area mainly containing information called a virtual container (abbreviated as VC) of 9 rows × 261 bytes on the right side. STM-1 is Administrative Unit-3 (Administrative Uni
3 virtual containers-3 (abbreviated as "VC-3") are accommodated via t-3 "abbreviated as" AU-3 "). The VC-3 accommodates the VC-11 via a tributary unit-11 (abbreviated as "Tributary Unit-11" TU-11 "). VC-3
And VC-11 contain signals such as 44.736 Mbit / s and 1.544 Mbit / s information, respectively.
In addition, the AU-3 signal accommodates seven tributary unit groups-2 (abbreviated as "Tributary Unit Group-2" TUG-2 "). Also, TUG-2 is a Tributary Unit-11 (TU-2).
1), 4 TU-11 or TU-12
Accommodates three.

The AU-3 is composed of a VC-3 and an AU-3 pointer. The AU-3 pointer is set to H as shown in (b).
9 bytes of 1 # 1, H1 # 2, H1 # 3 ... H3 # 3 are interleaved, and H1 # 1, H2 # 1, and H3 # 1 are ST
The position of the first byte (abbreviated as J1) of VC-3 # 1 of the M-1 frame is set to H1 # 2, H2 # 2, H3 # 2.
Position of the J1 byte of VC-3 # 2, and H1 #
2, H2 # 2, H3 # 2 indicate the position of the J1 byte of VC-3 # 3. One vertical column on the right side of each VC-3 has a path overhead (abbreviated as POH), and one byte in the uppermost row is the J1 byte. At the fourth position from the top of the POH is a byte (abbreviated as H4) that indicates the position of the VC payload.

TU-11 is composed of a VC-11 and a TU-11 pointer, and TU-2 is composed of a VC-2 and a TU-11 pointer. Hereinafter, the TU-11 pointer and the TU-2 pointer will be collectively referred to simply as the TU pointer.
As shown in (c), the TU pointer has four frames (50
0 μs) defines 4 bytes from V1 to V4.
1 and V2 depending on V5, that is, VC-11 or VC-2
The position of the first byte of is indicated by the number of bytes, and is placed in the top line of the frame. The detailed structure of the STM signal is known in the above-mentioned ITU-T Recommendations G707 to 709, etc., and therefore detailed description thereof will be omitted, and more detailed specifications will be described below in a necessary range.

As shown in FIG. 19 (a), the ATM signal is a 53-byte ATM cell (hereinafter referred to as a cell header (5 bytes), a SAR-PDU header (1 byte) and a cell payload (47 bytes). (Also simply referred to as a cell). The cell header has a virtual path identifier (hereinafter abbreviated as VPI) indicating the destination of the cell. SA
The R-PDU header (1 byte) includes a sequence number (hereinafter abbreviated as SN) field (4 bits) shown in (b) of FIG. 19 and a sequence number protection (hereinafter abbreviated as SNP) shown in (c) of FIG. It consists of fields (4 bits). The SN field is a 3-bit SN used to verify continuity of cells of the same VPI,
It consists of 1 bit CSI bit indicating the presence or absence of a cell pointer. The SNP field includes a CRC field (3 bits) for detecting an error in the SN field and 1 bit for even parity. The first one in the cell payload
Bytes are assigned as cell pointer opportunities. The cell pointer has an even SN and C
The SI is inserted into the cell pointer opportunity of the cell with '1'. When accommodating the STM signal, the cell pointer is the AU within the cell from the byte next to the cell pointer.
Or, it indicates the number of bytes up to the boundary of the TU.

As shown in FIG. 20, the method of converting the AU-3 of the STM signal into the ATM signal is as follows.
0, 101 are divided, and ATM cells 102, 103 ... 10
It is known that the method of inserting into each payload of 5 is advantageous from various viewpoints such as economical efficiency and reliability. In this case, like the ATM cell 103, when the AU-3 signal 101 starts in the middle of the payload, the subsequent bytes are accommodated in the cells 104, 105 ... In order. Where AT
When the SN of the M cell 103 is even and the CSI is '1', the cell pointer opportunity CPO represents the number of bytes a from the next byte to the AU pointer, as shown in (a) of FIG. In addition, S of the ATM cell 103
When N is an odd number, as shown in FIG. 20B, the cell pointer opportunity of the immediately preceding cell 102 indicates the number of bytes (a + b) from the next byte to the AU pointer. Similarly, TU-11, TU-12, and TU-2 can be converted into ATM signals. AT the above STM signal
The technique relating to the technique of converting to an M signal is described in detail in the above-mentioned document.

However, as node 4 in FIG.
There is no known technique for receiving an ATM signal containing an M signal, converting it into an STM-1 signal, and transmitting it to an STM network.

[0009]

Here, as in the node 4 of FIG. 17, three AU-3 signals are sent from the ATM cell string passing through three different lines of the ATM network to the STM-1.
When converting to a signal, the cell pointer is detected from the received ATM cell, then only the STM signal is extracted and written in the buffer memory, and on the read side, the STM-1 signal type is read, that is, on the write side. ATM / ST that processes in cell units and processes in byte units on the read side
The M conversion method is generally considered.

However, in the above-mentioned ATM / STM conversion method, as shown in the upper part of FIG.
-3 signals containing three different ATM signals AU-3
When # 1, AU-3 # 2, and AU-3 # 3 are received at arbitrary times, the phases of the respective signals are not aligned, and therefore the phases need to be aligned. However, as shown as an output signal in the lower part of FIG. 21, a large amount of memory (2 in the STM-1 frame is required to align the phases of the AU-3 signals that arrive).
Take as much as necessary). Also, a delay for phase matching occurs in each AU-3. The same applies to other TU-X (X = 2, 11 or 12).

The main object of the present invention is to transfer ATM signals to STM.
An object of the present invention is to realize an ATM / STM conversion method and an ATM / STM conversion device that reduce the delay generated when converting to a signal and reduce the memory capacity for conversion.

[0012]

In order to achieve the above object, an ATM / STM conversion method according to the present invention comprises an AU-
3, TU-2, TU-12, or TU-11, the AU-3, TU-2, T
VC signal of U-12 or TU-11 and cell pointer of the ATM cell, AU-3, TU-2, TU-1
2 or TU-11 pointer is separated and extracted, the separated VC signal is mapped as a VC of a new STM-1 frame, and A of the new STM-1 frame is also extracted.
Generate a U pointer or TU pointer, and add the new ST
Map to M-1 frame. Further, if necessary, N (N is 4, 16) STM-1 frames obtained as described above are time-division multiplexed for each byte and ST
Convert to STM of MN frame.

Further, the ATM / STM converter according to the present invention can convert the STM signal from the ATM signal accommodating the STM signal into the STM signal.
A write controller for extracting the signal of the virtual container of the signal and writing it in the buffer memory, a read controller for reading out the signal of the virtual container from the buffer memory in byte units, and an AU used for the STM-N frame of the new STM signal. A pointer generating means for generating a pointer or a TU pointer and a means for mapping a byte unit signal read from the buffer memory and the AU pointer or TU pointer from the pointer generating means to the STM-N frame are configured. To do.

The write control unit means extracts the cell pointer in the STM signal contained in the ATM signal and the AU pointer or TU pointer in the STM signal by using the cell pointer. The second means for extracting and the AU pointer or the TU pointer extracted by the second means are decoded and the STM is extracted from the ATM signal.
A third means for extracting the signal of the virtual container of the signal, a fourth means for extracting the first byte of the virtual container, a signal of the virtual container, and a first byte of the virtual container, The read control means also has means for accumulating a signal indicating that the byte is the head of the virtual container, and the read control means generates a read address signal from the buffer memory and a timing signal for the read control means. It has a timing generator to add.

[0015]

According to the present invention, when the STM signal from the buffer memory is mapped to the STM-N (N is 1, 4 or 16) frame, the AU pointer or TU pointer used for the STM-N frame is newly calculated. STM-signals obtained from the ATM signal and having different phases are obtained.
Since it can be placed at any time position in N frames, it is possible to obtain S from ATM signals received from different lines in different phases.
When mapping to the TM-N frame, a large capacity memory for phase matching is not required, and the ATM / S
The delay time associated with TM conversion can be reduced.

[0016]

1 is a block diagram showing the configuration of an embodiment of an ATM / STM converter according to the present invention. In this embodiment, only the VC signal of the STM signal is extracted from the ATM cell (hereinafter simply referred to as cell) 1 accommodating the STM signal of the input highway and stored in the delay fluctuation absorption buffer memory (hereinafter simply referred to as absorption buffer) 4. Store. That is, the header (VPI or the like) of the cell 1, the cell pointer, the AU pointer, or the TU pointer is not written in the absorption buffer 4.
A new AU pointer or TU is provided on the output side of the absorption buffer 4.
The pointer is generated by calculation and is mapped to the converted STM signal 3 of the STM-1 frame together with the VC signal read from the absorption buffer 4.

In this embodiment, the separation circuit 0, the frame phase extraction unit 6, the write counter 7, the VPI identification unit 9, the absorption buffer 4, the absorption buffer write control unit 18, the cell discard / cell discard /
The misalignment detection unit 21, the absorption buffer read control unit 27, the small delay cell search unit 30, the read timing generation unit 31, and the selector 34 are included.

The configuration and signal processing of each block will be described below. (Separation Circuit) The separation circuit 0 separates the SN, SNP byte 5, the internal VP signal 8 and the SN signal 10 described in FIG. 20 from the cell 1. Cell 1 is AU-3 of the STM signal,
It accommodates either TU-2, TU-12 or TU-11. As described above, the AU-3 has an AU pointer composed of H1 byte, H2 byte, and H3 byte, and VC-
Consists of three. TU-2, TU-12 or TU-11 is V
1 to V4 TU pointer and VC-2, VC
-12 or VC-11.

(Absorption buffer) The absorption buffer 4 is the cell 1
From STM, only the VC signal of the STM signal is accumulated and written in byte units for each virtual path (VP). At that time, all A
When three U-3 are input, as shown in FIG.
Each of the areas AU # 1, AU # 2, and AU # 3 of each VP has an area for storing the number of cells (256 cells). The addresses of the absorption buffer 4 are the areas AU # 1 and AU.
Address 2 bits (b1 for identifying # 2 and AU # 3
6, b15), an 8-bit address for identifying the cell (b1
4 ... b7) and 6 bits (b6 ... b1) of an address for identifying the byte of one cell.

Similarly, when all TU-11s are input, as shown in FIG. 3, areas cell # 1, cell # 2, ... Cell # 8 in which eight cells are stored for each VP.
Have. Further, as shown in FIG. 4, the area for storing one cell is 64 bytes for storing a signal of VC, and one for each of a VC-head flag and a cell-end flag described later.
Has an area for storing bits. The number of VPs input is
It depends on the type of STM signal accommodated in the ATM cell. When all TU-11 are accommodated, the number of VP is 8
It becomes 4. If all AU-3s are housed,
The number of VPs is 3. That is, three AU-3s are multiplexed into one STM-1 frame, one AU-3 is multiplexed with seven TUG-2s, and one TUG-2 is multiplexed with four TU-11s.

(VPI Identification Unit) FIG. 5 shows the configuration of the VPI identification unit 9. The VPI in the cell header is converted to the internal VP 8 by the separation circuit 0. The VPI identifying unit 9 performs all the operations described below for each internal VP. Inside V of cell 1
Using P8 as an address, the structure information 9-3 (d9 to d3) from the cell structure memory 9-1 and the S stored in the cell 1 are stored.
TM signal type 9-4, (d2, d1), that is, A
The identification bits of U-3, TU-2, TU-12, and TU-11 are extracted. The structure information 9-3 (d9 to d3) is 2 bits (d9, d8) and belongs to the AU of the input cell (AU # 1, AU # 1,
AU # 2, AU # 3), and belonging TUGs (TUG # 1, TUG # 2 ... TUG #) with 3 bits of d7, d6, and d5.
7), and 2 bits of d4 and d3 belong to the TU (TU-
11 # 1, ... TU-11 # 4). Type 9-4 of 2
Bits (d2, d1) are STs accommodated in cell 1
If the M signal is AU-3, it is '00', and if it is TU-2,
In the case of "01" and TU-11, it is "10".

The STM identifier generator 9-2 generates the STM identifier 11 from the structure information 9-3 and the signal type 9-4. For example, the signal type 9-4 is '00' (AU-3)
If so, d9 and d8 of the structure information 9-3 are STM.
The identifier is 11. If the signal type 9-4 is “01”, d9 to d5 are STM identifiers 11. Signal type 9
If -4 is '10', all bits (d9 to d3) of the structure information 9-3 are used as the STM identifier 11. The STM identifier 11 is the address 17 of the write buffer memory 4.
Become part of. For example, in the case of AU-3, the STM identifiers d9 and d8 are used for the upper 2 bits (b16 and b15 in FIG. 2) of the write address 17. Also, TU-
In the case of 11, the d9 to d3 of the STM identifier 11 are the upper 7 bits of the write address 17 (b16 to b1 in FIG. 3).
0) is used.

(Frame Phase Extraction Unit) FIG. 6 is a time chart for explaining the processing of the frame phase extraction unit 6. The frame phase extraction unit 6 extracts the cell pointer from the SN and SNP bytes 5 of the cell 1 separated by the separation circuit 0,
The AU pointer or TU pointer is extracted from the cell pointer. The leading byte of each VC is extracted using the extracted AU pointer or TU pointer.

First, the signal accommodated in the cell 1 is AU.
The processing in the case of -3 will be described. The cell pointer is shown in FIG.
As described above, the SN is an even number and the CSI is inserted into the cell pointer opportunity CPO of the cell having a value of "1". The write pointer 18 is detected by detecting the cell pointer.
(AU in the write address information memory 18-1 of FIG.
It is added to the pointer area (c10 to c1 in FIG. 9). Figure 6
As shown in, the cell pointer counter is decremented for each 1-byte input, and the AU-3 pointer (H1, H
2, H3) is inserted (H3 is a negative justification opportunity). Furthermore, this AU-3 pointer counter is used in byte units like the cell pointer.
Count down. The byte input when this value becomes '0' is the first byte (J1) of the VC of AU-3.
Is. Then, at the same time as writing the first byte (J1) to the absorption buffer 4, the VC-head of the same address is written.
The flag 14 is inserted in the area. In this way, the VC portion is continuously written to the absorption buffer 4 up to the last byte of the cell.

FIG. 7 shows a frame phase extraction unit 6 when the signal accommodated in the ATM cell is TU-2 or TU-11.
7 is a time chart illustrating the processing of FIG. In the figure, numeral 108 is the number of bytes in the case of TU-2, and numeral 27 in parentheses is the number of bytes in the case of TU-11. The cell pointer is detected as in the case of AU-3. The cell pointer counter counts down, and the byte (V1) input when it reaches "0" and 10 bytes from that byte
Byte (V2) input after 8 bytes and 10 more
The byte (V3) input after 8 bytes is the TU-2 pointer (V3: negative justification opportunity). In the case of the TU-11 pointer, the byte when the cell pointer becomes "0" is V1, the byte 27 bytes after that byte is V2, and the byte 27 bytes later is V3. The extracted TU-2 (or TU-1
1) Using the pointer, VC as well as the AU-3 pointer
Of the first byte (V5) of the
The flag 14 is inserted in the C-head area.

In addition to the above operation, the frame phase extraction unit 6 detects the final byte (hereinafter cell-end) of each input cell necessary for generating a read address 23 described later. For this purpose, the write counter 7 is used to count the number of bytes from the beginning of each cell. Then, the 53rd byte of the cell is set as cell-end, and that byte is written to the absorption buffer 4, and at the same time, the flag 15 is inserted in the cell-end area of the same address. At this time, if the byte corresponding to cell-end is a VC signal as shown in FIG. 8, the cell-en of that byte is
The flag 15 is inserted in the d area. If the byte corresponding to cell-end is an AU / TU pointer, H1 (V
1) The flag 15 is inserted in the cell-end area of the byte immediately before the byte. When the justification (PJ) is performed on the byte corresponding to the cell-end and the signal is TU-2 or TU-11, the flag 1 is sent to the cell-end area of the previous byte.
Insert 5. If it is AU-3, it goes back to the byte immediately before H1 and the cell-en of that byte.
The flag 15 is inserted into the d area. Negative justification (NJ) to the byte corresponding to cell-end
, The byte is an AU pointer or T
Although it is a U pointer, the flag 15 is inserted in the cell-end area of the byte.

(Absorption Buffer Write Control Unit) FIG. 9 shows the configuration of the absorption buffer write control unit 18. The write control unit 18 uses the write address information memory 18-1 for converting the STM identifier 11 from the VPI identification unit 9 into write address information 18-3, the byte number bit 12 of the write counter 7 and the write address information 18-3. And a write address generation unit 18-2 that generates the write address signal 17.

First, the generation of the write address 17 when a cell accommodating the AU-3 signal is inputted is shown in FIG.
Will be explained. Address 16 bits (b16 ... b
In 1), the upper 2 bits'b16, b15 'have A
The STM identifier 11 for U-3 (d9, d8 in FIG. 5) is used. Value of upper 2 bits'b16, b15 'is'00'
If so, specify the AU # 1 area in the absorption buffer 4,
If it is "01", the AU # 2 area is designated, and if it is "10", the AU # 3 area is designated. Medium 8 bits'b1
The signals (c25 to c18 in FIG. 9) of the cell counter for the area designated by the upper 2 bits are used for 4 to b7 '.
This specifies to which area of the cell storage area (256 cells) in the AU area specified by the upper 2 bits'b16 and b15 ', and which is counted up when the lower 6 bits are reset. Lower 6 bits (b6 to b1)
For this, the byte number bit 12 (6 bits) of the write counter 7 is used. This counts the number of bytes in the payload portion in the reception cell, and resets to "0" when the last byte is counted.

Next, the generation of the write address 17 when a cell accommodating the TU-11 signal is input will be described with reference to FIG. Among the 16 bits of the address, the upper 7 bits (b16 to b10) have ST for TU-11.
The M identifier 11 (d9 to d3 in FIG. 5) is used. The upper 2 bits of the upper 7 bits (b16 to b10) are "0".
If it is 0 ', the AU # 1 area is designated, if it is'01', the AU # 2 area is designated, and if it is' 10 ', the AU # area is designated.
Specify 3 areas. Next 3 bits (b14 to b12)
Specifies the TUG area in each AU area. The remaining 2 bits (b11, 10) are used for T in each TUG area.
Specify U-11. The middle 3 bits (b9 to b7) include the lower 3 bits of the cell counter (c20, c1 in FIG. 9).
9, c18) is used. This is due to the upper 7 bits
Indicate which cell area in the specified TU-11 storage area (8 cells) to write, and the lower 6 bits (b6 to b)
Counts up at reset in 1). The byte number bit 12 (6 bits) of the write counter 7 is used for the lower 6 bits (b6 to b1). This is similar to the case of AU-3, counting the number of bytes of the payload part in the reception cell and counting the last byte,
Reset to '0'. As described above, the write address 17 of the absorption buffer 4 is generated.

(Cell discard / mis-delivery detection unit 20) Cell discard /
The misdelivery detection unit 20 detects cell discard and cell misdelivery caused by a header error or congestion in the ATM network. For this detection, a method of comparing the SN of the cell with the expected value (SCR) of the SN and verifying the continuity of the SN is used. This method detects continuous discarding of 6 cells or less and misdelivery of 1 cell alone.
In this method, first, only the SN of the receiving cell 1 is accumulated, and the VC inside the cell is written in the absorption buffer 4. Then, the accumulated SN is verified by the following method.

FIG. 10 shows an algorithm for detecting cell discard and misdelivery. First, the expected value SCR is compared with the SN (current SN) of the arrived cell. When these two values are equal, it is determined to be normal (steps 2 and 3). When the two values are different, it is determined to be on hold (step 4), and discard or misdelivery is detected in step 5. In step 5, the SN one cell before
If the SNs are currently continuous, it is determined that cell discard has occurred. Then, the number of discarded cells is calculated ((8 + SN-SC
R) ₈ cells), the discard occurrence signal 19 and the discard cell number are output to the write control unit 18. In step 5, the current S
If N = SCR + 7 is established, it is determined that the cell is erroneously distributed, and the erroneous distribution occurrence signal 20 is output to the write control unit 18.

FIG. 11 is a diagram for explaining the processing in the case where cell discard and misdelivery occur according to the above method. (A)
As described above, when cell discard occurs, dummy cells equal to the number of discarded cells are inserted. When the cells with SNs 4 and 5 are discarded, the write control unit 18 is notified of the discard occurrence signal 1
A signal of 9 and the number of discarded cells '2' is input. Receiving this signal, the write address generator 18-2 (FIG. 9)
Advances the write address 17 by "2". As a result, a space for 2 cells is provided in the buffer 4 and a dummy cell is inserted.

When a cell mis-delivery occurs as shown in (b), for example, the SN is 6 between the cell having the SN of 3 and the cell having the SN of 4.
When the mis-distributed cell arrives, the write control unit 18
The misdelivery occurrence signal 20 is input. The write address generation unit 18-2 receiving the signal 20 changes the write address 17
Does not count up. Thereby, the correct cell with SN of 3 is overwritten on the mis-distributed cell and the mis-distributed cell is removed.

(Absorption Buffer Read Control Unit) FIG. 12 is a block diagram showing the configuration of the absorption buffer read control unit 27. The read control unit 27 uses the address information 33 from the read timing generation unit 31, the buffer write address 17 from the write control unit 18, and the read enable flag 29 from the small delay cell search unit 30 to read the read address of the absorption buffer 4. Delay fluctuation absorption buffer address generation unit 27-1 that generates 23 (16 bits), address information 33, and cell-en from absorption buffer 4
It is composed of a read address information memory 27-2 that counts the number of cells and bytes 27-3 using the d output 24 and the VC-head output 25.

First, the configuration of the read address 23 in the case where all the data stored in the absorption buffer 4 is VC-3 (the input data is the AU-3 structure) will be described with reference to FIG. Of the 16 bits of the read address 23, the upper 2 bits (b16, b15) are the 2-bit AU-3 output from the read timing generation unit 31.
The structural address information 33 is used. Upper 2 bits (b
If the value of (16, b15) is “00”, it specifies the AU # 1 area in the buffer, if it is “01”, it specifies the AU # 2 area, and if it is “10”, it is AU # 3. Specify the area. All the 8 bits (f24 to f17 in FIG. 13) of the cell counter for the AU area designated by the upper 2 bits are used for the middle 8 bits (b14 to b7). This is the cell storage area (for 256 cells) in the specified AU area,
Specify which cell storage area to read. These 8 bits are counted up when the lower 6 bits are reset. A byte counter (f16 to f11 in FIG. 13) is used for the lower 6 bits (b6 to b1). This specifies the byte position of each cell storage area specified by the middle-order bit, and is reset to '0' when the cell-end signal 24 is output from the absorption buffer 4.

Next, the structure of the read address 23 in the case where all the data accumulated in the absorption buffer 4 is VC-11 (input data is TU-11 structure) is shown in FIG.
Will be explained. Higher 7 of 16 bits of address
For the bits (b16 to b10), the 7-bit TU-11 structure address information 33 output from the read timing generation unit 31 is used. The upper 2 bits of the 7 bits specify the AU to which the TU-11 belongs, and the next 3 bits
The bit specifies the TUG to which it belongs, and the remaining 2 bits,
Specifies the four TU-11s in the TUG. In the middle 3 bits (b9 to b7), the T specified by the upper 7 bits is set.
The lower 3 bits (f19 to f17 in FIG. 13) of the 8 bits of the cell counter for the U-11 area are used. This is the specified TU-11 cell storage area (8 cells).
Specify which cell to read. Also, the bottom 6
Counts up when the bit is reset. A byte counter is used for the lower 6 bits (b6 to b1) as in the case of the AU-3 structure. As described above, the read address 23 of the absorption buffer 4 is generated.

(Read Timing Generation Unit) The read timing generation unit 31 generates the address information 33 (7 bits) of the absorption buffer 4 and instructs the position information 32 of the STM-1 frame. First, the address information 33 will be described. If the data stored in the absorption buffer 4 has the AU-3 structure, the upper 2 bits of the 7 bits are counted up in byte units. And '0
One cycle consists of 0 ',' 01 ', and' 10 '. This is sent to the read control unit 27 as the address information 33 for AU-3 and is used as a part of the read address 23.

If the stored data has the TU-2 structure, the upper 5 bits of the 7 bits are transmitted. Of these, the upper 2 bits are counted up in byte units as in the case of the AU-3 structure, and the remaining 3 bits are the upper 2 bits.
It counts up every one bit cycle. And
'000' to '110' is one cycle. This is T
The read control unit 27 uses the address information 33 for U-2.
To be a part of the read address 23.

If the stored data has the TU-11 structure, all 7 bits are transmitted.

At this time, the upper 5 bits are counted up as in the case of the TU-2 structure, and the lower 2 bits are counted up every cycle of the upper 5 bits. This is used as address information for TU-11, is sent to the absorption buffer read control unit 27, and is made a part of the read address 23.

Next, the position information 32 of the STM-1 frame
(2 bits) will be described. The read timing generation unit 31 generates the position information 32 (2 bits) of the STM-1 frame and gives it to the selector 34. Location information 32
Is '00', the output from the absorption buffer 4 is selected, if '01', a newly generated AU pointer or TU pointer 26, which will be described later, is selected, and if '10', STM-1. VC in frame SOH or AU-3
-3 Select "0" to be output to the POH position.

(Generation of AU Pointer / TU Pointer) FIG. 14 is a timing chart for explaining a method of generating the newly generated AU-3 pointer. ATM / ST
Generation of a new M-converted AU-3 pointer is performed by the STM.
H3 of AU-3 pointer when constructing -1 frame
From the byte next to the byte, counting up of the AU pointer (f10 ... f1 in FIG. 13) in the read address information memory 27-2 is started. After that, absorption buffer 4
Every time the VC stored therein is output, it is incremented. That is, when the SOH or AU pointer of the STM frame is output, it is not counted. Then, the value (b in FIG. 14) at the time when the VC-head flag inserted at the time of writing is output from the absorption buffer 4 is changed to the new A
U pointer value.

FIG. 15 is a timing chart illustrating the method of generating the TU-11 pointer. In the case of TU-11, a fixed value '522' (distance in bytes from H3 to the beginning of the next frame) is inserted in the AU-3 pointer area (H1, H2). As a result, VC
Fix the POH position at -3. The TU-11 pointer has three areas V1, V2, and V3.
To output the TU-11 pointer value. V3 is also used for negative justification opportunity. These three are discriminated by the H4 byte in the POH of VC-3. If the value of H4 is '00', the TU-11 pointer of the next AU-3 frame is V1, V2 is '01', and V3 is '10'. The TU-11 pointer counts up the AU pointer in the read address information memory from the next byte that outputs V2. Then, the value at the time when V5 is output is set to the new TU-11.
It is a pointer value.

(Small delay cell search unit) Read control unit 27
Then, in addition to the address generation, the write address 17 and the read address 23 are always compared in order to detect an underflow or overflow of the absorption buffer 4. When both addresses are equal, it is determined as underflow, and when the difference between both addresses is equal to the buffer capacity, it is determined as overflow, and an underflow or overflow generation signal 28 is added to the small delay cell search unit 30.

In this embodiment, the reception ATM cell 1 absorbs the delay fluctuation received in the network. Further, in order to prevent overflow or underflow of the absorption buffer 4, it is necessary to determine the cell read start time.

FIG. 16 shows a timing chart of the processing of the small delay cell search unit 30 which determines the read start time. The first cell arrival time Tk1 is used as the reference timing. An expected value Tk2 ′ of the arrival time of the second cell is calculated by adding the cell arrival interval T to Tk1. Next, the arrival timing of the second cell is compared with Tk2 '. In the case of the figure, Tk2' is earlier, so this value is set to Tk2. The next expected value (Tk3 ′) is calculated from Tk2. Similarly, the arrival timing of the third cell is compared with Tk3 ′. Since the arrival timing is earlier, the timing is set to Tk3, and Tk4 ′ is calculated. The above operation is repeated until the fifth cell is input, and the timing at that time is set to Tk5. Qmax calculated in advance in Tk5 (amount considered not to cause underflow or overflow of buffer)
The reading of the absorption buffer is started from the time when is added.

By the above operation, the S in the received ATM cell is
Reassemble the TM signal into an STM-1 frame. Further, by simultaneously extracting the STM signal from the cell and performing the pointer calculation, the delay time associated with the ATM / STM conversion can be reduced.

In the above embodiment, the description has been made mainly on the portion for converting the signal of the ATM cell into the signal of the STM-1 frame. However, the plural (N) signals of the converted STM-1 frame are multiplexed in byte units. By STM-
It is clear that N frames are obtained.

[0049]

According to the present invention, only the VC in the AU pointer or TU pointer of the STM signal accommodated in the received ATM cell is written in the delay fluctuation absorption buffer, and V
Since C is read and a new AU pointer or TU pointer of the STM-N frame of the STM signal is generated, the phase adjustment time can be shortened. Therefore, a frame memory for phase adjustment is not needed.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of an ATM / STM converter according to the present invention.

FIG. 2 is a diagram showing a configuration of a delay fluctuation absorption buffer 4 of FIG. 1 when all AU-3 signals are input.

FIG. 3 is a diagram showing a configuration of a delay fluctuation absorbing buffer 4 in FIG. 1 when all TU-11 signals are input.

FIG. 4 is a diagram showing a 1-cell storage area of the delay fluctuation absorption buffer 4 of FIG.

5 is a diagram showing a configuration of a VPI identifying unit 9 in FIG.

FIG. 6 shows VC-head (J in one embodiment of the present invention.
1) Detection processing time chart

FIG. 7 shows VC-head (V in one embodiment of the present invention.
5) Detection processing time chart

FIG. 8 is a diagram for explaining cell-end flag insertion in the embodiment of the present invention.

9 is a diagram showing a configuration of a delay fluctuation absorption buffer write control unit in FIG.

FIG. 10 is a diagram for explaining processing when cell discard / mis-delivery occurs in one embodiment of the present invention.

FIG. 11 is a diagram for explaining processing when a cell discard / erroneous distribution occurs in the embodiment of the present invention.

FIG. 12 is a diagram showing a configuration of a delay fluctuation absorption buffer read address control unit 27 in one embodiment of the present invention.

FIG. 13 is a diagram showing a configuration of a read address information memory according to an embodiment of the present invention.

FIG. 14 is a time chart of AU pointer generation processing according to an embodiment of the present invention.

FIG. 15 is a time chart of TU pointer generation processing according to an embodiment of the present invention.

FIG. 16 is a time chart of a small delay cell search process in the embodiment of the present invention.

FIG. 17 is an example of a transmission network that transmits an STM signal via an ATM network.

FIG. 18 is a frame configuration diagram of an STM-1 signal according to CCITT recommendation.

FIG. 19 is a block diagram of an ATM cell.

FIG. 20 is a diagram illustrating accommodation of an STM signal in an ATM signal.

FIG. 21 is a diagram for explaining phase adjustment in conventional ATM / STM conversion.

[Explanation of symbols]

1 ... Input ATM cell 1-1 ... Input ATM cell internal structure 1-2 ... SN field 1-3 ... SNP field 2 ... Data output from delay fluctuation absorbing buffer 3 ... Output STM signal 4 ... Delay fluctuation absorbing buffer 5 ... SN, SNP byte 6 ... Frame phase extraction unit 7 ... Write counter 8 ... Internal VP 9 ... VPI identification unit 9-1 ... Cell structure memory 9-2 ... STM identifier generation unit 9-3 ... Cell structure information 9-4 ... Cell STM signal type 10 ... SN 11 ... STM identifier 12 ... byte number bit 13 ... cell end insertion position information 14 ... VC-head flag 15 ... cell end flag 16 ... delay fluctuation absorption buffer write enable signal 17 ... delay fluctuation absorption buffer Write address 18 ... Delay fluctuation absorption buffer write controller 18-1 Write address information memory 18-2 ... Write address generation unit 18-3 ... Write address information 19 ... Cell discard detection signal 20 ... Cell misalignment detection signal 21 ... Cell discard / misalignment detection unit 22 ... Delay fluctuation absorption buffer read enable 23 ... delay fluctuation absorption buffer read address 24 ... cell-end from delay fluctuation absorption buffer
Output 25 ... VC-head output from delay fluctuation absorption buffer 26 ... Generated AU pointer or TU pointer 27 ... Delay fluctuation absorption buffer read control unit 28 ... Overflow or underflow generation signal 29 ... Readable flag 30 ... Small delay Cell search unit 31 ... Read timing generation unit 32 ... STM frame information 33 ... Read address information 34 ... Read signal selector

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Nobuhiro Ashi 216 Totsuka-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Hitachi, Ltd. Information & Communication Division

Claims (14)

[Claims] 1. AU-3, TU-2, T of STM signals
From an ATM signal accommodating U-12 or TU-11 to AU
-3, TU-2, TU-12 or TU-11 virtual container and the first step of separating the AU-3, TU-2, TU-12 or TU-11 AU or TU pointer, and the virtual container And a third step of newly generating an AU pointer or a TU pointer used for the STM-1 frame and mapping the AU pointer or TU pointer to the STM-1 frame. ATM / STM conversion method. 2. The STM-1 frame signal obtained by the ATM / STM conversion method according to claim 1 is multiplexed in N (N is an integer) byte by byte to form an STM-N frame signal. ATM / STM conversion method. 3. The ATM / STM conversion method according to claim 1 or 2, wherein said first step separates a header and a cell pointer from a cell of said ATM signal, and a cell pointer separated by said separation step. From the AU pointer or the TU-2, TU-12 or TU
Find the position of the TU pointer contained in -11,
A pointer decoding step of decoding the AU pointer or TU pointer, and ST stored in the ATM signal
When the M signal is AU-3, normally, the H1 byte, H2 byte, and H3 byte of the AU pointer specified in the STM signal are removed, and the normal justification is added to the byte next to the H3 byte. When done, the above H1 byte, H2 byte, H3 byte and H3 byte
When the next justified byte is removed and the H3 byte is negatively justified, the H1 byte and the H2 byte are removed, and the STM signal contained in the ATM signal is TU-2. , TU-12 or TU-11, normally, V in TU-2, TU-12 or TU-11 specified in the STM signal is specified.
1 byte, V2 byte, V3 byte and V4 byte are removed, and when the justification is made to the byte next to the V3 byte, the V1 byte,
The V2 byte, the V3 byte, and the 1 byte next to the V3 byte are removed, and when the V3 byte is negatively justified, a removal step of removing the V1 byte and the V2 byte, and a step other than the removal The signal is sent to the AU-3, TU-2, TU-12 or TU-11.
And an extraction step of extracting the virtual container as an ATM / STM conversion method. 4. The ATM / STM conversion method according to claim 3, wherein said pointer decoding step loads said AU pointer or TU pointer into a counter, and from said counter, the payload portion in said ATM signal is byte-wise. The byte at the time when the counter counts down to "0" is set as the first byte of the virtual container of the STM signal, and the ST contained in the ATM signal is stored.
When the M signal is AU-3, the number of bytes is set to AU-3
J1 byte indicating the beginning of the virtual container in
The STM signal is TU-2, TU-12 or TU-11.
, If the byte is TU-2, TU-12 or T
An ATM / STM conversion method, characterized in that it is V5 bytes indicating the beginning of a virtual container in U-11. 5. The ATM / STM conversion method according to claim 1, wherein the signal of the virtual container obtained in the first step is written in a buffer memory, and the second
The step includes the step of reading the signal of the virtual container from the buffer memory, and the write address of the buffer memory is the virtual path identifier described in the cell header of the ATM signal, and the AU-3 for each virtual path identifier. , TU-2, TU-1
2. If the STM signal converted into the STM identifier for identifying TU-11 and contained in the ATM signal is AU-3,
The STM used in the upper 2 bits of the address of the buffer memory of the STM identifier and accommodated in the ATM signal
When the signal is TU-2, the STM identifier is used for the upper 5 bits of the address of the buffer memory,
The STM signal contained in the signal is TU-12 or TU-1
In the case of 1, the STM identifier is used for the upper 7 bits of the address of the buffer memory.
/ STM conversion method. 6. The ATM / STM conversion method according to claim 5, wherein when the cell discard is detected in the first step, the write address is advanced by the number of discarded cells. 7. The ATM / STM conversion method according to claim 5, wherein when a cell mis-delivery is detected in the first step, the write address to be given to the buffer memory is stopped by one cell and the next normal cell is set to the above-mentioned normal cell. An ATM / STM conversion method characterized by overwriting on an erroneously distributed cell. 8. The ATM / STM conversion method according to claim 3, wherein the first step is the write side of the buffer memory, wherein the first byte of the virtual container of the STM signal obtained in the pointer decoding step is the buffer memory. At the same time as writing to the buffer memory, the flag signal indicating the first byte is written in the buffer memory, the third step is provided with a counter on the reading side, and the STM signal contained in the ATM signal is AU-3.
In the case of, from the byte next to the H3 byte in the output STM-N frame, the area other than the section overhead specified in the STM signal of the STM frame is counted up in byte units using the counter, and the flag is added. The value of the counter at the time when the signal is output from the buffer memory is used as the AU pointer used for the STM-N frame, and the STM signal contained in the ATM signal is TU-
In case of 2, TU-12 or TU-11, the above output STM
-From the byte next to the V2 byte in the N frame to the above ST
The section overhead of the M frame and the TU-
2 or the above V1 byte in TU-12 or TU-11,
Areas other than V2 bytes, V3 bytes, and V4 bytes are counted up in byte units using the counter, and the value of the counter at the time when the flag signal is output from the buffer memory is used for the STM-N frame. A comprising a step of making a TU pointer
TM / STM conversion method. 9. A write control means for extracting a virtual container signal of the STM signal from an ATM signal accommodating an STM signal and writing it in a buffer memory, and a read control for reading the virtual container signal from the buffer memory in byte units. Means, a pointer generating means for generating an AU pointer or a TU pointer used for an STM-N frame of a new STM signal, a byte unit signal read from the buffer memory, and an AU pointer or TU from the pointer generating means. AT having means for mapping a pointer to the STM-N frame
M / STM converter. 10. A first memory for the write control means to generate an STM identifier using a virtual path of a cell of the ATM signal as an address, a write counter for counting the number of bytes of the cell, the STM identifier and the byte. A timing control section for inputting a number and generating a write address for designating an area divided for each virtual path identifier of the ATM signal of the buffer memory, the timing control section for determining the read timing by the read control means; 10. The ATM / STM according to claim 9, further comprising a read control unit for generating a read address of the buffer memory memory for each of the virtual path identifiers using information from the timing generation unit.
Conversion device. 11. An apparatus for extracting a part of the STM signal from an ATM signal accommodating an STM signal and converting the part of the STM signal into a new STM signal of an STM-N frame by using the part of the STM signal. First means for extracting a cell pointer of an ATM signal, second means for extracting an AU pointer or a TU pointer in the STM signal using the cell pointer, and the AU pointer or the TU pointer extracted by the second means From the above ATM signal and the above ST
A third means for extracting the signal of the virtual container of the M signal, a fourth means for extracting the first byte of the virtual container, a signal of the virtual container, and a first byte of the virtual container , A buffer memory that also stores a flag signal indicating that the byte is the head of the virtual container, a fifth means for generating an AU pointer or a TU pointer used for the STM-N frame, and the virtual memory from the buffer memory. The reading means for reading the signal of the container in byte units, the AU pointer or TU pointer from the fifth means and the signal from the reading means for the STM-
An ATM / STM converter having a sixth means for mapping to N frames. 12. The second means loads the extracted cell pointer into a counter provided on the write side of the buffer memory, counts down the payload portion of the ATM signal in byte units by the counter, and outputs "0".
When the STM signal contained in the ATM signal is AU-3, the byte input at the time of becomes a part of the AU pointer or a part of the TU pointer, and a part of the AU pointer. The AU pointer is extracted from the H1 byte and H2 byte in a certain AU-3, and the STM signal contained in the ATM signal is TU-2.
, The TU-2 that is a part of the TU pointer
The TU pointer is extracted from the V1 byte in the above and the V2 byte which is a byte 108 bytes after the above byte.
When the STM signal contained in the TM signal is TU-12, the TU pointer is moved from the V1 byte in the TU-12 which is a part of the TU pointer and the V2 byte which is the byte 36 bytes after the byte. The STM signal extracted and contained in the ATM signal is TU-1.
In the case of 1, the TU- which is a part of the TU pointer.
12. The ATM according to claim 11, comprising means for extracting a TU pointer from a V1 byte in 11 and a V2 byte which is a byte 27 bytes after the V1 byte.
/ STM converter. 13. The third means and the buffer memory are the first.
Writing the byte of the cell pointer extracted by the means or the byte of the AU pointer extracted by the second means or the byte of the TU pointer to the buffer memory, the byte of the cell pointer of the buffer memory, the byte of the AU pointer or the TU pointer 12. The ATM / STM conversion device according to claim 11, wherein the same byte address as the address in which the byte is written is configured to overwrite the signal byte of the next virtual container. 14. The first means writes the head byte extracted by the fourth means into the buffer memory and at the same time, sends a flag signal indicating that the byte is the head of the virtual container to the buffer memory. The fifth means has a writing means, a counter is provided on the read side of the buffer memory, and the STM signal contained in the ATM signal is AU-3.
In this case, from the byte following the H3 byte in the STM-N frame, the area other than the section overhead of the STM-N frame is counted up in units of bytes using the counter, and a signal indicating the beginning of the virtual container. Is used for the STM-N frame using the value of the counter at the time when is output from the buffer memory.
As a U pointer, the STM signal contained in the ATM signal is TU-2
Or, in the case of TU-12 or TU-11, the above output STM
-From the byte next to the V2 byte in the N frame to the above ST
Section overhead of M frame and the V1 byte, V2 in the TU-2 or TU-12 or TU-11.
Areas other than bytes, V3 bytes, and V4 bytes are counted up in units of bytes using the counter, and the value of the counter when the signal indicating the head of the virtual container is output from the buffer memory is
12. The ATM / ST according to claim 11, wherein the ATM / ST comprises a TU pointer used for an MN frame.
M conversion device.