JPH08181286A

JPH08181286A - Semiconductor memory cell and its manufacture

Info

Publication number: JPH08181286A
Application number: JP7091587A
Authority: JP
Inventors: Akihiko Ochiai; Hajime Yagi; 肇矢木; 昭彦落合
Original assignee: Sony Corp; ソニー株式会社
Priority date: 1994-10-28
Filing date: 1995-03-24
Publication date: 1996-07-12

Abstract

PURPOSE: To pattern a ferrodielectric thin film securely into a required pattern without etching the ferrodielectric thin film and a lower electrode simultaneously by a method wherein the ferroelectric thin film connected to a contact plug is formed on an insulating layer and an upper electrode is formed on the ferroelectric thin film. CONSTITUTION: Source/drain regions 15 and 16 and channel regions 17 which are formed in a semiconductor substrate 10, gate electrodes 13 above the channel regions 17 and insulating layers 14, 18 and 20 which cover the source/drain regions 15 and 16 and the gate electrodes 13 are provided. A contact plugs 22 which are formed in the insulating layers 18 and 20 above the one side region 15 of the source/drain regions 15 and 16 and are electrically connected to those regions 15 are provided. Further, ferroelectric thin films 23 connected to the contact plugs 22 and upper electrodes 24 on the ferroelectric thin films 23 are provided. For instance, the ferroelectric thin film 23 is made of PZT system compound, etc.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory cell using a ferroelectric thin film and a method for manufacturing the same, more specifically, a nonvolatile memory cell using a ferroelectric thin film (so-called FERA).
The present invention relates to a semiconductor memory cell composed of M) or DRAM and a manufacturing method thereof.

[0002]

2. Description of the Related Art In recent years, application research of nonvolatile memory cells using a ferroelectric thin film has been actively pursued with the progress of film forming technology. This non-volatile memory cell is a non-volatile memory cell in which high-speed reversal of the ferroelectric thin film and high-speed rewriting utilizing the residual polarization thereof are possible. The ferroelectric thin film non-volatile memory cells that are currently being researched are divided into two methods: one that detects changes in the amount of charge stored in the ferroelectric capacitor and one that detects changes in the resistance of the semiconductor due to spontaneous polarization of the ferroelectric. Can be classified. The semiconductor memory cell of the present invention belongs to the former.

An example of a non-volatile memory cell that detects a change in the amount of charge stored in a ferroelectric capacitor is a non-volatile memory cell having a 1-capacitor + 1 transistor structure in which a selection transistor is added to the ferroelectric capacitor. You can The ferroelectric capacitor is composed of, for example, a lower electrode, an upper electrode, and a ferroelectric thin film sandwiched between them. Data writing and reading in this type of non-volatile memory cell are performed by applying the PE hysteresis loop of the ferroelectric substance shown in FIG. When an external electric field is removed after applying an external electric field to the ferroelectric thin film, the ferroelectric thin film exhibits spontaneous polarization. The remanent polarization of the ferroelectric thin film becomes + P _r when an external electric field in the positive direction is applied, and −P _r when an external electric field in the negative direction is applied. Where remanent polarization is + P _r
The state (see “D” in FIG. 8) is set to “0”, and the state in which the remanent polarization is −P _r (see “A” in FIG. 8) is “
1 ".

In order to determine the state of "1" or "0", an external electric field in the positive direction, for example, is applied to the ferroelectric thin film. As a result, the polarization of the ferroelectric thin film becomes the state of "C" in FIG. At this time, if the data is "0", the polarization state of the ferroelectric thin film changes from "D" to "C". On the other hand, if the data is "1", the polarization state of the ferroelectric thin film changes from "A" to "C" via "B". If the data is "0",
The polarization reversal of the ferroelectric thin film does not occur. On the other hand, the data is "
In the case of 1 ", polarization inversion occurs in the ferroelectric thin film. As a result, there is a difference in the amount of charge stored in the ferroelectric capacitor. This storage is turned on by turning on the select transistor of the selected memory cell. The charge is detected as a signal current.
When the external electric field is set to 0 after reading the data, the polarization state of the ferroelectric thin film becomes the state of “D” in FIG. 8 regardless of whether the data is “0” or “1”. Therefore, when the data is "1", an external electric field in the negative direction is applied to bring the state of "A" through the paths "D" and "E", and the data "1" is written.

Such a non-volatile memory cell is described in, for example, the specification of US Pat. No. 5,229,309 and the document “Required performance in view of operation principle and application of ferroelectric memory cell”, Toshio Tanaka. Written by Tokyo Institute of Technology, Joint symposium "Device application of high-dielectric / ferroelectric thin films" 1
It is known from January 27, 994, pages 70 to 79 (hereinafter referred to simply as literature).

In the non-volatile memory cell disclosed in the specification of US Pat. No. 5,229,309, an insulating layer 111 is formed on a source region 103 formed on a semiconductor substrate, and the insulating layer 111 is formed on the insulating layer 111. A polysilicon layer 106 is formed in the formed opening and on the insulating layer 111. Then, Pt or P is formed on the polysilicon layer 106.
lower electrode 107 composed of d, ferroelectric thin film 108, Al
Is formed on the upper electrode 109.

On the other hand, FIG. 11 on page 79 of the above document.
In (a), a lower electrode is connected to one source / drain of a MOS transistor through a contact plug, a ferroelectric thin film is formed on this lower electrode, and further on this ferroelectric thin film. A nonvolatile memory cell having a structure in which a plate line is formed is shown. For reference, the non-volatile memory cell shown in FIG. 11A on page 79 of the document is shown in FIG. 9 attached to this specification.

[0008]

SUMMARY OF THE INVENTION US Pat. No. 5,2
In the manufacture of the non-volatile memory cell disclosed in the specification of No. 29,309, the ferroelectric thin film and the lower electrode are simultaneously patterned into a desired shape by the sputter etching method. The lower electrode is composed of Pt or Pd, while the ferroelectric thin film is composed of PbTiO ₃ , PZT, PLZT or the like. Therefore, when patterning the ferroelectric thin film and the lower electrode at the same time by the sputter etching method, it is necessary to change the etching conditions during the process, and the reproducibility of the processed shape of the ferroelectric thin film and the lower electrode becomes poor. However, there is a problem that it is difficult to select and control the optimum etching conditions. Alternatively, the ferroelectric thin film is RI
There is also a method of patterning by the E method and patterning the lower electrode by the ion milling method, but such a method also has the same problem because it is necessary to change the etching conditions during the process.

In the non-volatile memory cell disclosed in the specification of US Pat. No. 5,229,309 and the above-mentioned document, the side surface of the ferroelectric thin film is not exposed when the patterning of the ferroelectric thin film is completed. It is exposed.
Therefore, when forming, for example, an insulating layer on the ferroelectric thin film in the next step, the residual polarization ± P _r of the ferroelectric thin film may decrease due to the adverse effect of hydrogen and moisture.

Therefore, an object of the present invention is to provide a semiconductor memory cell having a structure in which the ferroelectric thin film and the lower electrode need not be simultaneously etched, and the ferroelectric thin film can be reliably patterned into a desired shape. It is to provide a manufacturing method. A further object of the present invention is to provide a semiconductor memory cell having a structure in which a ferroelectric thin film is not adversely affected in a subsequent step, and a method for manufacturing the same.

[0011]

To achieve the above object, a semiconductor memory cell of the present invention comprises: (a) a source / drain region and a channel region formed on a semiconductor substrate;
(B) A gate electrode formed above the channel region, (c) an insulating layer covering the source / drain regions and the gate electrode, and (d) an insulating layer above one source / drain region. A contact plug electrically connected to the one source / drain region, (e) a ferroelectric thin film formed on the insulating layer and connected to the contact plug, and (f) the ferroelectric thin film. And an upper electrode formed on the body thin film.

In the semiconductor memory cell of the present invention, the ferroelectric thin film is preferably made of PbTiO ₃ , a PZT compound, or a Bi compound having a layered structure.
As the PZT-based compound, lead zirconate titanate (PZT), which is a solid solution of PbZrO ₃ and PbTiO ₃ having a perovskite structure, PLZT, which is a metal oxide obtained by adding La to PZT, or metal oxide obtained by adding Nb to PZT. An example is PNZT. Also,
As the Bi-based compound having a layered structure, SrBi ₂ Ta ₂ O ₉ and SrBi ₂ Nb ₂ having a perovskite structure are used.
O ₉ , BaBi ₂ Ta ₂ O ₉ , SrBi ₄ Ti ₄ O ₁₅ , Bi ₄
Ti ₃ O ₁₂ , SrBi ₂ TaNbO ₉ , PbBi ₂ Ta ₂ O ₉
And the like.

From the viewpoint that the ferroelectric thin film is not adversely affected in the subsequent steps, it is preferable that the upper electrode covers the ferroelectric thin film.

The upper electrode is, for example, Pt, Pd, Ru
O ₂ , IrO ₂ , Pt / Ti laminated structure, Pt / Ta laminated structure, Pt / Ti / Ta laminated structure, La _0.5 Sr _0.5
CoO ₃ (LSCO), Pt / LSCO laminated structure, Y
It can be composed of Ba ₂ Cu ₃ O ₇ . The upper electrode may also serve as the plate line, or the plate line may be provided separately from the upper electrode.

The contact plug has, for example, tungsten, Ti, Pt, P in the opening formed in the insulating layer.
It is preferable to have a structure in which a metal wiring material made of a refractory metal such as d or Cu or polysilicon is embedded. The top surface of the contact plug may exist on the same plane as the surface of the insulating layer, or the top portion of the contact plug may extend to the surface of the insulating layer.

As a form of the semiconductor memory cell of the present invention,
Non-volatile memory cell (so-called FERAM) or DRA
M can be mentioned.

A method of manufacturing a semiconductor memory cell according to the present invention for achieving the above object comprises: (a) a step of forming a gate electrode, a source / drain region and a channel region on a semiconductor substrate; A step of covering the drain region and the gate electrode with an insulating layer; and (c) a step of forming a contact plug electrically connected to the one source / drain region in the insulating layer above the one source / drain region. And (d) a step of forming a ferroelectric thin film connected to the contact plug on the insulating layer and then patterning the ferroelectric thin film into a desired shape, and (e) the ferroelectric. And a step of forming an upper electrode on the thin film.

In the method of manufacturing a semiconductor memory cell of the present invention, the contact plug is formed by forming an opening in the insulating layer and filling the opening with a metal wiring material or polysilicon (polysilicon doped with impurities). It is preferably formed. Specifically, there is a so-called blanket tungsten CVD method in which a metal wiring material made of tungsten is deposited on the insulating layer including the inside of the opening by a CVD method and the metal wiring material on the insulating layer is removed by an etching method. However, as a metal wiring material, Ti or P
A high melting point metal such as t, Pd, or Cu can also be used.
A part of the metal wiring material may be left on the insulating layer.

In the method for manufacturing a semiconductor memory cell of the present invention, the ferroelectric thin film is preferably made of a PZT compound or a Bi compound having a layered structure. The ferroelectric thin film can be formed by, for example, the MOCVD method, the pulse laser ablation method, or the sputtering method.

From the viewpoint that the ferroelectric thin film is not adversely affected in the subsequent steps, it is preferable to cover the ferroelectric thin film with the upper electrode.

The upper electrode is made of, for example, Pt, Pd, RuO.
₂ , IrO ₂ , Pt / Ti laminated structure, Pt / Ta laminated structure, Pt / Ti / Ta laminated structure, La _0.5 Sr _0.5 C
oO ₃ (LSCO), Pt / LSCO laminated structure, YB
a ₂ Cu ₃ O ₇ and these materials are formed on an insulating layer including a ferroelectric thin film by, for example, a sputtering method or a pulse laser ablation method, and then formed into a desired shape by an ion milling method or an RIE method. It can be formed by patterning.

In the method of manufacturing a semiconductor memory cell of the present invention, the upper electrode may be patterned so that the upper electrode also serves as a so-called plate line, or the plate line may be formed separately from the upper electrode. Further, the other source / drain region may also serve as a bit line, or a bit line electrically connected to the other source / drain region may be formed.

[0023]

In the present invention, the contact plug corresponds to the lower electrode in the prior art. Therefore, when the ferroelectric thin film is formed and then patterned into a desired shape, unlike the conventional technique, the patterning of the lower electrode is unnecessary. Therefore, it is possible to optimize the formation and processing conditions of the contact plug and the ferroelectric thin film corresponding to the lower electrode. Further, since the contact plug is used as the lower electrode, the manufacturing process of the semiconductor memory cell can be reduced. Furthermore, by covering the ferroelectric thin film with the upper electrode, it is possible to suppress adverse effects on the ferroelectric thin film in a later process, such as a decrease in remanent polarization ± P _r of the ferroelectric thin film.

[0024]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will now be described based on embodiments with reference to the drawings.

Example 1 A schematic partial sectional view of a semiconductor memory cell of Example 1 is shown in FIG. 2B, FIG. 3A and FIG. 3B. Further, FIG. 4 shows a projection plan view when each region of the semiconductor memory cell is projected on a virtual plane. Partial cross-sectional views obtained by tying and cutting the portion indicated by AA in FIG. 4 correspond to FIGS. 1 and 2, and partially cut and ligated by the portion indicated by BB in FIG. A cross-sectional view corresponds to FIG. 3A, and a partial cross-sectional view obtained by connecting and cutting a portion indicated by CC in FIG. 4 corresponds to FIG. 3B.

As shown in FIG. 2B, the semiconductor memory cell of Example 1 includes source / drain regions 15 and 16 and a channel region 17 formed in a semiconductor substrate 10,
Gate electrode 1 formed above this channel region 17
It consists of three. These source / drain regions 15 and 1
6, the channel region 17 and the gate electrode 13 form a so-called select transistor. In FIG. 2B, one set (two) of selection transistors is formed on the left side. The gate electrode 13 also serves as the word lines WL ₁ , WL ₂ , WL ₃ , WL ₄ ... (See FIG. 4), and is made of, for example, polysilicon.
The source / drain regions 15 and 16 and the gate electrode 13 are covered with the insulating layer 20. Insulation layer 2
0 consists of BPSG, for example. In the figure, reference numeral 11 is an element isolation region having a trench structure, 12 is a gate oxide film, 14 is an insulating film made of SiO ₂ formed on the top surface and side walls of the gate electrode 13, and 18 is a lower layer insulating film. It is a layer.

Further, one source / drain region 15
A contact plug 22 is formed in the insulating layer 20 above (for example, the source region), and the contact plug 22 is electrically connected to one of the source / drain regions 15 at the bottom thereof. In Example 1,
By embedding a metal wiring material made of tungsten or polysilicon doped with impurities in the opening 21,
The contact plug 22 is formed. Further, the top surface of the contact plug 22 exists in substantially the same plane as the surface of the insulating layer 20. The top surface of the contact plug 22 may be projected or recessed from the surface of the insulating layer 20.

A ferroelectric thin film 23 is formed on the insulating layer 20 and connected to the top surface of the contact plug 22. Further, the upper electrode 24 is formed on the ferroelectric thin film 23. The ferroelectric thin film 23 is made of PZT,
The upper electrode 24 is made of Pt. The upper electrode 24 also serves as the plate lines PL ₁ , PL ₂ , PL ₃ ... (FIG. 3).
(B) and FIG. 4). In addition, in FIG. 4, one set of selection transistors is shown surrounded by a double line. The region not surrounded by the double line corresponds to the element isolation region 11.

The other source / drain region 16 (for example, drain region) is bit line (BL in FIG. 3 and B in FIG. 4) via the bit contact portion 19 (see FIG. 4).
L ₁ , BL ₂ , BL ₃ , BL ₄ )).

A method of manufacturing the semiconductor memory cell of Example 1 will be described below with reference to FIGS. 1 and 2 which are schematic partial cross-sectional views of a semiconductor substrate and the like.

[Step-100] First, the element isolation region 11 having a trench structure is formed on the silicon semiconductor substrate 10 by a known method. Next, the surface of the semiconductor substrate 10 is oxidized to form the gate oxide film 12. Then, after depositing a polysilicon layer on the entire surface by, for example, a CVD method, the polysilicon layer is patterned by a photolithography technique and an etching technique to form a gate electrode 13 made of polysilicon. The gate electrode 1
3 also functions as word lines WL ₁ , WL ₂ , WL ₃ , WL _4, ... Next, ion implantation of impurity ions and activation treatment of the implanted impurities are performed, and the source / drain region 1
5, 16 and the channel region 17 are formed. Then C
A SiO ₂ film is deposited on the entire surface by the VD method, and then Si
Etch back the O ₂ film. As a result, the insulating film 14 made of SiO ₂ is formed on the top surface and the side wall of the gate electrode 13. Thus, the structure shown in FIG. 1A can be obtained.

[Step-110] Next, after depositing the lower insulating layer 18 made of, for example, SiO _{2 on the} entire surface by, for example, the CVD method, the lower insulating layer 18 above the other source / drain region 16 is photo-coated. The opening is formed by using the lithography technique and the etching technique. Then, after depositing a polysilicon layer on the lower insulating layer 18 including the inside of the opening by, for example, a CVD method, the polysilicon layer on the lower insulating layer 18 is patterned. Thus, as shown in FIGS. 3 and 4, the other source
Bit lines BL, BL ₁ , BL ₂ , BL ₃ , BL _4, ... Made of polysilicon electrically connected to the drain region 16
・ Is formed. A partial cross-sectional view of this state is omitted.

[Step-120] After that, the source / drain regions and the gate electrode are covered with an insulating layer. Specifically, the insulating layer 20 made of, for example, BPSG is deposited on the entire surface by the CVD method illustrated below. After forming the insulating layer 20 made of BPSG, for example, 90
It is preferable to reflow the insulating layer 20 at 0 ° C. for 20 minutes. Furthermore, if necessary, it is desirable to planarize the insulating layer 20 by chemically and mechanically polishing the top surface of the insulating layer 20 by, for example, a chemical mechanical polishing method (CMP method). Gas used: SiH ₄ / PH ₃ / B ₂ H ₆ Film formation temperature: 400 ° C Reaction pressure: Normal pressure

[Step-130] Next, the contact plug 2 electrically connected to the one source / drain region 15 in the insulating layer above the one source / drain region 15.
Form 2 In the first embodiment, the contact plug 22 is formed by the so-called blanket tungsten CVD method. For that purpose, first, the opening 21 is formed in the insulating layer 20 and the lower insulating layer 18 by using the photolithography technique and the etching technique (see FIG. 1B). Then, a Ti layer and a TiN layer are sequentially formed on the insulating layer 20 including the inside of the opening 21 by, for example, a magnetron sputtering method. The film forming conditions for the Ti layer and the TiN layer are exemplified below. The reason for forming the Ti layer and the TiN layer is to obtain an ohmic low contact resistance, to prevent damage to the semiconductor substrate 10 in the blanket tungsten CVD method, and to improve the adhesion of tungsten. Ti layer (thickness: 20 nm) Process gas: Ar = 35 sccm Pressure: 0.52 Pa RF power: 2 kW Substrate heating: None TiN layer (thickness: 100 nm) Process gas: N ₂ / Ar = 100/35 sccm Pressure: 1 0.0Pa RF power: 6kW Substrate heating: None

Next, a tungsten layer is formed on the TiN layer,
It is deposited by the CVD method under the conditions exemplified below. Gas used: WF ₆ / H ₂ / Ar = 40/400/2250 sccm Pressure: 10.7 kPa Film formation temperature: 450 ° C

After that, the tungsten layer, the TiN layer and the Ti layer on the insulating layer 20 are removed by etching. The etching conditions can be set as follows, for example. First-stage etching: Tungsten layer etching Working gas: SF ₆ / Ar / He = 110: 90: 5 sccm Pressure: 46 Pa RF power: 275 W Second-stage etching: TiN layer / Ti layer etching Working gas: Ar / Cl ₂ = 75 /: 5 sccm Pressure: 6.5 Pa RF power: 250 W

Thus, the structure shown in FIG. 1C can be obtained. In the first embodiment, the top surface of the contact plug 22 and the surface of the insulating layer 20 are located on substantially the same plane. It should be noted that the TiN layer and the Ti layer are not shown in FIGS. 1 and 2. Incidentally, here, the contact plug 2
Reference numeral 2 is formed in a self-aligned manner with the gate electrode 13 also serving as a word line and the bit line.

[Step-140] Next, on the insulating layer 20,
After forming the ferroelectric thin film 23 connected to the contact plug 22, the ferroelectric thin film 23 is patterned into a desired shape. In the first embodiment, the ferroelectric thin film 23 is PZ.
It is made of T and is formed by a magnetron sputtering method. The film forming conditions are exemplified below. Although PZT is amorphous, its characteristics pose no practical problem. Target: PZT process gas: Ar / O ₂ = 90% by volume / 10% by volume Pressure: 4 Pa Power: 50 W Deposition temperature: 500 ° C Thickness of ferroelectric thin film: 0.3 μm

After that, the ferroelectric thin film 2 is formed by, for example, the RIE method.
3 is patterned. Thus, the structure shown in FIG. 2A can be obtained. In the method of manufacturing a semiconductor memory cell according to the present invention, before patterning the ferroelectric thin film 23, the contact plug 2 corresponding to the lower electrode has already been formed.
2 is formed. Therefore, unlike the conventional technique, it is not necessary to pattern the lower electrode at the same time as patterning the ferroelectric thin film 23, and the patterning condition of the ferroelectric thin film 23 can be set to the optimum condition.

[Step-150] Next, the ferroelectric thin film 23.
An upper electrode 24 is formed on top. Specifically, a Pt film is deposited on the insulating layer 20 including the ferroelectric thin film 23 by the RF magnetron sputtering method. The thickness of the Pt film is 0.2 μm
And The RF magnetron sputtering conditions are exemplified below. Anode voltage: 2.6 kV Input power: 1.1 to 1.6 W / cm ² Process gas: Ar / O ₂ = 90/10 Pressure: 0.7 Pa Film forming temperature: 600 to 750 ° C Deposition rate: 5 to 10 mm / Min

After forming the Pt film, the Pt film is patterned into a desired shape by using, for example, an ion milling technique.
Thus, the upper electrode 24 made of Pt is formed. The upper electrode 24 covers the ferroelectric thin film 23. That is, there is no exposed portion on the ferroelectric thin film 23. The upper electrode 24, the ferroelectric thin film 23, and the contact plug 22 corresponding to the lower electrode constitute a ferroelectric thin film capacitor. In the first embodiment, the ferroelectric thin film 23
The upper electrode 24 is left on the insulating layer 20 other than the upper portion, and this portion functions as a plate line (see FIG. 3). That is, the upper electrode 24 is connected to the ferroelectric thin film forming the adjacent semiconductor memory cell. Thus, FIG. 2B, FIG. 3A and FIG. 3B, and FIG.
The semiconductor memory cell shown in is manufactured. An equivalent circuit of the semiconductor memory cell shown in FIG. 4 is shown in FIG.

(Embodiment 2) Embodiment 2 is a modification of the semiconductor memory cell described in Embodiment 1. Example 2 is Example 1
Is that the top of the contact plug 22 extends over the insulating layer 20 (see FIG. 6). Other configurations are similar to those of the first embodiment, and detailed description thereof will be omitted. In the fabrication of the semiconductor memory cell of Example 2, a photolithography technique was used in [Step-140] of Example 1 so that the polysilicon layer, the tungsten layer, or the like remained on the insulating layer 20 in the vicinity of the opening 21. Using polysilicon layer or tungsten layer and TiN layer / T
The i layer may be etched.

(Embodiment 3) Embodiment 3 is also a modification of the semiconductor memory cell described in Embodiment 1. Example 3 is Example 1
Is that plate lines are independently provided, and the upper electrode 24A is not connected to the ferroelectric thin film forming the adjacent semiconductor memory cell (see FIG. 7).
That is, in the semiconductor memory cell of Example 3, the upper insulating layer 30 is formed on the insulating layer 20 including the patterned upper electrode 24A, and the opening 31 is formed in the upper insulating layer 30 above the upper electrode 24A. Is provided. Then, after forming an aluminum-based alloy layer on the upper insulating layer 30 including the inside of the opening 31 by, for example, a sputtering method, the plate line 32 is formed by patterning the aluminum-based alloy layer into a desired shape. It Other configurations and manufacturing methods are the same as those in the first embodiment, and detailed description thereof will be omitted. By independently providing the plate lines in this manner, the degree of freedom in designing the semiconductor memory cell can be increased.

Although the present invention has been described based on the preferred embodiments, the present invention is not limited to these embodiments.

In the embodiment, the ferroelectric thin film made of PZT is formed by the magnetron sputtering method, but PZT or PLZT can be formed by the pulse laser ablation method instead. The film forming conditions in this case are exemplified below. Target: PZT or PLZT Laser used: KrF excimer laser (wavelength 248 nm,
Pulse width 25 nsec, 3 Hz) Output energy: 400 mJ (1.1 J / cm ² ) Film formation temperature: 550 to 600 ° C Oxygen concentration: 40 to 120 Pa

Alternatively, a ferroelectric thin film made of SrBi ₂ Ta ₂ O ₉ can be formed by the pulse laser ablation method. The film forming conditions in this case are exemplified below. Target: SrBi ₂ Ta ₂ O ₉ Laser used: KrF excimer laser (wavelength 248 nm,
Pulse width 25 nsec, 5 Hz) Film formation temperature: 500 ° C. Oxygen concentration: 3 Pa After the film formation of SrBi ₂ Ta ₂ O ₉ , the film is post-baked at 800 ° C. for 1 hour in an oxygen atmosphere.

Although the upper electrode is made of Pt in the embodiment, it may be made of LSCO instead. The film forming conditions by the pulse laser ablation method in this case are exemplified below. Target: LSCO Laser used: KrF excimer laser (wavelength 248 nm,
Pulse width 25 nsec, 3 Hz) Output energy: 400 mJ (1.1 J / cm ² ) Film formation temperature: 550 to 600 ° C Oxygen concentration: 40 to 120 Pa

From the semiconductor memory cell of the present invention, a nonvolatile memory cell using a ferroelectric thin film (so-called FERAM) is used.
Not only can DRAM be configured. In this case, only the polarization of the ferroelectric thin film is used. That is, the characteristic that the difference (P _max −P _r ) between the maximum (saturation) polarization P _{max due} to the external electrode and the remnant polarization P _r when the external electrode is 0 has a constant proportional relationship with the power supply voltage is used. To do. The polarization state of the ferroelectric thin film is always between the saturation polarization (P _max ) and the remanent polarization (P _r ) and is not inverted. Data is retained by refresh.

In the embodiment, the element isolation region 11 having the trench structure has been described as an example, but the element isolation region may have the LOCOS structure. Gate electrode 13
Instead of being composed of a polysilicon layer,
It can also be composed of polycide or metal silicide. The insulating film 14 may be omitted in some cases. As the insulating layer 20, instead of BPSG, Si
O ₂ , PSG, BSG, AsSG, PbSG, SbS
Known insulating materials such as G, SOG, SiON, and SiN, or laminated materials of these insulating materials can be given. The insulating layer 20 may be smoothed by, for example, a resist etch back method. The procedure for forming the bit line is arbitrary, and for example, the bit line can be formed after forming the upper electrode.

In the embodiment, one source
Although the ferroelectric thin film connected to the contact plug electrically connected to the drain region has been described as an example,
The wiring electrically connected to the contact plug electrically connected to one of the source / drain regions is provided,
A mode in which another connection hole (for example, a via hole) electrically connected to the wiring is formed and the ferroelectric thin film is connected to the connection hole is also included in the semiconductor memory cell of the present invention.

[0051]

According to the present invention, the contact plug corresponds to the lower electrode in the prior art, and when the ferroelectric thin film is patterned into a desired shape, the lower electrode need not be patterned. Therefore, the formation and processing conditions of the contact plug and the ferroelectric thin film corresponding to the lower electrode can be optimized, and the manufacturing yield of the semiconductor memory cell can be improved. Further, since the contact plug is used as the lower electrode, the manufacturing process of the semiconductor memory cell can be reduced and the manufacturing cost of the semiconductor memory cell can be reduced. Furthermore, by covering the ferroelectric thin film with the upper electrode, it is possible to suppress adverse effects on the ferroelectric thin film, such as a decrease in remanent polarization ± P _r of the ferroelectric thin film due to hydrogen or moisture in a later step. It is possible to obtain stable polarization characteristics of the ferroelectric thin film.

[Brief description of drawings]

FIG. 1 is a schematic partial cross-sectional view of a semiconductor substrate or the like for explaining a manufacturing process of a semiconductor memory cell according to a first embodiment.

2 is a schematic partial cross-sectional view of a semiconductor substrate or the like for explaining the manufacturing process of the semiconductor memory cell of Example 1, and a schematic partial cross-section of the manufactured semiconductor memory cell, following FIG. 1; It is a figure.

FIG. 3 is a schematic partial cross-sectional view of a semiconductor memory cell of Example 1.

FIG. 4 is a projection plan view when each region of the semiconductor memory cell of Example 1 is projected on a virtual plane.

5 is an equivalent circuit diagram of the semiconductor memory cell shown in FIG.

FIG. 6 is a schematic partial cross-sectional view of a semiconductor memory cell of Example 2.

FIG. 7 is a schematic partial cross-sectional view of a semiconductor memory cell of Example 3.

FIG. 8 is a PE hysteresis loop diagram of a ferroelectric substance.

FIG. 9 is a schematic partial cross-sectional view of a FERAM according to a conventional technique.

[Explanation of symbols]

10 semiconductor substrate 11 element isolation region 12 gate oxide film 13 gate electrode 14 insulating film 15, 16 source / drain region 17 channel region 18 lower insulating layer 19 bit contact portion 20 insulating layer 21, 31 opening 22 contact plug 23 ferroelectric substance Thin film 23 24, 24A Upper electrode 30 Upper insulating layer 32 Plate line WL ₁ , WL ₂ , WL ₃ , WL ₄ Word line BL, BL ₁ , BL ₂ , BL ₃ , BL ₄ Bit line PL ₁ , PL ₂ , PL ₃ Plate line

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI Technical display location H01L 27/108 21/8242 21/8247 29/788 29/792 H01L 29/78 371

Claims

[Claims]

1. A source / drain region and a channel region formed on a semiconductor substrate; (b) a gate electrode formed above the channel region; and (c) a source / drain region and a gate electrode. (D) a contact plug formed in the insulating layer above one of the source / drain regions and electrically connected to the one of the source / drain regions, and (e) on the insulating layer. And (f) an upper electrode formed on the ferroelectric thin film and a ferroelectric thin film connected to the contact plug.

2. The semiconductor memory cell according to claim 1, wherein the ferroelectric thin film is made of a PZT compound or a Bi compound having a layered structure.

3. The semiconductor memory cell according to claim 1, wherein the upper electrode covers a ferroelectric thin film.

4. A gate electrode, a source
A step of forming a drain region and a channel region, (b) a step of covering the source / drain region and the gate electrode with an insulating layer, and (c) an insulating layer above one of the source / drain regions,
A step of forming a contact plug electrically connected to the one source / drain region, and (d) forming a ferroelectric thin film connected to the contact plug on the insulating layer, and thereafter forming the ferroelectric thin film. A method of manufacturing a semiconductor memory cell, comprising: a step of patterning a dielectric thin film into a desired shape; and (e) a step of forming an upper electrode on the ferroelectric thin film.

5. The method of manufacturing a semiconductor memory cell according to claim 4, wherein the contact plug is formed by forming an opening in the insulating layer and filling the opening with a metal wiring material.

6. The method of manufacturing a semiconductor memory cell according to claim 4, wherein the ferroelectric thin film is made of a PZT compound or a Bi compound having a layered structure.

7. The method for manufacturing a semiconductor memory cell according to claim 4, wherein the ferroelectric thin film is covered with the upper electrode.