JPH08172112A - Disposition method for ic chip - Google Patents
Disposition method for ic chipInfo
- Publication number
- JPH08172112A JPH08172112A JP6334519A JP33451994A JPH08172112A JP H08172112 A JPH08172112 A JP H08172112A JP 6334519 A JP6334519 A JP 6334519A JP 33451994 A JP33451994 A JP 33451994A JP H08172112 A JPH08172112 A JP H08172112A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- thermal expansion
- electrically connected
- bare chip
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15182—Fan-in arrangement of the internal vias
- H01L2924/15183—Fan-in arrangement of the internal vias in a single layer of the multilayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、ＩＣチップを実装基板
に電気的に接続して配置するためのＩＣチップの配置方
法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an IC chip arranging method for electrically connecting and arranging an IC chip on a mounting board.
【０００２】[0002]
【従来の技術】ウエハー状に形成された、樹脂パッケー
ジに封入する前のベアーのＩＣチップは、フリップチッ
プ法により実装基板に対して配置するようになってい
る。このベアーチップは、ウエハー状に形成されたもの
である。ベアーチップを実装基板に対して実装する場合
に、従来ベアーチップと基板の間に樹脂を充填して、ベ
アーチップと実装基板をその樹脂により一体化して固定
するようにしている。このように樹脂を用いてベアーチ
ップと基板を一体化する理由は、ベアーチップの材質
と、実装基板の材質の膨張率の差により生じるストレス
をこの樹脂で吸収して、長期間電気的接続の信頼性を確
保するためである。2. Description of the Related Art A bare IC chip, which is formed into a wafer and is not sealed in a resin package, is arranged on a mounting substrate by a flip chip method. This bare chip is formed in a wafer shape. When mounting a bear chip on a mounting substrate, conventionally, a resin is filled between the bare chip and the substrate, and the bare chip and the mounting substrate are integrally fixed by the resin. The reason why the bare chip and the substrate are integrated by using the resin in this way is that the resin absorbs the stress caused by the difference in expansion coefficient between the material of the bare chip and the material of the mounting substrate, and long-term electrical connection is achieved. This is to ensure reliability.
【０００３】図２は、従来のベアーチップと実装基板の
接続の方法を示していて、ベアーチップ１はバンプ接続
部２を介して実装基板３側に電気的に接続されるように
なっている。このベアチップ１と実装基板３の間には樹
脂４が封入されるようになっている。FIG. 2 shows a conventional method of connecting a bare chip and a mounting substrate, wherein the bare chip 1 is electrically connected to the mounting substrate 3 side via a bump connecting portion 2. . A resin 4 is sealed between the bare chip 1 and the mounting substrate 3.
【０００４】[0004]
【発明が解決しようとする課題】ところが、このように
ベアーチップと実装基板の間に樹脂を封入する方式で
は、樹脂を充填するためのスペースを必要とし、ベアー
チップの大きさが限定されると共に、上述したようなベ
アーチップと実装基板の間に樹脂を充填もしくは封入す
る工程が必要である。However, such a method of encapsulating the resin between the bare chip and the mounting substrate requires a space for filling the resin, and the size of the bare chip is limited. The step of filling or encapsulating the resin between the bare chip and the mounting substrate as described above is required.
【０００５】そこで、本発明は上記課題を解消するため
になされたものであり、ベアーチップのようなＩＣチッ
プと実装基板の間の熱膨張率の差によるストレスを緩和
して長期的な電気的接続の信頼性を確保することができ
ると共に、樹脂の封入工程を省くことができるＩＣチッ
プの配置方法を提供することを目的としている。Therefore, the present invention has been made in order to solve the above-mentioned problems, and stresses due to a difference in coefficient of thermal expansion between an IC chip such as a bare chip and a mounting substrate are alleviated to provide a long-term electrical conductivity. It is an object of the present invention to provide an IC chip arranging method which can ensure the reliability of connection and can omit the resin encapsulation step.
【０００６】[0006]
【課題を解決するための手段】上記目的は、本発明にあ
っては、ＩＣチップを熱膨張緩和手段に電気的に接続し
て配置し、前記熱膨張緩和手段を実装基板に電気的に接
続して配置するＩＣチップの配置方法により、達成され
る。本発明では、好ましくは前記ＩＣチップは、ベアー
チップであり、前記熱膨張緩和手段に対して、熱圧着で
電気的に接続する。本発明では、好ましくは前記熱膨張
緩和手段は、前記実装基板に対して、はんだ付けにより
電気的に接続する。本発明では、好ましくは前記熱膨張
緩和手段は、ポリイミド両面基板またはポリイミド多層
基板である。In the present invention, the above object is to arrange an IC chip electrically connected to the thermal expansion reducing means, and to electrically connect the thermal expansion reducing means to the mounting substrate. This is achieved by the method of arranging the IC chips. In the present invention, preferably, the IC chip is a bare chip and is electrically connected to the thermal expansion alleviating means by thermocompression bonding. In the present invention, preferably, the thermal expansion alleviating means is electrically connected to the mounting board by soldering. In the present invention, the thermal expansion relaxation means is preferably a polyimide double-sided board or a polyimide multilayer board.
【０００７】[0007]
【作用】上記構成によれば、本発明にあっては、ＩＣチ
ップを熱膨張緩和手段に電気的に接続して配置し、熱膨
張緩和手段を実装基板に電気的に接続して配置する。こ
れにより、熱膨張緩和手段がＩＣチップと実装基板の熱
膨張率の差によるストレスを吸収するとともに、従来必
要であった樹脂の充填や封入が不要である。本発明で
は、好ましくはＩＣチップは、ベアーチップであり、熱
膨張緩和手段に対して、熱圧着で電気的に接続する。According to the above construction, in the present invention, the IC chip is electrically connected to the thermal expansion reducing means, and the thermal expansion reducing means is electrically connected to the mounting board. As a result, the thermal expansion alleviating means absorbs the stress due to the difference in the thermal expansion coefficient between the IC chip and the mounting substrate, and the resin filling and encapsulation conventionally required are not necessary. In the present invention, the IC chip is preferably a bare chip and is electrically connected to the thermal expansion alleviating means by thermocompression bonding.
【０００８】[0008]
【実施例】以下、本発明の好適な実施例を添付図面に基
づいて詳細に説明する。なお、以下に述べる実施例は、
本発明の好適な具体例であるから、技術的に好ましい種
々の限定が付されているが、本発明の範囲は、以下の説
明において特に本発明を限定する旨の記載がない限り、
これらの態様に限られるものではない。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will be described in detail below with reference to the accompanying drawings. The examples described below are
Since it is a preferred specific example of the present invention, various technically preferable limitations are attached, but the scope of the present invention is, unless otherwise stated to limit the present invention, in the following description.
It is not limited to these modes.
【０００９】図１は、本発明のＩＣチップの配置方法の
一例を示す図である。図１において、ベアーチップ（ベ
アーＩＣチップともいう）５の表面５ｂ（図１では、下
面）には、複数のパッドが所定のレイアウトで配置され
ている。これに対して、ポリイミド両面基板７の一方の
面７ｃ（図１では上面）には、ベアーチップ５のパッド
が所定のレイアウトに一対一になるように、複数のパッ
ドが配置されている。しかも、ベアーチップ５の表面に
は、後にポリイミド両面基板７に対して電気的に接続す
るために、ベアーチップ５の複数のパッドには、ＢＬＭ
等の表面処理を行っておき、必要ならばはんだ等によっ
てバンプを形成しておく。このＢＬＭの表面処理とは、
ボール・リミテッド・メタルであり、ベアーチップ５の
Ａｌ電極に対してたとえば金、ニッケルＮｉ、銅の合金
を形成する表面処理である。このようにＢＬＭの表面処
理は、Ａｌ上にバンプんを形成する際に必要となる手段
であり、Ａｌ−はんだの接合が本来不可能なために行わ
れる。一例として、図１には、ベアーチップ５の表面の
１つのパッド５ａを示している。これに対して、ポリイ
ミド両面基板７の一方の面７ｃのパッド７ａを示してい
る。このパッド７ａはベアーチップ５のパッド５ａに対
応した位置に形成されている。FIG. 1 is a diagram showing an example of an IC chip arranging method according to the present invention. In FIG. 1, a plurality of pads are arranged in a predetermined layout on a surface 5b (a lower surface in FIG. 1) of a bare chip (also referred to as a bare IC chip) 5. On the other hand, a plurality of pads are arranged on one surface 7c (upper surface in FIG. 1) of the polyimide double-sided substrate 7 so that the pads of the bare chip 5 have a one-to-one correspondence with a predetermined layout. Moreover, on the surface of the bare chip 5, in order to electrically connect to the polyimide double-sided substrate 7 later, the plurality of pads of the bare chip 5 have BLMs.
Surface treatment such as is performed, and bumps are formed by soldering or the like if necessary. What is this BLM surface treatment?
It is a ball limited metal, and is a surface treatment for forming an alloy of gold, nickel Ni, and copper on the Al electrode of the bare chip 5. As described above, the surface treatment of BLM is a means necessary for forming bumps on Al, and is performed because Al-solder bonding is essentially impossible. As an example, FIG. 1 shows one pad 5 a on the surface of the bare chip 5. On the other hand, the pad 7a on one surface 7c of the polyimide double-sided substrate 7 is shown. The pad 7a is formed at a position corresponding to the pad 5a of the bare chip 5.
【００１０】ポリイミド両面基板７の他方の面７ｂに
は、接続部が、実装基板９の配線レイアウトに対応して
形成する。一例として、図１には、ポリイミド両面基板
７の他方の面７ｂには、バンプともいう電気的接続部８
が形成されている。この接続部８は、実装基板９の配線
レイアウトに対応する。このようにポリイミド両面基板
７の一方の面７ｃにはパッド７ａが形成されており、ポ
リイミド両面基板７の他方の面７ｂには接続部８が形成
されている。これらパッド７ａと接続部８は、結線部７
ｄ，７ｅ，７ｆを介して電気的に接続されている。結線
部７ｅは、ポリイミド両面基板７のスルーホール７ｇに
配置されている。結線部７ｅは、たとえばはんだを用い
ることができる。On the other surface 7b of the polyimide double-sided board 7, a connecting portion is formed corresponding to the wiring layout of the mounting board 9. As an example, in FIG. 1, an electrical connection portion 8 also called a bump is formed on the other surface 7 b of the polyimide double-sided substrate 7.
Are formed. The connection portion 8 corresponds to the wiring layout of the mounting board 9. Thus, the pad 7a is formed on one surface 7c of the polyimide double-sided substrate 7, and the connection portion 8 is formed on the other surface 7b of the polyimide double-sided substrate 7. The pad 7a and the connecting portion 8 are connected to each other by the connecting portion 7
It is electrically connected via d, 7e, and 7f. The connection portion 7e is arranged in the through hole 7g of the polyimide double-sided substrate 7. For the connection portion 7e, for example, solder can be used.
【００１１】次に、図１のＩＣチップの配置方法につい
て説明する。ベアーチップ５のパッド５ａをポリイミド
両面基板７のパッド７ａに対応して配置して、たとえば
超音波溶着等の方法を用いてはんだ層からなる接続部６
を形成する。この際には、ベアーチップ５のパッド５ａ
とポリイミド両面基板７のパッド７ａを正しく位置決め
して、接続部６を介して超音波溶着又は熱圧着等で接合
する。なお、上述の要領でウエハーに多数搭載されたベ
アーチップ５とポリイミド基板を接合させた後に、多数
のベアーチップに対応するウェハーの部分をそれぞれカ
ットすることは可能である。Next, a method of arranging the IC chips of FIG. 1 will be described. The pad 5a of the bear chip 5 is arranged corresponding to the pad 7a of the polyimide double-sided substrate 7, and the connecting portion 6 made of a solder layer is formed by using a method such as ultrasonic welding.
To form. At this time, the pad 5a of the bare chip 5
The pads 7a of the polyimide double-sided substrate 7 are correctly positioned, and they are joined by ultrasonic welding, thermocompression bonding, or the like via the connecting portion 6. After the bare chips 5 mounted on the wafer are bonded to the polyimide substrate as described above, it is possible to cut the wafer portions corresponding to the bare chips.
【００１２】次に、ポリアミド両面基板７の接続部８
を、実装基板９の対応する配線レイアウト（接続部分）
に対して、予め供給されたはんだ（たとえばクリームは
んだ等）によりマウントし、そしてはんだ付けを行う。
この一連の方法により、ベアーチップ５が、実装基板９
に対してマウントされかつはんだ付けされることにな
る。ところで、ベアーチップ５と実装基板９の熱膨張率
差によりストレスが生じた場合においても、この剛性の
低いポリイミド両面基板７が、接続部に発生する熱膨張
率の違いによるストレスを緩和し、長期的な電気的接続
の信頼性を確保することができる。このポリイミド両面
基板７におけるパッド７ａは、ベアーチップ５のパッド
５ａに対応して任意に配置することができる。しかも従
来必要であったベアーチップと実装基板の間に樹脂を封
入する工程を省くことができる。ところで、ベアーチッ
プのパッドの再配置とは、狭いピッチで配置されたパッ
ドの間隔を基板上に実装するのに容易な大きさにポリイ
ミド基板を利用して偏光することである。Next, the connecting portion 8 of the polyamide double-sided substrate 7
Is the wiring layout (connection portion) corresponding to the mounting board 9.
Is mounted with solder (for example, cream solder or the like) supplied in advance, and soldering is performed.
By this series of methods, the bare chip 5 is mounted on the mounting substrate 9
Will be mounted and soldered to. By the way, even when stress is generated due to the difference in thermal expansion coefficient between the bare chip 5 and the mounting substrate 9, this low-rigidity polyimide double-sided substrate 7 relieves stress due to the difference in thermal expansion coefficient generated at the connection portion, and It is possible to secure the reliability of the electrical connection. The pads 7a on the polyimide double-sided substrate 7 can be arbitrarily arranged corresponding to the pads 5a on the bare chip 5. Moreover, it is possible to omit the step of encapsulating the resin between the bare chip and the mounting board, which has been conventionally required. By the way, the rearrangement of the pads of the bare chip is to use the polyimide substrate for polarization so that the intervals of the pads arranged at a narrow pitch can be easily mounted on the substrate.
【００１３】ところで本発明は上記実施例に限定されな
い。上述した実施例ではポリイミド両面基板を熱膨張緩
和手段として用いているが、これに限らずポリイミド多
層基板を用いても良いし、他の種類の材質を用いても良
い。熱膨張緩和手段としては、たとえば剛性の低い材料
で耐熱性を備える材料、例えばシリコンラバー、フッ素
樹脂のような種類の材質の基板を用いても勿論構わな
い。The present invention is not limited to the above embodiment. Although the polyimide double-sided board is used as the thermal expansion alleviating means in the above-described embodiments, the invention is not limited to this, and a polyimide multi-layer board may be used, or another type of material may be used. As the thermal expansion reducing means, for example, a substrate made of a material having low rigidity and heat resistance, for example, a substrate made of a material such as silicon rubber or fluororesin may be used.
【００１４】[0014]
【発明の効果】以上説明したように本発明によれば、ベ
アチップのようなＩＣチップと実装基板の間の熱膨張率
の差によるストレスを緩和して長期的な電気的接続の信
頼性を確保することができると共に、樹脂の封入工程を
省くことができる。As described above, according to the present invention, stress due to a difference in coefficient of thermal expansion between an IC chip such as a bare chip and a mounting substrate is relieved to secure long-term reliability of electrical connection. In addition, it is possible to omit the resin encapsulation step.
【図１】本発明のＩＣチップの配置方法の一例を示す
図。FIG. 1 is a diagram showing an example of an IC chip arrangement method of the present invention.
【図２】従来のＩＣチップの配置方法を示す図。FIG. 2 is a diagram showing a conventional IC chip arranging method.
５ ベアーチップ（ＩＣチップ） ５ａ，７ａ パッド ６ 接続部 ７ ポリイミド両面基板（熱膨張緩和手段） ８ 接続部（バンプ） ９ 実装基板 5 Bear Chip (IC Chip) 5a, 7a Pad 6 Connection Part 7 Polyimide Double-sided Board (Thermal Expansion Relief Means) 8 Connection Part (Bump) 9 Mounting Board
Claims (4)
接続して配置し、 前記熱膨張緩和手段を実装基板に電気的に接続して配置
することを特徴とするＩＣチップの配置方法。1. A method of arranging an IC chip, characterized in that an IC chip is electrically connected to a thermal expansion relaxation means and arranged, and the thermal expansion relaxation means is electrically connected to a mounting board.
り、前記熱膨張緩和手段に対して、熱圧着で電気的に接
続する請求項１に記載のＩＣチップの配置方法。2. The method of arranging an IC chip according to claim 1, wherein the IC chip is a bare chip and is electrically connected to the thermal expansion alleviating means by thermocompression bonding.
対して、はんだ付けにより電気的に接続する請求項２に
記載のＩＣチップの配置方法。3. The IC chip arranging method according to claim 2, wherein the thermal expansion alleviating means is electrically connected to the mounting substrate by soldering.
基板またはポリイミド多層基板である請求項３に記載の
ＩＣチップの配置方法。4. The method of arranging an IC chip according to claim 3, wherein the thermal expansion alleviating means is a polyimide double-sided board or a polyimide multilayer board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6334519A JPH08172112A (en) | 1994-12-19 | 1994-12-19 | Disposition method for ic chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6334519A JPH08172112A (en) | 1994-12-19 | 1994-12-19 | Disposition method for ic chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH08172112A true JPH08172112A (en) | 1996-07-02 |
Family
ID=18278317
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6334519A Pending JPH08172112A (en) | 1994-12-19 | 1994-12-19 | Disposition method for ic chip |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH08172112A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR19980070331A (en) * | 1997-01-02 | 1998-10-26 | 추후보충 | Cantilever Ball Connections for Integrated Circuit Chip Packages |
| US6323542B1 (en) | 1997-01-17 | 2001-11-27 | Seiko Epson Corporation | Electronic component, semiconductor device, methods of manufacturing the same, circuit board, and electronic instrument |
-
1994
- 1994-12-19 JP JP6334519A patent/JPH08172112A/en active Pending
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR19980070331A (en) * | 1997-01-02 | 1998-10-26 | 추후보충 | Cantilever Ball Connections for Integrated Circuit Chip Packages |
| US6323542B1 (en) | 1997-01-17 | 2001-11-27 | Seiko Epson Corporation | Electronic component, semiconductor device, methods of manufacturing the same, circuit board, and electronic instrument |
| US6518651B2 (en) | 1997-01-17 | 2003-02-11 | Seiko Epson Corporation | Electronic component, semiconductor device, methods of manufacturing the same, circuit board, and electronic instrument |
| US7235881B2 (en) | 1997-01-17 | 2007-06-26 | Seiko Epson Corporation | Electronic component, semiconductor device, methods of manufacturing the same, circuit board, and electronic instrument |
| US7307351B2 (en) | 1997-01-17 | 2007-12-11 | Seiko Epson Corporation | Electronic component, semiconductor device, methods of manufacturing the same, circuit board, and electronic instrument |
| US7485973B2 (en) | 1997-01-17 | 2009-02-03 | Seiko Epson Corporation | Electronic component, semiconductor device, methods of manufacturing the same, circuit board, and electronic instrument |
| US7755205B2 (en) | 1997-01-17 | 2010-07-13 | Seiko Epson Corporation | Electronic component, semiconductor device, methods of manufacturing the same, circuit board, and electronic instrument |
| US7888177B2 (en) | 1997-01-17 | 2011-02-15 | Seiko Epson Corporation | Electronic component, semiconductor device, methods of manufacturing the same, circuit board, and electronic instrument |
| US8399999B2 (en) | 1997-01-17 | 2013-03-19 | Seiko Epson Corporation | Electronic component, semiconductor device, methods of manufacturing the same, circuit board, and electronic instrument |
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