JPH08139328A - Semiconductor device manufacturing method - Google Patents

Abstract

PURPOSE: To provide a method of manufacturing a semiconductor device having an LDD structure, reducing the number of photolithographic steps and number of ion implantation steps. CONSTITUTION: On a glass substrate 31 a poly-Si film 32 is formed on which a first mask 33A is patterned. On this mask a second or third mask 34 or 35 is formed to form a mask region for ion implantation into lightly doped regions and for ion implantation at a low concn. into a lightly doped forming region. When ion implantation is made under a high concn. condition, for example, a p-type heavily doped region 32A and p-type lightly doped region 32B can be formed en bloc to permit the number of steps to be reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to an LDD (Light-ly Doped D
The present invention relates to a method of manufacturing a MOS transistor having a rain structure.

[0002]

2. Description of the Related Art In recent years, TFT (Thin Film Transistor:
The progress of active matrix liquid crystal displays using thin film transistors (TFTs) is remarkable, and higher resolution and higher quality are demanded. In order to meet these demands, it is necessary to miniaturize pixels and TFTs. When the size of a MOS transistor such as TFT is reduced, the electric field,
In particular, the electric field strength near the drain becomes extremely large.
In such a high electric field, hot carriers are generated,
A short channel effect such as variation of the threshold voltage Vth is brought about, deterioration of transistor element characteristics,
This has a significant effect on device reliability, such as a reduction in source / drain breakdown voltage. As a measure against such a problem, an LDD structure is adopted for a MOS transistor.

FIG. 7 shows a cross section of a MOS transistor having an LDD structure formed on a glass substrate 1. The polysilicon layer 2 is formed on the glass substrate 1,
In this polysilicon layer 2, high-concentration impurity regions 2A and 2A as source / drain and low-concentration impurity regions (LDD regions) 2B and 2B are formed. A gate electrode 4 is formed on the polysilicon layer 2 with a gate insulating film 3 interposed therebetween. Further, the high concentration impurity regions 2A, 2A
Source / drain electrodes 6, 6 are connected to each of these via contact holes formed in the gate insulating film 3 and the insulating film 5.

FIG. 8 shows a pMO having an LDD structure.
A cross section in which a CMOS including an S transistor and an nMOS transistor is formed on the glass substrate 1 is shown. In this CMOS, source / drain regions 14 in which p-type impurities are introduced so as to have a high concentration distribution are formed in the polysilicon layer 7 on the pMOS transistor side, and the p-type is formed inside each of the source / drain regions 14. LDD region (low concentration impurity region) 10A is formed. Similarly, in the polysilicon layer 7 on the nMOS transistor side, source / drain regions 16 are formed in which n-type impurities are introduced so as to have a high concentration distribution, and the n-type impurities are formed inside the source / drain regions 16. LDD region 1
2A is formed. The drain regions of both pMOS and nMOS transistors are connected by a common drain electrode 17. In the figure, 18 is a gate insulating film, 19 is a gate electrode, 20 is an insulating film, and 21 is a source electrode.

Next, a conventional CMOS manufacturing method is shown in FIG.
This will be described with reference to (A), (B) and FIGS. 10 (A), (B). First, as shown in FIG. 9A, the glass substrate 1
A non-doped polysilicon layer 7 by a well-known method.
Then, a cap insulating film 8 is formed on the polysilicon layer 7. Next, a photoresist 9 is patterned on the cap insulating film 8. This photoresist 9
The pattern is such that only the high-concentration impurity region to be formed in the pMOS transistor formation region and the cap insulating film 8 on the LDD region are exposed. Boron (B) is ion-implanted under low concentration conditions using the photoresist 9 as a mask to form p-type low-concentration impurity regions 10 and 10 in the polysilicon layer 7 (first ion implantation step).

After that, the above-mentioned photoresist 9 is peeled off, a new photoresist 11 is applied, and a pattern as shown in FIG. 9B is formed by using a lithography technique. The pattern of the photoresist 11 has an inverse relationship with the pattern of the photoresist 9 described above.
Only the high-concentration impurity region to be formed in the formation region of the OS transistor and the cap insulating film 8 on the LDD region are exposed. Then, for example, phosphorus (P) is ion-implanted under a low concentration condition by using the photoresist 11 as a mask, and the n-type low concentration impurity region 1 is formed in the polysilicon layer 7.
2 and 12 are formed (second ion implantation step).

Next, the photoresist 11 described above is peeled off, and the photoresist 13 is newly patterned as shown in FIG. The pattern of the photoresist 13 is formed to expose only the cap insulating film 8 on the high concentration impurity region to be formed in the pMOS transistor formation region. Then, using the photoresist 13 as a mask, boron is ion-implanted under a high concentration condition,
A p-type high concentration impurity region 14 is formed in the polysilicon layer 7 (third ion implantation step). As a result of the formation of the high-concentration impurity region 14, the low-concentration impurity region 10 having a narrowed region becomes the LDD region 10A.

Further, the photoresist 13 described above is peeled off, and the photoresist 15 is newly patterned as shown in FIG. This photoresist 15
The pattern is such that only the cap insulating film 8 on the high concentration impurity region to be formed in the nMOS transistor formation region is exposed. And this photoresist 15
Is used as a mask, and, for example, phosphorus is ion-implanted under high-concentration conditions to form an n-type high-concentration impurity region 16 in the polysilicon layer 7.
Are formed (fourth ion implantation step). Also in this case,
As a result of the formation of the high-concentration impurity region 16, the low-concentration impurity region 12 having a narrowed region becomes the LDD region 12A. After each impurity region is formed in the polysilicon layer 7 in this manner, element isolation, gate insulating film formation, gate electrode formation, insulating film deposition, contact hole window formation, source / drain electrode formation, etc. Then, the CMOS device is completed.

[0009]

However, in the above-described CMOS manufacturing method, the photolithography process and the ion implantation process are required four times each, and a cleaning process, a rinsing process, etc. are performed after each photolithography process. Since the processing steps are involved, there is a problem that the process becomes complicated. In the case of manufacturing the MOS transistor shown in FIG. 7, the ion implantation step for LDD and the high concentration ion implantation step were also required twice. The problem of increasing the number of steps is not limited to the TFT, and is the same when the MOS transistor is formed in single crystal silicon or the like. The problem to be solved by this invention is
In manufacturing a semiconductor device having an LDD structure, what means should be taken to reduce the number of photolithography processes and the number of ion implantation processes.

[0010]

Therefore, according to the invention of claim 1, a first mask for reducing the amount of impurity ions passing by ion implantation under a high concentration condition is formed on the semiconductor layer on the semiconductor layer. The step of forming so as to cover the channel region and the low-concentration impurity region to be formed, and the step of forming a second mask on the first mask, the second mask having a portion narrower in the gate length direction than the first mask, The solution is to provide a step of forming the upper surface of the mask so that both ends in the gate length direction are exposed, and a step of performing ion implantation under high concentration conditions on the entire surface thereafter. The invention according to claim 2 is characterized in that the semiconductor layer is formed on a glass substrate. Further, the invention according to claim 3 is characterized in that the first mask is a silicon oxide film or a silicon nitride film. The invention according to claim 4 is characterized in that the second mask is made of a photoresist. The invention according to claim 5 is characterized in that the semiconductor layer is a polysilicon thin film.

According to a sixth aspect of the present invention, the first conductive type MOS transistor of the semiconductor layer is provided on the semiconductor layer with a first mask for reducing the passage amount of impurity ions due to ion implantation under high concentration conditions. A channel region and a low concentration impurity region to be formed in the formation region, and a second conductivity type MOS
Forming a channel region and a low-concentration impurity region to be formed in the transistor formation region, covering the second conductivity type MOS transistor formation region, and forming the first conductivity type MOS transistor A second mask consisting of a portion formed on the first mask formed on the region, a portion formed on the first mask of the first conductivity type MOS transistor forming region,
A step of forming a width narrower in the gate length direction than the first mask and exposing both ends of the upper surface of the first mask in the gate length direction, and thereafter, impurity ions of the first conductivity type under a high concentration condition. A step of implanting ions, a portion covering the first conductivity type MOS transistor formation region, and a second portion
A third mask consisting of a portion formed on the first mask formed on the conductive type MOS transistor formation region is formed on the first mask of the second conductive type MOS transistor formation region. Forming a portion having a width in the gate length direction narrower than that of the first mask and exposing both ends of the upper surface of the first mask in the gate length direction;
After that, a step of implanting second conductivity type impurity ions under a high concentration condition is provided as a solving means. The invention according to claim 7 is the first conductivity type M.
One of the OS transistor and the second conductivity type MOS transistor is n-type and the other is p-type. Further, the invention according to claim 8 is characterized in that the first mask is a silicon oxide film or a silicon nitride film. The invention according to claim 9 is characterized in that the second mask and the third mask are photoresists. The invention according to claim 10 is characterized in that the semiconductor layer is a polysilicon thin film.

[0012]

According to the first aspect of the invention, the first mask covers the channel region and the low-concentration impurity region (LDD region) to be formed in the semiconductor layer, and the second mask covers the first mask and the first mask. It is formed so that both ends of the mask in the gate length direction are exposed. Further, since the first mask has a function of reducing the amount of impurity ions passing by ion implantation under a high concentration condition, ions which are not covered by the second mask and which are incident from both end portions of the upper surface in the gate length direction are:
All ions cannot reach the underlying semiconductor layer.
Therefore, the underlying semiconductor layer portions at both ends in the gate length direction which are not covered with the second mask of the first mask become low-concentration impurity introduction regions, that is, LDD regions. Further, the surface of the semiconductor layer portion which is not covered with the first mask and the second mask is exposed, and a high-concentration impurity region, that is, a source / drain region is formed by direct incidence of a beam on this portion. The low-concentration impurity region and the high-concentration impurity region described above can be formed in a self-aligned manner with respect to the first mask, and thus are formed adjacent to each other. Further, the channel region formed by being sandwiched by the low-concentration impurity regions is the second
The mask can be formed in a self-aligned manner. Therefore, the LDD structure capable of relaxing the electric field strength near the drain in the low concentration impurity region can be formed by one-time ion implantation.

Further, in the inventions according to claims 2 to 5, the semiconductor layer is formed on the glass substrate, so that the low concentration impurity region (LDD region) of the TFT formed in the liquid crystal display panel has a high concentration. It can be formed at the same time as the impurity region, and the number of steps can be reduced. When the first mask is formed of a silicon oxide film or a silicon nitride film, by controlling the film thickness of these films,
It is possible to set the dose amount to the low concentration impurity region during the ion implantation under the high concentration condition. Further, since these films have a light-transmitting property, the second mask made of a photoresist can be patterned in a so-called bottom gate in a self-aligned manner by a backside exposure technique when manufacturing a reverse stagger type TFT. it can.

According to the sixth aspect of the present invention, when the second mask is formed on the first mask and the first conductivity type impurity is ion-implanted under a high concentration condition, the gate of the first mask is formed. Since both ends in the longitudinal direction are exposed, the first-conductivity-type low-concentration impurity regions are formed in the base semiconductor layer portions at the both ends, and the exposed first-conductivity-type high-concentration impurity regions are formed. Concentrated impurity regions are formed at the same time. Similarly,
When the third mask is formed on the first mask and ion implantation of the second conductivity type impurity is performed under a high concentration condition, both ends of the first mask in the gate length direction are exposed.
Second-conductivity-type low-concentration impurity regions are formed in the underlying semiconductor layer portions at both ends, and second-conductivity-type high-concentration impurity regions are simultaneously formed in the exposed semiconductor layer portions. In this way, a semiconductor device including two types of transistors can be formed by performing the ion implantation process only twice.

Further, in the inventions of claims 7 to 10, by using an n-type MOS and a p-type MOS, a T forming a CMOS formed in the liquid crystal display panel is formed.
The low concentration impurity region (LDD region) of the FT can be formed at the same time as the high concentration impurity region, and the number of steps of the liquid crystal process can be reduced. When the first mask is formed of a silicon oxide film or a silicon nitride film,
By controlling these film thicknesses, it becomes possible to set the dose amount to the low concentration impurity region at the time of ion implantation under the high concentration condition.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The details of the method for manufacturing a semiconductor device according to the present invention will be described below with reference to embodiments. (Embodiment 1) FIGS. 1 to 3 are process sectional views showing Embodiment 1 of the present invention. In this embodiment, the CMOS is mounted on the glass substrate.
This is an example in which the present invention is applied to the case where a polysilicon TFT constituting the above is formed. First, in this embodiment, FIG.
As shown in (A), an amorphous silicon film (not shown) is deposited on the glass substrate 31 to have a film thickness of 500 Å, for example. Then, this amorphous silicon film is subjected to laser annealing to change into a polysilicon film 32 as a semiconductor layer. Then, a mask material film 33 made of, for example, SiO ₂ is deposited on the polysilicon film 32 to have a film thickness of, for example, 200 Å. The film thickness of the mask material film 33 is set according to the condition of ion implantation under a high concentration condition to be performed later, especially according to the acceleration voltage. That is, the density of the ion beam passing through the mask material film 33 (the number of ion beams per unit area) is set to a predetermined value,
The film thickness of the mask material film is determined in consideration of the acceleration voltage.

Next, a first mask is formed. That is,
The mask material film 33 is patterned using a lithography technique and an etching technique as shown in FIG. 1B to form a first mask 33A. This first mask 33A
As shown in the figure, the pattern (1) exposes the p-type MOS transistor formation region as the first conductivity type and the n-type MOS transistor formation region as the second conductivity type. The p-type long mask portion 33 is formed so as to cover the setting positions of a channel region and a low concentration impurity region, which will be described later, which should be formed in the pMOS transistor formation region.
B is also formed, and the n-type long mask portion 33C is formed at a position to cover a channel region and a low-concentration impurity region described later, which should be formed in the nMOS transistor formation region.
Is also formed. Of the first mask 33A, the portion of the mask material film other than the p-type long mask portion 33B and the n-type long mask portion 33C is designed to cover the portion where the MOS transistor is not formed. .

Next, as shown in FIG. 2A, the photoresist 34 as the second mask is patterned. Specifically, first, a photoresist 34 is applied on the entire surface, and exposure and development are performed. The pattern of the photoresist 34 covers the area other than the pMOS transistor formation area, but the p-type long mask portion 33B of the first mask 33A in the pMOS transistor formation area is also covered with the p-type area. It is designed to have a width in the gate length direction narrower than that of the long mask portion 33B and to have a p-type short mask portion 34A that exposes both ends in the gate length direction of the upper surface of the p-type long mask portion 33B. The width of the p-type short mask portion 34A is set to be the same as the channel length of the pMOS transistor, and the p-type short mask portion 34A is provided above the design position of the channel region described later.
A is set to be offset.

After patterning the photoresist 34 as the second mask in this way, as shown in FIG. 2A, the p-type impurity as the first conductivity type impurity, that is, boron (B) is accelerated, for example. Ion implantation is performed under the conditions of a voltage of 10 keV and a dose amount of about 2E15 (2 × 10 15 / cm ² ). As a result, as shown in FIG.
In the polysilicon film 32 in the OS transistor formation region, p
The high-concentration type impurity regions 32A and 32A and the low-concentration p-type impurity regions 32B and 32B are formed simultaneously. The p-type high-concentration impurity region 32A is formed in the polysilicon film 32 portion located outside the p-type long mask portion 33B in the gate length direction. The p-type low-concentration impurity region 32B is formed in the polysilicon film 32 portion located below the portion where the p-type long mask 33B is not covered with the p-type short mask portion 34A. The polysilicon film 32 portion sandwiched between the p-type low-concentration impurity regions 32B becomes the channel region 32C of the pMOS transistor. The dose amount of the p-type low-concentration impurity amount 32B is 1E14 (1 × 10 14 / cm ²⁾ because the number of ion beams passing through the p-type long mask portion 33B of the first mask 33A is limited. )
About. In this way, the p-type high-concentration impurity region 32A serving as the source / drain and the p-type low-concentration impurity region 32B serving as the LDD region can be simultaneously formed in the pMOS transistor formation region by one ion implantation.

Then, the photoresist 34 is peeled off, and a new photoresist 35 as a third mask is patterned as shown in FIG. Specifically, similarly to the patterning of the photoresist 34 described above, first, the photoresist 35 is first coated on the entire surface, and exposed and developed. The pattern of the photoresist 35 covers the area other than the nMOS transistor forming area, but the first mask 33 in the nMOS transistor forming area is formed.
Also on the n-type long mask portion 33C of A, the width in the gate length direction is narrower than that of the n-type long mask portion 33C, and both ends of the upper surface of the n-type long mask portion 33C in the gate length direction are exposed. It is designed to have an n-type short mask portion 35A. The width of the n-type short mask portion 35A is set to be the same as the channel length of the nMOS transistor, and is set to cover the n-type short mask portion 35A above the design position of the channel region described later. There is.

After patterning the photoresist 35 as the third mask in this way, as shown in FIG. 2B, an n-type impurity as the second conductivity type impurity, phosphorus (P) in this embodiment, is added. For example, the ion implantation is performed under the condition that the acceleration voltage is 10 keV and the dose amount is about 2E15 (2 × 10 15 / cm ² ). As a result, as shown in FIG.
In the polysilicon film 32 in the MOS transistor formation region,
The n-type high concentration impurity regions 32D and 32D and the n-type low concentration impurity regions 32E and 32E are simultaneously formed. The n-type high-concentration impurity region 32D includes the n-type long mask portion 33C.
Is formed in the portion of the polysilicon film 32 located outside the gate length direction. The n-type low-concentration impurity region 32E is formed in the polysilicon film 32 portion located below the portion where the n-type long mask 33C is not covered with the n-type short mask portion 35A. The polysilicon film 32 portion sandwiched between the n-type low-concentration impurity regions 32E becomes the channel region 32F of the nMOS transistor. The dose amount to the n-type low-concentration impurity region 32E is n of the first mask 33.
Since the number of ion beams passing through the die long mask portion 33C is limited, 1E14 (1 × 10 14 / c
m ² ). In this way, the n-type high-concentration impurity region 32D which is the source / drain and the n-type low-concentration impurity region 32E which is the LDD region can be simultaneously formed in the nMOS transistor formation region by one ion implantation.

Next, after the photoresist 35 is removed, the first mask 33A is used as the underlying polysilicon film 32.
And is removed by using a well-known etching technique with which a sufficient selection ratio can be obtained. Thereafter, as shown in FIG. 3A, after element isolation, a gate insulating film 36 made of SiO ₂ or the like is deposited on the entire surface. Next, the gate electrode 37 is patterned on the gate insulating film 36 at a predetermined position in each MOS transistor formation region. Further, as shown in FIG. 3B, a passivation film 3 such as PSG is formed on the entire surface.
8 is deposited, and the source electrode 39 and the common drain electrode 40 are deposited.
A semiconductor device that constitutes a CMOS is completed by making contacts such as.

In the present embodiment, since the high-concentration impurity region and the low-concentration impurity region of each conductivity type MOS transistor can be collectively ion-implanted, the impurity diffusion region of the semiconductor device forming the CMOS can be two. It is possible to reduce the number of ion implantation steps. Along with this, the photolithography process and the like can be reduced, and the manufacturing process of the semiconductor device can be greatly simplified. If a silicon-based thin film having a good controllability of film thickness is used as the first mask, the dose amount of the low concentration impurity region can be adjusted to an appropriate value.

Although the present invention is applied to the semiconductor device which constitutes the CMOS in the present embodiment, it goes without saying that the number of steps can be reduced even when a MOS transistor is simply manufactured. Further, although the polysilicon film is used as the semiconductor layer in the above embodiment, it is also possible to use, for example, an amorphous silicon thin film or a single crystal silicon substrate. Further, in this embodiment, the silicon oxide film is used as the mask material film, but a silicon nitride film may be used. The silicon oxide film is made of C as in this embodiment.
Besides the deposited film by VD, a thermal oxide film may be used.

(Embodiment 2) FIGS. 4 to 6 are process sectional views showing Embodiment 2 of the present invention. This embodiment is a polysilicon TF having a structure having a so-called bottom gate on a glass substrate.
This is an example in which the present invention is applied to the manufacture of a CMOS configured by T. First, as shown in FIG. 4A, the gate electrode 42 is formed at a predetermined position in each MOS transistor formation region on the glass substrate 41. After that, a gate insulating film 43 made of, for example, SiO ₂ is deposited on the entire surface to a predetermined thickness. next,
After depositing an amorphous silicon film (not shown) on the gate insulating film 43, the amorphous silicon film is annealed such as laser irradiation to be changed into a polysilicon film 44. Then, the polysilicon film 4
A mask material film 45 made of, for example, SiO ₂ is deposited on the substrate 4.

Subsequently, as shown in FIG. 4B, the mask material film 45 is patterned to form a first mask 45.
Form A. The pattern of the first mask 45A is the p-type MOS as the first conductivity type, as in the first embodiment.
Although the inside of the transistor formation region and the inside of the n-type MOS transistor formation region of the second conductivity type are exposed, they should be formed within the pMOS transistor formation region,
The p-type long mask portion 45B is also formed so as to cover the setting positions of the channel region and the low-concentration impurity region, which will be described later, and also covers the channel region and the low-concentration impurity region, which will be described later, to be formed in the nMOS transistor formation region. Thus, the n-type long mask portion 45C is also formed. Of the first mask 45A, the long mask portion 45 for p-type
A portion other than B and the long mask portion 45C for n-type, which is made of the mask material film 45, is designed to cover a portion where the MOS transistor is not formed. Also in this embodiment, the film thickness of the mask material film 45 is set according to the condition of ion implantation under a high concentration condition to be performed later, particularly according to the acceleration voltage. That is, the film thickness of the mask material film is determined in consideration of the acceleration voltage so that the density of ion beams passing through the mask material film 45 (the number of ion beams per unit area) becomes a predetermined value.

Next, as shown in FIG. 5A, a photoresist 46 is applied on the entire surface, and as shown in FIG. 5B, patterning is performed so that the photoresist 46 serves as a second mask. The pattern of the photoresist 46 is intended to cover the area other than the pMOS transistor formation region as in the case of the first embodiment.
Also on the p-type long mask portion 45B of the first mask 45A in the transistor formation region, the width in the gate length direction is narrower than the p-type long mask portion 45B, and the gate on the upper surface of the p-type long mask portion 45B is formed. It is designed to have a p-type short mask portion 46A that exposes both ends in the long direction. Incidentally, this p-type short mask portion 46A
Is set to be the same as the channel length of the pMOS transistor, and is set to cover the p-type short mask portion 46A above the design position of the channel region described later.

After patterning the photoresist 46 as the second mask in this manner, as shown in FIG. 5B, the p-type impurity as the first conductivity type impurity, that is, boron (B) is accelerated, for example. Ion implantation is performed under the conditions of a voltage of 10 keV and a dose amount of about 2E15 (2 × 10 15 / cm 2). As a result, as shown in FIG.
In the polysilicon film 44 in the OS transistor formation region, p
High-concentration type impurity regions 44A and 44A and low-concentration p-type impurity regions 44B and 44B are formed. The p-type high-concentration impurity region 44A is formed in the polysilicon film 44 portion located outside the p-type long mask portion 45B in the gate length direction. The p-type low-concentration impurity region 44B is formed in the polysilicon film 44 portion located below the portion where the p-type long mask 45B is not covered with the p-type short mask portion 46A. The polysilicon film 44 portion sandwiched between the p-type low-concentration impurity regions 44B becomes the channel region 44C of the pMOS transistor. The dose amount of the p-type low concentration impurity amount 44B becomes 1E14 (1 × 10 14 / cm ²⁾ because the number of ion beams passing through the p-type long mask portion 45B of the first mask 45A is limited. ) It will be about. In this manner, the p-type high-concentration impurity region 4 serving as the source / drain is formed in the pMOS transistor formation region.
4A and a p-type low concentration impurity region 44B which is an LDD region
And can be simultaneously formed by one ion implantation.

After that, the photoresist 46 is peeled off, and a new photoresist 47 as a third mask is patterned as shown in FIG. 6 (A). The pattern of the photoresist 47 covers the area other than the nMOS transistor forming area. However, the pattern for the n type is also formed on the n type long mask portion 45C of the first mask 45A in the nMOS transistor forming area. It is designed to have a width in the gate length direction narrower than that of the long mask portion 45C and to have an n-type short mask portion 47A exposing both ends in the gate length direction of the upper surface of the n-type long mask portion 45C. The width of the n-type short mask portion 47A is
It is set to the same as the channel length of the nMOS transistor,
The n-type short mask portion 47A is set to cover the design position of the channel region described later.

After patterning the photoresist 47 as the third mask in this manner, as shown in FIG. 6A, an n-type impurity as the second conductivity type impurity, phosphorus (P) in this embodiment, is added. For example, the ion implantation is performed under the conditions of an acceleration voltage of 10 keV and a dose of about 2E15 (2 × 10 15th power / cm 2). As a result, as shown in FIG.
In the polysilicon film 44 in the MOS transistor formation region,
N-type high concentration impurity regions 44D and 44D and n-type low concentration impurity regions 44E and 44E are formed. The n-type high-concentration impurity region 44D is formed in the portion of the polysilicon film 44 located outside the n-type long mask portion 45C in the gate length direction. The n-type low-concentration impurity region 44E is formed in the polysilicon film 44 portion located below the portion where the n-type long mask 45C is not covered with the n-type short mask portion 47A. Further, the portion of the polysilicon film 44 sandwiched between the n-type low-concentration impurity regions 44E becomes the channel region 44F of the nMOS transistor. The dose amount to the n-type low-concentration impurity region 44E is 1E14 (1 × 10 14 / cm 2) because the number of ion beams passing through the n-type long mask portion 45C of the first mask 45A is limited. It will be about. Thus, in the nMOS transistor formation region, the n-type high-concentration impurity region 44D which is the source / drain and the n-type low-concentration impurity region 4 which is the LDD region.
4E and 4E can be formed simultaneously by one ion implantation.

Next, after the photoresist 47 is removed, the first mask 45A is used as the underlying polysilicon film 44.
And is removed by using a well-known etching technique with which a sufficient selection ratio can be obtained. After that, as shown in FIG. 6B, an insulating film 48 made of, for example, SiO2 is deposited on the entire surface. Next, after performing a contact window opening process, contacts such as the source electrode 49 and the common drain electrode 50 are taken to complete a semiconductor device forming a CMOS. In this embodiment, since the polysilicon film 44 is not patterned for element isolation, the entire semiconductor device can be formed flat. Also in this embodiment, the number of manufacturing steps could be significantly reduced as in the first embodiment.

Although the first and second embodiments have been described above, the present invention is not limited to these.
Various design changes and material changes can be made based on the concept of the structure. For example, although phosphorus (P) is used as the n-type impurity in both of the above embodiments, arsenic (As) may be used. Further, although the semiconductor device is formed on the glass substrate in both of the above-mentioned embodiments, the point is that a MOS having an LDD structure is used.
The present invention can be applied to manufacturing of transistors in general. Furthermore, in both of the above embodiments, the first conductivity type is p
Although the type and the second conductivity type are n-type, of course, the p-type and the n-type may be reversed.

[0033]

As is apparent from the above description, according to the present invention, it is possible to reduce the number of photolithography steps and the number of ion implantation steps for manufacturing a semiconductor device having an LDD structure. Further, if a silicon-based thin film having a good controllability of film thickness is used as the first mask, the amount of impurities passing through the first mask can be set appropriately.
Therefore, there is an effect that the dose amount of the low concentration impurity region (LDD region) can be adjusted to an appropriate value. Furthermore, the use of the present invention has the effect of simplifying the manufacture of liquid crystal display panels.

[Brief description of drawings]

1A and 1B are process cross-sectional views of a first embodiment of the present invention.

2A and 2B are process cross-sectional views of Embodiment 1 of the present invention.

3A and 3B are process cross-sectional views of Embodiment 1 of the present invention.

4A and 4B are process cross-sectional views of a second embodiment of the present invention.

5A and 5B are process cross-sectional views of a second embodiment of the present invention.

6A and 6B are process sectional views of a second embodiment of the present invention.

FIG. 7 is a cross-sectional view of a thin film transistor having an LDD structure.

FIG. 8 is a cross-sectional view of a CMOS including a thin film transistor having an LDD structure.

9A and 9B are cross-sectional views showing a conventional CMOS manufacturing process.

10A and 10B are cross-sectional views showing a conventional CMOS manufacturing process.

[Explanation of symbols]

 31 glass substrate 32 polysilicon film 32A p type high concentration impurity region 32B p type low concentration impurity region 32C channel region 32D n type high concentration impurity region 32E n type low concentration impurity region 32F channel region 33 mask material film 33A first mask 33B Long mask portion for p-type 33C Long mask portion for n-type 34 Photoresist (second mask) 34A Short mask portion for p-type 35 Photoresist (third mask) 35A Short mask for n-type 36 Gate insulating film 37 Gate electrode

Claims (10)

[Claims] 1. A first mask, which reduces the amount of impurity ions passing by ion implantation under high concentration conditions, is formed on the semiconductor layer so as to cover a channel region and a low concentration impurity region to be formed in the semiconductor layer. Forming step, and forming a second mask on the first mask, the second mask having a portion whose width in the gate length direction is narrower than that of the first mask so that both ends of the upper surface of the first mask in the gate length direction are exposed. And a step of performing ion implantation under high-concentration conditions on the entire surface after that, a method of manufacturing a semiconductor device. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor layer is formed on a glass substrate. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the first mask is a silicon oxide film or a silicon nitride film. 4. The method of manufacturing a semiconductor device according to claim 1, wherein the second mask is a photoresist. 5. The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor layer is a polysilicon thin film. 6. A channel region in which a first mask for reducing the passage amount of impurity ions due to ion implantation under high-concentration conditions should be formed on a semiconductor layer in a MOS transistor formation region of the first conductivity type of the semiconductor layer. And a low-concentration impurity region, and a channel region and a low-concentration impurity region to be formed in the second-conductivity-type MOS transistor formation region, respectively, and forming the second-conductivity-type MOS transistor formation region. A second mask including a portion that covers and a portion that is formed on the first mask that is formed on the first-conductivity-type MOS transistor formation region is provided with a second mask of the first-conductivity-type MOS transistor formation region. A portion formed on one mask has a width in the gate length direction narrower than that of the first mask, and both ends of the upper surface of the first mask in the gate length direction are exposed. And a step of implanting first conductivity type impurity ions under a high concentration condition, a portion covering the first conductivity type MOS transistor formation region, and the second conductivity type MOS A third mask consisting of a portion formed on the first mask formed on the transistor formation region and a portion formed on the first mask of the second conductivity type MOS transistor formation region A step of forming the second mask so that the width in the gate length direction is narrower than that of the first mask and exposing both ends of the upper surface of the first mask in the gate length direction; And a step of implanting the semiconductor device. 7. The method of manufacturing a semiconductor device according to claim 6, wherein one of the first conductivity type MOS transistor and the second conductivity type MOS transistor is n-type and the other is p-type. 8. The method of manufacturing a semiconductor device according to claim 6, wherein the first mask is a silicon oxide film or a silicon nitride film. 9. The method of manufacturing a semiconductor device according to claim 6, wherein the second mask and the third mask are photoresists. 10. The method of manufacturing a semiconductor device according to claim 6, wherein the semiconductor layer is a polysilicon thin film.