JPH08139212A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE: To prevent increase of diffused layer resistance and parasitic junction capacitance by eliminating variation of width in the diffused layer resulting from positioning error. CONSTITUTION: After the diffused layers 16, 17 are formed by ion implantation from an aperture 12a of a Si3 N4 /SiO2 film 12, a part of the Si3 N4 /SiO2 film 12 is removed and a channel stop 14 is formed by the ion implantation utilizing this Si3 N4 /SiO2 film 12 as a mask. Therefore, any one of the boundary between the region where the diffused layers 16, 17 are not formed and the diffused layers 16, 17 and the boundary between the channel stop 14 and diffused layers 16, 17 is determined by the initial pattern of the Si3 N4 /SiO2 film 12.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device having a diffusion layer and a channel stop in an element isolation region.

[0002]

2. Description of the Related Art FIG. 7 shows an equivalent circuit of a memory cell array of a floating gate type nonvolatile semiconductor memory device. In this memory cell array, memory cells M ₁₁ ... Formed by transistors having floating gates are arranged in a matrix, and word lines W ₁ ... Which are gate electrodes of the transistors are arranged in the row direction. It is extended. Source lines S ₁ ... And bit lines B ₁ ... Connected to the sources and drains of the transistors extend in the column direction.

By the way, source lines S ₁ ... And bit lines B ₁ ...
The structure in which the source lines S ₁ ... And the bit lines B ₁ ... Are formed by diffusion layers in the element isolation regions as shown in FIG. Is being considered.

FIG. 9 shows a conventional example of a method of manufacturing a floating gate type nonvolatile semiconductor memory device having such a structure. In this conventional example, as shown in FIG.
A Si ₃ N ₄ / SiO ₂ film 12 having a film thickness of 100/5 nm and having an opening 12a on a region where a channel stop is to be formed is patterned on a Si substrate 11 of a mold.

Then, from the opening 12a to the Si substrate 11, p
Si ₃ N ₄ / SiO ₂
The Si substrate 11 is thermally oxidized using the film 12 as a mask. As a result, the SiO ₂ film 13 is formed corresponding to the opening 12a, and the channel stop 14 in contact with the lower surface of the SiO ₂ film 13 is formed.

Next, as shown in FIG. 9B, Si ₃ N ₄
The portions of the / SiO ₂ film 12 on the regions where the source lines S ₁ ... And the bit lines B ₁ ... Are to be formed are removed by etching. Then, the Si ₃ N ₄ / SiO ₂ film 12
And SiO ₂ film 13 as a mask, 5 × 10 ¹⁵ cm ^-2
As ⁺ 15 is ion-implanted into the Si substrate 11 with a dose of ^{2 to} form the n ⁺ type diffusion layers 16 and 17 to be the source lines S ₁ ... And the bit lines B ₁ ...

Next, the remaining Si ₃ N ₄ / SiO ₂
The Si substrate 11 is thermally oxidized using the film 12 as a mask. As a result, as shown in FIG. 9C, the thickness of the SiO ₂ film 13 increases to 500 nm, and the SiO ₂ film 21 having a thickness of 200 nm is formed on the diffusion layers 16 and 17.
These SiO ₂ films 13 and 21 partition the element isolation region.

The remaining Si ₃ N ₄ / SiO
After removing the ₂ film 12 by etching, a SiO ₂ film 22 having a film thickness of 7 nm is formed as a gate oxide film on the exposed surface of the Si substrate 11, and the floating gate nonvolatile Complete a semiconductor memory device.

[0009]

However, in the conventional example shown in FIG. 9, the Si ₃ N ₄ / SiO ₂ film 12 patterned in the step of FIG. 9A is formed in the step of FIG. 9B. Further patterning is performed. Therefore, the width of the diffusion layers 16 and 17 varies due to the alignment error of the patterning of FIG. 9B with respect to the patterning of FIG. 9A, and, for example, the width of the diffusion layer 16 becomes narrower than the designed value. Conversely, the width of the diffusion layer 17 becomes wider than the designed value.

When the width of the diffusion layer 16 as the source lines S ₁ ... Is narrower than the design value, the diffusion layer resistance in the diffusion layer 16 increases and the voltage drop increases. As a result, as apparent from FIG. 10, the memory cells M ₁₁ ...
The read current becomes less and the reading cannot be performed stably.

Further, when the width of the diffusion layer 17 as the bit lines B ₁ ... becomes wider than the designed value, the parasitic junction capacitance in the diffusion layer 17 increases, and as is apparent from FIG. The line capacitance increases. As a result, the diffusion layer 1
Memory cell M together with the increase of the diffusion layer resistance in FIG.
Read time from ₁₁ ... becomes long. Therefore, FIG.
In the conventional example shown in (1), it is difficult to manufacture a semiconductor device having stable characteristics.

[0012]

A method of manufacturing a semiconductor device according to a first aspect of the present invention is directed to a semiconductor device having diffusion layers 16 and 17 and a channel stop 14 below an oxide film 26 for element isolation in a semiconductor substrate 11. In the manufacturing method, the diffusion layer 1
Forming on the semiconductor substrate 11 a mask layer 12 having an opening 12a in regions 6 and 17 to be formed; and using the mask layer 12 as a mask, the diffusion layers 16 and 17
The first impurity 15 for forming the
1 and the step of removing the portion of the mask layer 12 on the region where the channel stop 14 is to be formed after introducing the first impurity 15, and the mask after the removal. Second impurity 25 for forming the channel stop 14 using the layer 12 as a mask
Is introduced into the semiconductor substrate 11, and after the second impurity 25 is introduced, the semiconductor substrate 11 is oxidized using the mask layer 12 as a mask to form the oxide film 26. It is characterized by doing.

A method of manufacturing a semiconductor device according to a second aspect of the present invention is the method of manufacturing a semiconductor device having diffusion layers 16 and 17 and a channel stop 14 under an insulating film 33 for element isolation in a semiconductor substrate 11. Forming on the semiconductor substrate 11 a first mask layer 12 having an opening 12a on the regions where the layers 16 and 17 are to be formed; and using the first mask layer 12 as a mask First
Forming the trench 27, forming the second mask layer 31 on the inner surface of the first trench 27, and forming the first trench 27, and then masking the first mask layer 12 And then introducing the first impurity 15 for forming the diffusion layers 16 and 17 into the semiconductor substrate 11, and after introducing the first impurity 15,
A step of removing a portion of the first mask layer 12 on a region where the channel stop 14 is to be formed, and, after the removal, using the first and second mask layers 12 and 31 as a mask, The second trench 3 is formed in the semiconductor substrate 11.
2 and the second trench 32 is formed, and then the second impurity 2 for forming the channel stop 14 is formed by using the first mask layer 12 as a mask.
5 is introduced into the semiconductor substrate 11, and after the second impurity 25 is introduced, the first and second trenches 27 and 32 are filled with the insulating film 33. There is.

A method for manufacturing a semiconductor device according to a third aspect is the method for manufacturing a semiconductor device according to the second aspect, wherein the depth of the second trench 32 is equal to or larger than the depth of the first trench 27. I am trying.

[0015]

In the method of manufacturing a semiconductor device according to claim 1, the opening 12a for forming the diffusion layers 16 and 17 is formed in the mask layer 12.
, The boundary between the regions where the diffusion layers 16 and 17 are not formed and the diffusion layers 16 and 17 is determined by the initial pattern of the mask layer 12.

Further, the channel stop 14 is formed after removing a part of the mask layer 12 used for forming the diffusion layers 16 and 17. The impurity concentration of the channel stop 14 is the diffusion layers 16 and 17. Since it is much lower than the impurity concentration of the diffusion layer 1, even if the channel stop 14 is formed,
The patterns of 6 and 17 do not change. Therefore, the boundary between the channel stop 14 and the diffusion layers 16 and 17 is also at the mask layer 1
2 determined by the original pattern.

In the method of manufacturing a semiconductor device according to a second aspect of the present invention, since the first mask layer 12 originally has the opening 12a for forming the first trench 27 and the diffusion layers 16 and 17, the diffusion layer is formed. The boundaries between the diffusion layers 16 and 17 and the regions where the layers 16 and 17 are not formed are determined by the initial pattern of the first mask layer 12.

Further, the first trench 27 and the diffusion layer 1
Part of the first mask layer 12 used to form the trenches 6 and 17 is removed, and the inner surface of the first trench 27 is covered with the first mask layer 12.
The second mask layer 3 in a self-aligned manner with respect to the mask layer 12 of
1 is formed. Then, the second trench 32 and the channel stop 14 are formed using the first and second mask layers 12 and 31.
Since the impurity concentration of No. 4 is much lower than the impurity concentration of the diffusion layers 16 and 17, the pattern of the diffusion layers 16 and 17 does not change even if the channel stop 14 is formed. Therefore, the boundary between the channel stop 14 and the diffusion layers 16 and 17 is also the first
Determined by the original pattern of the mask layer 12.

In the method of manufacturing a semiconductor device according to the third aspect, the depth of the second trench 32 is set to be equal to or larger than the depth of the first trench 27, so that the channel stop 14 is formed in the diffusion layer 1.
It is possible to form deeper than 6 and 17.

[0020]

The first and second embodiments of the present invention applied to the manufacture of a floating gate nonvolatile semiconductor memory device will be described below.
This will be described with reference to FIGS. It should be noted that both the first and second embodiments have the equivalent circuit shown in FIG. 7 and the planar structure shown in FIG. Moreover, FIGS.
In the first and second embodiments shown in FIG. 9, the components corresponding to those of the conventional example shown in FIG. 9 are denoted by the same reference numerals as those in FIG.

1 and 2 show a first embodiment. In the first embodiment, as shown in FIG. 1A, p-type Si is used.
On the substrate 11, the Si ₃ N ₄ / SiO ₂ film 12 having a film thickness of 100/5 nm and having the opening 12a on the regions where the n ⁺ type diffusion layers 16 and 17 are to be formed is patterned.

Then, from the opening 12a to the Si substrate 11, 5
After ion-implanting As ⁺ 15 with a dose amount of × 10 ¹⁵ cm ^-2 , annealing is performed and further Si ₃ N ₄ / SiO ₂ film 1 is formed.
2 is used as a mask to thermally oxidize the Si substrate 11. As a result, the n ⁺ type diffusion layers 16 and 17 to be the source lines S ₁ ... And the bit lines B ₁ ...
A SiO ₂ film 23 is formed on the surface of the Si substrate 11 in 2a.

Next, as shown in FIG. 1B, a photoresist 24 is applied on the entire surface, and the portion of the photoresist 24 on the region where the channel stop 14 is to be formed and on the region in the vicinity thereof is removed. Patterning is performed. Then, using the photoresist 24 as a mask, Si ₃ N ₄ /
The SiO ₂ film 12 and the SiO ₂ film 23 are removed by etching, and B ⁺ 25 is ion-implanted into the Si substrate 11 with a dose amount of 1 × 10 ¹³ cm ^-2 to form a channel between the diffusion layers 16 and 17. The stop 14 is formed.

The SiO ₂ film 23 is for preventing contaminants from entering the Si substrate 11 from the photoresist 24. Alternatively, B ⁺ 25 may be ion-implanted after removing the photoresist 24 and using only the Si ₃ N ₄ / SiO ₂ film 12 as a mask.

Next, as shown in FIG. 2A, the photoresist 24 is removed and the SiO ₂ film 23 is removed by etching. The Si ₃ N ₄ / SiO ₂ film 12 is used as a mask to thermally oxidize the Si substrate 11 to a film thickness of 200 to 3
A SiO ₂ film 26 having a thickness of 00 nm is formed in the element isolation region.

Next, as shown in FIG. 2B, after the remaining Si ₃ N ₄ / SiO ₂ film 12 is removed by etching, the exposed surface of the Si substrate 11 has a film thickness of 7 nm. The SiO ₂ film 22 is formed as a gate oxide film, and the floating gate type non-volatile semiconductor memory device is completed through known steps.

3 to 6 show a second embodiment. Also in this second embodiment, as shown in FIG. 3A, Si ₃ N _{4 is used.}
Until the patterning of the / SiO ₂ film 12, substantially the same steps as those in the first embodiment shown in FIGS. However, in this second embodiment, next, as shown in FIG. 3B, using the Si ₃ N ₄ / SiO ₂ film 12 as a mask, the trench 27 having a depth of 150 to 200 nm is formed on the Si substrate 1.
1 to form.

After that, the Si ₃ N ₄ / SiO ₂ film 12 is used as a mask to thermally oxidize the Si substrate 11 to a film thickness of 20 nm.
The SiO ₂ film 31 is formed on the inner surface of the trench 27. Then, As ⁺ 15 is applied from the opening 12a to the Si substrate 11.
Are ion-implanted into the source line S ₁ ... And the bit line B
_The n ⁺ type diffusion layers 16 and 17 which become ₁ ...
It is formed along the inner surface of 7.

Next, as shown in FIG. 4A, a photoresist 24 is applied on the entire surface, and a portion of the photoresist 24 where the channel stop 14 is to be formed and a portion in the vicinity thereof are removed. Patterning is performed. Then, using the photoresist 24 as a mask, Si ₃ N ₄ /
The SiO ₂ film 12 is removed by etching.

Next, as shown in FIG. 4B, after removing the photoresist 24, the Si ₃ N ₄ / SiO ₂ film 12 is removed.
And using the SiO ₂ film 31 as a mask, the depth is 200 to 3
A trench 32 having a thickness of 00 nm is formed in the Si substrate 11. Then, as shown in FIG. 5A, after removing the SiO ₂ film 31 by etching, the Si ₃ N ₄ / SiO ₂ film 12 is removed.
B ⁺ 25 is ion-implanted into the Si substrate 11 using the mask as a mask, and the channel stop 14 is formed between the diffusion layers 16 and 17.
To form.

Next, as shown in FIG. 5B, after the remaining Si ₃ N ₄ / SiO ₂ film 12 is removed by etching, a SiO ₂ film 33 is deposited on the entire surface, and this SiO ₂ film is deposited.
The film 27 fills the trenches 27 and 32. Then, the SiO ₂ film 33 is subjected to chemical mechanical polishing or etch back until the surface of the Si substrate 11 other than the trenches 27 and 32 is exposed to planarize the Si substrate 11.

Next, as shown in FIG. 6, a SiO ₂ film 22 as a gate oxide film is formed on the exposed surface of the Si substrate 11, and a polycrystalline Si film 34 is deposited on the entire surface of each memory cell M _11. The floating gate is formed by patterning into islands corresponding to.

After that, ON is performed as an insulating film for capacitive coupling.
An O film 35 is formed on the surface of the polycrystalline Si film 34, and the Al film 36 and the like deposited on the entire surface are patterned to form word lines W ₁ ... As control gates. Then, a surface protection film (not shown) and the like are further formed to complete this floating gate type nonvolatile semiconductor memory device.

As described above, it is apparent from the fact that both the first and second embodiments described above have the planar structure shown in FIG. 8 as in the conventional example. In addition, the memory cell areas of the first and second embodiments are not larger than the memory cell area of the conventional example.

In the first and second embodiments, the invention of the present application is applied to the manufacture of the floating gate type nonvolatile semiconductor memory device. However, the MONOS type nonvolatile semiconductor memory device and the ferroelectric MIS are formed. The invention of the present application can be applied to a nonvolatile semiconductor memory device and a semiconductor device other than the nonvolatile semiconductor memory device.

[0036]

According to the method of manufacturing the semiconductor device of the first and second aspects, both the boundary between the region where the diffusion layer is not formed and the diffusion layer and the boundary between the channel stop and the diffusion layer are formed on the semiconductor substrate. Since it is determined by the initial pattern of the formed mask layer, there is no variation in the width of the diffusion layer due to the alignment error. Therefore, it is possible to prevent the diffusion layer resistance and the parasitic junction capacitance from increasing and to manufacture a semiconductor device with stable characteristics.

In the method of manufacturing a semiconductor device according to the third aspect, since the channel stop can be formed deeper than the diffusion layer, a semiconductor device having excellent element isolation characteristics and high reliability can be manufactured. .

[Brief description of drawings]

FIG. 1 is a side cross-sectional view showing a first half step of a first embodiment of the invention of the present application in order and taken along a line AA in FIG.

FIG. 2 sequentially shows the latter half of the steps of the first embodiment,
It is a sectional side view in the position which follows the AA line of FIG.

FIG. 3 is a side cross-sectional view showing the initial step of the second embodiment of the present invention in order and is a position taken along the line AA of FIG.

FIG. 4 shows the middle steps of the second embodiment sequentially.
It is a sectional side view in the position which follows the AA line of FIG.

FIG. 5 sequentially shows the final steps of the second embodiment,
It is a sectional side view in the position which follows the AA line of FIG.

FIG. 6 is a side sectional view showing a floating gate nonvolatile semiconductor memory device manufactured in a second example, taken along a line AA in FIG.

FIG. 7 is an equivalent circuit diagram of a memory cell array of a floating gate type nonvolatile semiconductor memory device to which the invention of the present application can be applied.

FIG. 8 is a plan view of a memory cell array of a floating gate type nonvolatile semiconductor memory device to which the invention of the present application can be applied.

FIG. 9 is a side cross-sectional view showing a step in a conventional example of the invention of the present application in order and taken along a line AA in FIG. 8;

FIG. 10 is an equivalent circuit diagram including a bit line capacitance and a diffusion layer resistance in a memory cell of a floating gate nonvolatile semiconductor memory device.

[Explanation of symbols]

11 Si substrate 12 Si ₃ N ₄ / SiO ₂ film 12a opening 14 channel stop 15 As ⁺ 16 diffusion layer 17 diffusion layer 25 B ⁺ 26 SiO ₂ film 27 trench 31 SiO ₂ film 32 trench 33 SiO ₂ film

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Office reference number FI technical display location H01L 21/76 27/115 H01L 27/10 434

Claims (3)

[Claims] 1. A method of manufacturing a semiconductor device having a diffusion layer and a channel stop below an oxide film for element isolation in a semiconductor substrate, wherein a mask layer having an opening is formed on a region where the diffusion layer is to be formed. Forming on the semiconductor substrate, using the mask layer as a mask, introducing a first impurity for forming the diffusion layer into the semiconductor substrate, and after introducing the first impurity, Removing a portion of the mask layer above the region where the channel stop is to be formed; and, after the removal, using the mask layer as a mask, a second impurity for forming the channel stop is added to the semiconductor. And a step of introducing the second impurity into the substrate, and oxidizing the semiconductor substrate using the mask layer as a mask after introducing the second impurity to form the oxide film. The method of manufacturing a semiconductor device according to claim and. 2. A method of manufacturing a semiconductor device having a diffusion layer and a channel stop below an insulating film for element isolation in a semiconductor substrate, the first mask having an opening above a region where the diffusion layer is to be formed. Forming a layer on the semiconductor substrate; forming a first trench in the semiconductor substrate using the first mask layer as a mask; and a second mask layer on the inner surface of the first trench. Forming a first trench, and then introducing a first impurity for forming the diffusion layer into the semiconductor substrate by using the first mask layer as a mask after forming the first trench, Removing the portion of the first mask layer on the region where the channel stop is to be formed after introducing the first impurity, and removing the first and second mask layers. Into a mask And forming a second trench in the semiconductor substrate, and forming a second impurity for forming the channel stop by using the first mask layer as a mask after forming the second trench. A method of manufacturing a semiconductor device, comprising: a step of introducing into the semiconductor substrate; and a step of filling the first and second trenches with the insulating film after introducing the second impurity. 3. The method for manufacturing a semiconductor device according to claim 2, wherein the depth of the second trench is set to be equal to or greater than the depth of the first trench.