JPH08111457A - Fabrication of semiconductor device - Google Patents

Abstract

PURPOSE: To make uniform the stress being applied to each part on the surface of a lower layer wiring by etching the corner part at a level difference of a second insulation film caused by a first layer wiring more than other faces of the second insulation film by sputter etching using an inert gas. CONSTITUTION: A second insulation film 13' is cut off obliquely and preferentially by sputter etching from the corner part on the upper surface of first layer wiring 12A, 12B. SiO2 subjected to sputter etching is redeposited as a redeposition layer 33 on the side face of wiring in a recess between the wiring 12A, 12B which is least susceptible to sputter etching and thereby the second insulation film has substantially uniform thickness over the entire surface of the first and second layer wiring 12A, 12B. Since the second insulation film 13 covering the surface of the first layer wiring 12A, 12B directly has substantially uniform thickness over the upper surface of wiring, the corner part on the upper surface and the side face of the wiring, stress to be applied to the first layer wiring 12A, 12B can be made uniform.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device,
In particular, it relates to a method for forming an interlayer insulating film in a multilayer wiring structure.

Recently, in semiconductor devices, wiring tends to be further miniaturized and arranged at high density due to high integration. Along with this, the aspect ratio of the recess formed between the wirings is increased, and a steep uneven step is formed on the surface of the interlayer insulating film formed on the wiring. When the upper layer wiring is formed directly on the interlayer insulating film, defects such as step breakage will occur in the upper layer wiring due to insufficient coverage. Therefore, in the multilayer wiring structure, a spin-on-glass coating layer is added to the interlayer insulating film to alleviate the steepness of the step.

In such a structure of the interlayer insulating film, there is a problem that a non-uniform stress applied from the interlayer insulating film to the surface of the lower wiring in contact therewith causes a wedge-shaped defect defect in the lower wiring. , Improvement is desired.

[0004]

2. Description of the Related Art A method for forming a multi-layered wiring in which a surface on which an upper layer wiring is formed is flattened is known as a method capable of forming an interlayer insulating film having a flattened surface at a relatively low cost. The method using spin-on-glass as described below with reference to the process sectional view of FIG.

Referring to FIG. 6 (a), that is, in the above-mentioned conventional method, for example, an aluminum / copper / titanium (AlCuTi) alloy layer 52a is formed on the first insulating film 51 made of silicon oxide (SiO ₂ ) by a normal wiring forming method. Is used as a main conductive layer, and a first-layer wiring 52 having a titanium nitride (TiN) layer 52b as a barrier metal and a Ti layer 52c as a contact metal underneath is formed. The width of the first layer wiring 52 is about 800 nm,
The uTi alloy layer 52a has a thickness of about 500 nm, the TiN layer 52b has a thickness of about 150 nm, and the Ti layer 52c has a thickness of about 20 nm.

Next, referring to FIG. 6B, plasma CVD is performed on the formation surface of the first layer wiring 52.
The second insulating film 53 made of a SiO ₂ film having a thickness of about 350 nm is formed by the method. The second insulating film 53 formed by the plasma CVD method tends to be deposited particularly thickly on the corners or shoulders of the upper surface of the wiring 52.

Next, referring to FIG. 6 (c), a 500 nm film is formed on the substrate by a conventional spin coating method.
After the silanol-based spin-on-glass (SOG) layer 54 is applied to a thickness of about a degree (on the flat portion of the recess between the wirings) and cured to form a third insulating film, then the third insulating film is formed. The SOG layer 54 is etched back by about 300 nm to expose the second insulating film 53 on the first layer wiring 52 by the CVD method.

Then, referring to FIG. 6 (d), SiO _{2 is} deposited on the substrate by plasma CVD.
Alternatively, a fourth insulating film 55 made of phosphosilicate glass (PSG) and having a thickness of about 500 nm is formed by the low temperature growth CVD method.

Next, referring to FIG. 6 (e), a fourth insulating film 55 and a second insulating film 53 therebelow.
Then, a via hole 56 exposing the upper surface of the first layer wiring 52 is formed by ordinary photolithography and etching means.

Next, referring to FIG. 6 (f), according to a normal wiring forming method, on the substrate,
The first exposed in the via hole 56 at the above-mentioned via hole portion 56
A second layer wiring 57 made of, for example, an AlCuTi alloy is formed so as to contact the layer wiring 52 and extend on the fourth insulating film 55.

The above steps are repeated when forming a multi-layered wiring having three or more layers.

[0012]

However, in the above-mentioned conventional method, there have been problems as described below with reference to FIG.

Referring to FIG. 7A, that is, when the second insulating film 53 is formed by plasma CVD, the width w and the distance d of the first layer wiring 52 are 7
When the width is reduced to about 00 to 800 nm, the film thickness t of the second insulating film 53 deposited on the side surface portion 52S of the wiring 52 becomes extremely smaller than the film thickness T of the upper portion. Then, during the heat treatment such as the deposition of the insulating film in the upper layer and the reflow of the insulating film in the multilayer wiring forming step, the second insulating film 53 on the upper and side surfaces is formed.
The stress exerted on the wiring due to the large difference in the thickness of
The first layer wiring 52 having a narrow wiring width as described above cannot be absorbed completely.

Referring to FIG. 7B, as shown in FIG. 5B in a plan view, a wedge-shaped deep defect portion 58 is formed on the side surface of the first layer wiring 52, and
There is a problem that the reliability of the layer wiring 52 is significantly reduced.

Therefore, the present invention extends from the second insulating film, that is, the interlayer insulating film formed by directly covering the first layer wiring, that is, the lower layer wiring, to each part of the surface of the first layer wiring, that is, the lower layer wiring. It is an object of the present invention to make the stress uniform so as to prevent a defect defect from occurring in the one-layer wiring, that is, the wiring immediately below the interlayer insulating film in the multilayer wiring forming process.

[0016]

Means for Solving the Problems To solve the above-mentioned problems, a step of forming a first-layer wiring on a first insulating film in the formation of a multi-layer wiring, and a first insulation including the first-layer wiring A step of forming a second insulating film on the film by a plasma CVD method, and a corner portion of a step of the second insulating film caused by the first layer wiring by the sputter etching method using an inert gas. A step of etching more than the other surface of the second insulating film, a step of forming a polysilazane layer on the sputter-etched second insulating film by a coating method, and then curing the polysilazane layer; and a step of curing the polysilazane layer. Forming a via hole on the first layer wiring by selectively etching a layer and the second insulating film, and a second layer contacting the first layer wiring on the polysilazane layer via the via hole Form the wiring A method for manufacturing a semiconductor device according to the present invention, which comprises a step of forming a first layer wiring on a first insulating film, and a step of forming a first insulating layer including the first layer wiring. A step of forming a second insulating film on the film by a plasma CVD method, and a corner portion of a step of the second insulating film caused by the first layer wiring by the sputter etching method using an inert gas. A step of etching more than the other surface of the second insulating film, and applying a coating insulating film on the sputter-etched second insulating film, and then curing the coating insulating film to form a third insulating film. And a step of etching back the third insulating film to expose the second insulating film above the first layer wiring, and a step of including the exposed second insulating film. Forming a fourth insulating film on the third insulating film, and the first layer A step of selectively etching the fourth insulating film and the second insulating film on a line to form a via hole on the first layer wiring; and a step of contacting the first layer wiring via the via hole. And a step of forming a two-layer wiring.

[0017]

1, 2 and 3 are explanatory views of the principle of the present invention, in which 1 is a first insulating film, 2A and 2B are first layer wirings, and 3 is formed by a plasma CVD method. Second insulating film, 3'is a portion of the second insulating film which is etched by sputter etching, 33 is a redeposition layer of the second insulating film, 4 is a polysilazane layer, 44 is an SOG layer (third insulating film). ), 5 is a fourth insulating film, 6 is a via hole, and 7 is a second layer wiring.

The wedge-shaped defect defect (see FIG. 7 (b)) which has been generated in the first layer wiring in the conventional multilayer wiring formation occurs for the following reason. That is, when the first-layer wiring is miniaturized and its interval is also reduced, the film thickness of the second insulating film directly deposited on the first-layer wiring is determined by the corner portions of the upper and upper surfaces of the wiring. Since it is formed thick on the (shoulder portion) and extremely thin on the side surface portion, the strength of the stress exerted by the second insulating film on the upper layer portion and the lower layer portion of the first layer wiring is different. In the miniaturized first layer wiring, the ratio of the cross-sectional area of the second insulating film to the cross-sectional area of the wiring is large, so that the stress exerted on the upper layer portion and the lower layer portion of the first layer wiring is reduced. This is because the difference in strength becomes an extremely large value, and the miniaturized first layer wiring cannot absorb the strain due to this stress difference.

Therefore, in the method of the present invention, as shown in (a) of the principle explanatory view of FIG. 1, first layer wirings 2A, 2B, etc. made of a fine Al alloy or the like are formed on the first insulating film 1. After the second insulating film 3 having a thickness of about 500 nm made of, for example, SiO _{2 is} deposited by the plasma CVD method on the surface formed in close proximity (for example, the line and space is about 800 nm), the Sputter etching is performed using active ions such as Ar ⁺ . This sputter etching acts most strongly on the portion of the second insulating film that is projected and deposited on the corners (shoulders) of the upper surface of the first-layer wirings 2A, 2B where the electric field is concentrated. Then, as shown in FIG.
The thickness t ₁ of the second insulating film 3 on the corners of the upper surface of A, 2B, etc. is made thinner than the thickness T of the upper portion of the first layer wiring 2A, 2B, etc. In the figure, 3'represented by a chain line indicates a part of the second insulating film 3 which has been scraped off. It has been experimentally confirmed that the thickness of t ₁ is preferably ⅓ or less of the diagonal length A of the wiring cross section.

The next strongest effect of sputter etching is on the upper portions of the wirings 2A, 2B, etc., where a predetermined etching rate can be obtained. Then, it hardly acts on the second insulating film 3 formed in the concave portion 8 between the wirings 2A, 2B, etc., and conversely, the second insulating film 3 sputter-etched is formed on that portion. The redeposition layer 33 is redeposited as shown by chain lines and diagonal lines. By experimentally selecting the conditions of this sputter etching, the thickness of the second insulating film 3 deposited on each part of the surface of the first layer wirings 2A, 2B, etc. can be made almost equal as shown in FIG. Can be uniform.

Therefore, the stress exerted on the upper and lower layers of the first-layer wirings 2A, 2B, etc. from the second insulating film covering the wirings 2A, 2B, etc. is substantially equalized, so that the above-mentioned stress Defect defects of the first layer wirings 2A, 2B and the like caused by the balance are prevented.

In the first method according to the present invention, as shown in FIG. 2, the second insulating film 3 for covering the surfaces of the first layer wirings 2A, 2B, etc. is formed by the above method with a substantially uniform thickness. After the formation, the polysilazane layer 4 is spin-coated on the surface on which the second insulating film 3 is formed, whereby the surface of the interlayer insulating film is flattened. At this time, the first layer wiring is formed by the sputter etching.
Since the second insulating film 3 on the corners of the upper surface of 2A, 2B, etc. is shaved off obliquely, the polysilazane can easily flow into the space of the first layer wiring 2A, 2B, etc. There is no cavity left in the part. Further, in this method, since the oxidation of silicon oxide in the cure of polysilazane is caused by an oxidation reaction, there is no generation of water which deteriorates the wiring, and accordingly, there is no water contained in the film. Therefore, after the via hole 6 for exposing the first layer wiring 2A, for example, is formed in the cured polysilazane layer 4 and the second insulating film 3 thereunder, the first layer wiring 2A is formed on the polysilazane layer 4 by the via hole 6. Even if the second-layer wiring 7 that contacts the second wiring 7 is formed, the wiring quality of the second-layer wiring 7 and the contact quality with the first-layer wiring 2A are not deteriorated by moisture, so that the process can be simplified.

The second method according to the present invention is a case where, for example, a silanol-based SOG is used for the SOG layer for flattening the surface of the interlayer insulating film, which is accompanied by generation of water due to dehydration condensation of silicon oxide by cure. Etc., the moisture remaining in the cured SOG layer reduces the grain size of the upper layer wiring at the time of forming the upper layer wiring on the SOG layer, so that the upper layer wiring may be deteriorated in electromigration resistance. This is a method for preventing the deterioration of the reliability. After the step of FIG. 1, the second insulating film 3 having a uniform film thickness covering the surfaces of the first layer wirings 2A and 2B is formed. As shown in FIG. 3, the SOG layer 44 is applied and cured on the formation surface to form a third insulating film SOG layer 44 on which a fourth insulating film 5 is formed by a plasma CVD method to form a second insulating film. Layer wiring 7 on SOG layer 44 As well as to not to touch the,
SOG layer (third insulating film) above the one-layer wiring 2A, 2B, etc.
44 is previously removed before the fourth insulating film 5 is deposited, and
It is possible to prevent the SOG layer (third insulating film) 44 from being exposed in the via hole 6 formed on the layer wiring 2A,
The second layer wiring 7 is prevented from deteriorating.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the drawings. FIG. 4 is a process sectional view of one embodiment of the present invention,
5A to 5D are process sectional views of another embodiment of the present invention. The same object is denoted by the same reference numeral throughout the drawings.

Referring to FIG. 4 (a), when a multilayer wiring structure of a semiconductor device is formed by the method of the present invention, Si formed on a semiconductor substrate (not shown) is used.
A Ti film 12c having a thickness of 20 nm to be a contact metal is formed on the first insulating film 11 made of O ₂ by, for example, a sputtering method.
Then, a TiN film 12b with a thickness of 150 nm to be a barrier metal and an AlCuTi alloy film 12a with a thickness of 500 nm to be a main conductive layer are sequentially formed, and then the above-mentioned laminated film is patterned using ordinary photolithography and dry etching means. hand,
First layer wirings 12A and 12 having an L & S of about 800 nm, which are formed by sequentially stacking a contact metal Ti film 12c, a barrier metal TiN film 12b, and a main conductive layer AlCuTi alloy film 12a from the lower layer.
Form B etc. The dry etching uses a reactive ion etching (RIE) process using (BCl ₃ + Cl ₂ ) as an etching gas, for example.

Next, referring to FIG. 4 (b), a thickness of 500 nm is formed on the main surface by plasma CVD.
A second insulating film 13 made of, for example, SiO ₂ is deposited.

For plasma CVD of this second insulating film,
For example, the following conditions are used. The second insulating film 13 deposited under the above conditions is a film that is thick as shown in the same manner as in the conventional case, on the upper portions and the corners (shoulders) of the first layer wirings 12A, 12B, etc. and the side portions are extremely thin. Becomes

Next, as shown in FIG. 4C, the entire surface of the second insulating film 13 is etched by sputter etching using argon ions (Ar ⁺ ).

For example, the following conditions are used for sputter etching. Ar gas flow rate 100 sccm Vacuum degree 0.01 Torr RF power (13.56MHz) 700 W Etching time 120 sec This process causes the first layer wirings 12A, 12B, etc. to have defective defects. The first layer wirings 12A, 12B, etc. The second insulating film 13 '(shown by a chain line) at the corner (upper shoulder) of the upper surface of the is preferentially shaved to a thickness of about 200 nm.
The reason is that the sputter yield of that portion is the highest due to the protruding shape. Then, sputter-etched SiO ₂ becomes a redeposition layer 33 on the side surfaces of the wirings in the recesses between the wirings 12A and 12B where sputter etching is least likely to act, and redeposited as shown by chain lines and diagonal lines. The second insulating film on the entire surface of the first layer wiring 12A, 12B, etc.
The thickness of 13 is about 400 to 500 nm, which is almost uniform.

As described above, the thickness of the second insulating film 13 that directly covers the surfaces of the first-layer wirings 12A, 12B, etc. is made substantially uniform over the upper surface, the corners and side surfaces of the upper surface of the wirings. Due to the imbalance of the thickness of the second insulating film 13,
The strong stress exerted on the layer wirings 12A, 12B, etc. is eliminated,
It is possible to prevent occurrence of defective defects in the first layer wirings 12A, 12B and the like.

Next, as shown in FIG. 4D, a polysilazane layer 14 of SOG is formed on the main surface on which the sputter etching is finished by a conventional spin coating method to a thickness of 100 to 800 nm so as to be planarized. . In this example, coating was performed so that the thickness of the plane portion was 200 nm. Then, the polysilazane layer 14 is cured (silicon oxide conversion) under the condition that the atmosphere (strictly speaking, the moisture content in the atmosphere) is not caught by using a vertical furnace. Reference numeral 14 'indicates a cured (silicon oxide) polysilazane layer. The curing conditions are as follows, for example.

O ₂ gas flow rate 10 slm or more Temperature 450 ° C. Time 30 min In the above spin coating, the first layer wirings 12 A, 12 in the first SiO ₂ insulating film 13 are formed by the sputter etching.
Since the corners (shoulders) of the upper surface of B etc. are cut away obliquely, polysilazane easily flows into the recesses between the first layer wirings 12A, 12B etc., and no cavities remain there. .

Further, since the reaction of converting the polysilazane into silicon oxide by the curing is an oxidation reaction, the formed silicon oxide layer does not contain water. Therefore, in this method, even if the upper wiring is directly formed on the cured polysilazane layer 14 ', the quality and reliability of the upper wiring are not deteriorated.

Referring to FIG. 4E, in the method of this embodiment, for example, the cured polysilazane layer 14 'and the second polysilazane layer 14' are formed on the upper portion of the first layer wiring 12A.
A via hole 16 penetrating the insulating film 13 is formed by normal photolithography and dry etching treatment using a fluorine-based gas, and then by a normal wiring forming method.
On the cured polysilazane layer 14 ', a second layer wiring 17 made of an Al alloy or the like that contacts the first layer wiring 12A is formed in the via hole 16 to complete a multilayer wiring structure.

In another embodiment of the present invention described with reference to FIG. 5, silanol-based SOG is used for the SOG layer for flattening the interlayer insulating film. See FIG. 5 (a). In this method, after the steps shown in FIG. 4 (c) are completed by the same method as in the first embodiment, the first layer wirings 12A, 12B, etc. have a substantially uniform thickness. On the surface covered with the second insulating film 13,
Silanol-based SOG layer for planarization by spin coating
Form 34 to a thickness of about 200 nm. And 450 in oxygen
The silanol-based SOG layer is cured (oxidized into silicon oxide) at a temperature of about ℃ to obtain a silicon oxide layer (third insulating film)
Set to 34 '. Since the silanol-based SOG silicon oxide conversion reaction is a dehydration condensation reaction, water is not used for curing.
(H ₂ O) is generated, and this H ₂ O is contained in the cured silanol-based SOG layer, that is, the silicon oxide layer (third insulating film) 34 ′.

Therefore, in this embodiment, a fluorine-based gas such as SF _{6 is used.}
The silanol-based SOG layer 34 ', which has been cured by the RIE process using the above-mentioned materials, is applied to the C on the first layer wirings 12A, 12B, etc.
Etching back is performed until the second insulating film 13 formed by VD is exposed. This is because the silanol-based SOG layer 34 'containing the water is not left in the via hole forming portion.

Next, referring to FIG. 5 (c), the second insulating film 13 exposed above and the remaining silanol-based SOG layer (third layer) are formed by a normal plasma CVD method.
A continuous fourth insulating film 15 made of SiO ₂ or PSG having a thickness of about 200 nm. The fourth insulating film 15 is a barrier insulating film for preventing the moisture contained in the silanol-based SOG layer 34 'from adversely affecting the upper wiring such as an Al alloy formed on the upper portion.

Next, referring to FIG. 5D, a via hole penetrating the upper fourth insulating film 15 and the second insulating film 13 is formed, for example, on the first layer wiring 12A by using ordinary photolithography and dry etching means. 16 is formed, and then the second layer wiring 17 made of Al alloy or the like that contacts the first layer wiring 12A at the via hole 16 is formed on the fourth insulating film 15 by the usual wiring forming means to form a multilayer wiring structure. Is completed.

In the above embodiment, the first layer wiring 12
Wirings of the second insulating film 13 formed by directly covering the surfaces of the first layer wirings 12A, 12B, etc. for separating A, 12B, etc. from the SOG layer 14 or 34 used for planarizing the interlayer insulating film The second shoulder is thinned to cover the surface of the wiring.
Although the film thickness of the insulating film 13 is made uniform by sputter etching using inert ions, this is not limited to the above method.

That is, for example, by the deposition (etching) method, which is a deposition (CVD method) including etching under the following conditions, the entire surface of the first layer wirings 12A, 12B, etc. has a substantially uniform film thickness. Of course, the same effect as the method of the present invention can be obtained by using the method of depositing the second insulating film.

Deposition / etching method conditions (deposition and etching are switched every few seconds.) Deposition apparatus Plasma CVD apparatus Growth gas SiH ₄ 40 sccm N ₂ O 410 sccm N ₂ 2 slm Pressure 3 Torr RF power (13.65 MHz ) 300 W etching (performed with the residual gas in the film formation system exhausted) Etching gas Ar 100 sccm Pressure 30 m Torr RF power (13.65 MHz) 500 W (Under these conditions, the etching rate is about 10Å / sec. ) Further, the second insulating film is not limited to the SiO ₂ film,
Silicon nitride (Si ₃ N ₄ ) film, silicon oxynitride (SION)
A film or the like is also used.

[0042]

As described above, according to the present invention, in a semiconductor device having a multi-layered wiring structure, it is possible to prevent a defective defect from being generated in the wiring in the lower layer due to the stress received from the interlayer insulating film, and to improve the yield of the semiconductor device. And reliability is improved.

Further, in particular, according to the method of the present invention in which polysilazane is used to planarize the surface of the interlayer insulating film, the multi-layer wiring forming process is simplified as compared with the conventional method, and the manufacturing steps can be shortened and the manufacturing cost can be reduced. .

[Brief description of drawings]

FIG. 1 is an explanatory diagram of the principle of the present invention (No. 1)

FIG. 2 is an explanatory diagram of the principle of the present invention (No. 2)

FIG. 3 is an explanatory diagram of the principle of the present invention (No. 3)

FIG. 4 is a process sectional view of an embodiment of the present invention.

FIG. 5 is a process sectional view of another embodiment of the present invention.

FIG. 6 is a process sectional view of a conventional method.

FIG. 7 is a schematic diagram showing problems of the conventional method.

[Explanation of symbols]

 1 First Insulating Film 2A, 2B First Layer Wiring 3 Second Insulating Film 3'Scraped Part of Second Insulating Film 33 Redeposition Layer of Second Insulating Film 4 Polysilazane Layer 44 SOG Layer (3rd Insulating film) 5 Fourth insulating film 6 Via hole 7 Second layer wiring 8 Recess between first layer wiring

Claims (4)

[Claims] 1. When forming a multi-layer wiring, a step of forming a first-layer wiring on a first insulating film, and a plasma of a second insulating film on the first insulating film including the first-layer wiring. The step of forming by the CVD method and the corners of the step of the second insulating film caused by the first layer wiring are compared with the other surface of the second insulating film by the sputter etching method using an inert gas. A step of forming a polysilazane layer on the sputter-etched second insulating film by a coating method and then curing the polysilazane layer, and selecting the polysilazane layer and the second insulating film. Selectively etching to form a via hole on the first layer wiring, and forming a second layer wiring on the polysilazane layer to contact the first layer wiring via the via hole. Characteristic half A method for manufacturing a conductor device. 2. A step of forming a first layer wiring on a first insulating film in forming a multilayer wiring, and a plasma of a second insulating film on the first insulating film including the first layer wiring. The step of forming by the CVD method and the corners of the step of the second insulating film caused by the first layer wiring are compared with the other surface of the second insulating film by the sputter etching method using an inert gas. Etching a large amount, and a step of applying a coating insulating film on the sputter-etched second insulating film and then curing the coating insulating film to form a third insulating film.
A step of etching back the third insulating film to expose the second insulating film above the first layer wiring; and a step of exposing the exposed second insulating film.
Forming a fourth insulating film on the third insulating film including the second insulating film, the fourth insulating film on the first layer wiring, and the second insulating film.
Selectively etching the insulating film to form a via hole on the first layer wiring, and forming a second layer wiring contacting the first layer wiring via the via hole. A method for manufacturing a characteristic semiconductor device. 3. The method of manufacturing a semiconductor device according to claim 2, wherein silanol spin-on glass is used for the coating insulating film. 4. The method of manufacturing a semiconductor device according to claim 2, wherein polysilazane is used for the coating insulating film.