JPH0810559B2 - Semiconductor memory device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a semiconductor memory device, for example, a mask type ROM (read only memory) having a function of switching to 8 bits / 16 bits. And effective technology.

[Conventional technology]

It is conceivable that the mask ROM is provided with an output function of switching the number of output bits between 8 bits and 16 bits by a switching signal supplied from an external terminal. As a mask type ROM having a mask programmable 4-bit and 8-bit output switching function, for example, "Hitachi IC Memory Data Book" issued by Hitachi, Ltd. in September 1985
There is "HN61256P / 61256FP" of P293 of.

In this mask type ROM, 16 bits are output when the switching signal BHE is at the low level, 8 bits are output when the switching signal BHE is at the high level, and among the 16 bits among the 16 bits depending on a specific address signal. The upper 8 bits or the lower 8 bits are output.

[Problems to be solved by the invention]

Since the operation speed of the mask type ROM is relatively slow, it is possible to use a simple switching circuit which is controlled by a combination of the control signal BHE and a specific address signal.
Of the bit read signal, the upper or lower 8 bits can be output. However, when trying to increase the operating speed, the speed cannot be increased by the simple switching circuit as described above. That is, when the address signal is not determined, either the higher-order signal or the circuit signal is temporarily output. Therefore, when the true read signal is output by the determination of the address signal,
It takes time to invert the above-mentioned temporarily output signal.

An object of the present invention is to provide a semiconductor memory device having a function of switching the number of output bits under high speed operation.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for solving problems]

The outline of a typical one of the inventions disclosed in the present application will be briefly described as follows. That is,
A read signal composed of a plurality of bits is supplied to each of the sense amplifiers divided into two sets, and the operation of these sense amplifiers is performed at an early timing according to an output switching control signal and a specific address signal. Pair and second
First, the output signals of the respective sense amplifiers of the set are switch-controlled at a timing delayed from the operation timing thereof.
A first output control circuit which complementarily controls the second switch circuit, and which receives the signal of the common output node and sends it to an external terminal in accordance with a substantial chip selection signal; and the second sense amplifier. Receiving the output signal of
A second output control circuit for sending each to an external terminal according to an output control signal formed based on the output switching control signal and the chip selection signal is provided.

[Action]

According to the above-mentioned means, when only the read signal of the divided number of bits among the plurality of bits is sent to the external terminal, there is a time difference between the operation of the sense amplifier and the switching of its output. Since only the read signal is transmitted to the output signal path, high speed can be realized.

〔Example〕

FIG. 1 shows a circuit diagram of an embodiment of an output circuit in a mask type ROM to which the present invention is applied. The ROM of this embodiment is not particularly limited, but is formed on one semiconductor substrate such as single crystal silicon by a known CMOS circuit manufacturing technique. Although not particularly limited, the integrated circuit is formed on a semiconductor substrate made of single crystal P-type silicon. The N-channel MOSFET is formed on the surface of the semiconductor substrate (channel region) between the source region and the drain region and between the source region and the drain region through a gate insulating film having a small thickness. It is composed of a gate electrode made of silicon. The P-channel MOSFET is formed in the N-type well region formed on the surface of the semiconductor substrate. As a result, the semiconductor substrate has a plurality of N channel MOs formed thereon.
Configure a common substrate gate for SFETs. The N-type well region constitutes the substrate gate of the P-channel MOSFET formed thereon. In the figure, the P-channel MOSFET is
By adding an arrow to that channel, N
Distinct from channel MOSFETs.

In this embodiment, since the number of output bits can be switched to 8 bits / 16 bits, there is no particular limitation, but the memory array unit is composed of the memory arrays M0 to M7 and M8 to M1.
As shown in 5, it is divided into two sets. Each memory array can be
One memory cell is selected from each of M0 to M15, and a read signal of 16 bits in total is transmitted in parallel.

The read signal from the memory array M0 is supplied to the input terminal of the sense amplifier SA0. Sense amplifiers SA1 to SA7 are provided for read signals from the other memory arrays M1 to M7 of the same set, respectively. The operations of these sense amplifiers SA0 to SA7 are controlled by the timing signal S1.

Similarly, the read signal from the other set of memory arrays M8 is supplied to the input terminal of the sense amplifier SA8. Sense amplifiers SA9 to SA15 are provided for read signals from the other memory arrays M9 to M15 of the same set, respectively. These sense amplifiers SA8 to SA15 are
The operation is controlled by the timing signal S2.

The output signal of the sense amplifier SA0 exemplarily shown as a representative of the NOR gate circuit G1 as an output control circuit is passed through a CMOS switch circuit composed of a parallel N-channel MOSFET Q1 and a P-channel MOSFET Q2. It is supplied to one input terminal. The chip selection signal ▲ ▼ is supplied to the other input terminal of the NOR gate circuit G1. The output signal of the NOR gate circuit G1 is sent to the external terminal D0 via the output inverter circuit N4, although not particularly limited. Circuits similar to the above are provided for the output signals of the other sense amplifiers SA1 to SA7.

In another set, the output signal of the sense amplifier SA8 exemplarily shown as the above-mentioned representative outputs 8-bit output, and therefore, through the CMOS switch circuit composed of the N-channel MOSFET Q3 and the P-channel MOSFET Q4 arranged in parallel, It is supplied to the input terminal of the NOR gate circuit G1 as an output control circuit. Also, because it outputs 16 bits,
The output signal of the sense amplifier SA8 is not particularly limited, but one input of a NOR (NOR) gate circuit G2 as an output control circuit via a CMOS switch circuit including an N-channel MOSFET Q7 and a channel MOSFET Q8 arranged in parallel. Supplied to the terminal. An inverted control signal ▲ ▼ is supplied to the other input terminal of the NOR gate circuit G2. The output signal of the NOR gate circuit G2 is not particularly limited,
It is sent to the external terminal D8 via the output inverter circuit N5. Circuits similar to the above are provided for the output signals of the other sense amplifiers SA9 to SA15.

The CMOS switch circuit composed of the MOSFETs Q1 and Q2 is controlled by the control signal S1 '. That is, the control signal S1 '
Is supplied to the gate of the N-channel MOSFET Q1, inverted by the inverter circuit N1, and supplied to the gate of the P-channel MOSFET Q2. The CMOS switch circuit composed of the MOSFETs Q3 and Q4 is controlled by the control signal S2 '. That is, the control signal S2 'is supplied to the gate of the N-channel MOSFET Q3, inverted by the inverter circuit N2, and supplied to the gate of the P-channel MOSFET Q4. MOSFET Q7 and Q8 above
The CMOS switch circuit consisting of is controlled by the control signal BH. That is, the control signal BH is the N-channel MOSFET Q7.
Is supplied to the gate of the P-channel MOSFET Q8 after being inverted by the inverter circuit N3.

Each control signal S1, S2 and S1 ', S2' and BH (▲ ▼)
Are formed by the following switch control circuit SWC.

Chip selection signal ▲ ▼ and output switching signal BHE are
It is supplied to the NOR gate circuit G3. This NOR gate circuit G3
Forms an output mode switching signal BH. This signal
BH is used as a control signal for the CMOS switch circuits (Q7, Q8), inverted by an inverter circuit (not shown), and transmitted to the NOR gate circuit G2.

The signal BH is also used as a control signal for the NOR gate circuit G4 that receives the address signal Ai. The output signal of the NOR gate circuit G4 and the signal BH are supplied to the NOR gate circuit G6. The output signal of the inverter circuit N7 that receives the output signal of the NOR gate circuit G4 and the signal BH are supplied to the NOR gate circuit G8.

The NOR gate circuit G6 is used to generate operation timing signals of the sense amplifiers SA0 to SA7 corresponding to the lower bits D0 to D7 and control signals S1 and S1 'of the output switch circuits thereof. That is, the output signal of the NOR gate circuit G6 is
It is inverted by the inverter circuit N10 and supplied as the operation control signal S1 to the sense amplifiers SA0 to SA7. Further, the output signal of the NOR gate circuit G6 and the delay signal passed through the delay circuit including the inverter circuits N8 and N9 are supplied to the NOR gate circuit G7, and the switch control signal S1 'is formed.

The NOR gate circuit G8 is used to form the operation timing signals of the sense amplifiers SA8 to SA15 corresponding to the upper bits D8 to D15 and the control signals S2 and S2 'of the output switch circuits thereof. That is, the output signal of the NOR gate circuit G8 is inverted by the inverter circuit N12 and supplied as the operation control signal S2 to the sense amplifiers SA8 to SA15. Further, a NOR gate circuit G9 and an inverter circuit which receive the output signal of the NOR gate circuit G6 and the signal BH.
The delay signal passed through the delay circuit composed of N11 is supplied to the NOR gate circuit G10 to form the switch control signal S2 '.

The 8-bit output operation by the circuit of this embodiment will be described with reference to the timing chart shown in FIG.

In 8-bit output operation, the switching signal BHE is
Set to high level (logic “1”). Therefore, during the read operation in which the chip select signal ▲ ▼ is set to the low level, the switch MOSFETs Q7 and Q8 are turned off because the signal BH is set to the low level due to the high level of the signal BHE. The output signal of the NOR gate circuit G2 is maintained at the low level due to the high level of the signal ▲ ▼.

In this state, if the address signal Ai is low level, the output signal of the NOR gate circuit G4 becomes high level and the output signal of the NOR gate circuit G6 becomes low level. As a result, the control signal S1 output from the inverter circuit N10 becomes high level at a relatively early timing, and the sense amplifiers SA0 to SA7 are activated. At this time, since the low-level signal is supplied from the inverter circuit N7 to the NOR gate circuit G8, the output signal thereof becomes the high level.
As a result, the control signals S2, S2 'obtained from the inverter circuit N12 and the NOR gate circuit G10 become low level as shown by the dotted line in the figure, so that the sense amplifiers SA8 to SA15 are kept in the inactive state and the MOSFET Q3 , The CMOS switch circuit composed of Q4 is turned off.

Operation timing signal of the above sense amplifiers SA0 to SA7
Inverter circuit that forms the delay circuit after S1 is generated
In response to the delay of the output signal of N9 to the low level, the output signal S1 ′ of the NOR gate circuit G7 changes from the low level to the high level. This causes MOSFETs Q1 and Q2 to be turned on with a delay, and the sense amplifiers SA0 to SA7
Output signal is sent to the external terminals D0 to D7 via the output control NOR gate circuit G1.

When the address signal Ai is at high level, the output signal of the NOR gate circuit G4 becomes low level, and the output signal of the NOR gate circuit G6 becomes high level. by this,
Since the output signals S1 and S1 'obtained from the inverter circuit N10 and the NOR gate circuit G7 are set to low level, the sense amplifiers SA0 to SA7 are deactivated and the switch MOSFETs Q1 and Q2 provided at their outputs are turned off. To be done. Since the output signal of the inverter circuit N7 is set to the high level by the low level of the output signal of the NOR gate circuit G4, the output signal of the NOR gate circuit G8 is set to the low level. As a result, the control signal S2 output from the inverter circuit N12 becomes high level at a relatively early timing, and the sense amplifiers SA8 to SA15 are activated. After the operation timing signal S2 of the sense amplifiers SA8 to SA15 is generated, the delay signal passing through the NOR gate circuit G9 and the inverter circuit N11 forming the delay circuit is delayed to the low level, and accordingly the NOR gate circuit G10 Output signal S
2'changes from low level to high level. As a result, the MOSFETs Q3 and Q4 are turned on with a delay, and the output signals of the sense amplifiers SA8 to SA15 are sent to the external terminals D0 to D7 via the output control NOR gate circuit G1. Even in such a read operation of the upper bits, the signal BH
The switch MOSFETs Q7 and Q8 are turned off by the low level of. As a result, the wiring leading to the NOR gate circuit G2 and its input capacitance are separated from the read signal transmission path of the higher-order bits, so that the signal transmission speed can be increased.

In this embodiment, in the 8-bit read operation, the sense amplifiers SA0 to SA7 and SA8 to SA15 are complementarily activated in response to the address signal Ai. In addition, the signals of the upper 8 bits simultaneously read by the addressing of the memory array do not appear as shown by the dotted line in FIG. As a result, the read signal can be output at high speed. Further, when the address signal Ai is switched and the upper bit and the lower bit are read by switching, the control signals S2 and S2 'that are switched from the selected state to the non-selected state as shown by the dotted line in the figure are at the low level at the same time when the address is switched. It is possible to separate the output terminals of the sense amplifiers SA8 to SA15 from the common signal path by setting them to the non-selection level. That is, the control signal S2 ′ (S1 ′) is formed by a NOR gate circuit that receives an input signal and its delay signal, so that its rising edge is delayed while its rising edge corresponds to that of the control signal S2 (S1). The low level can be immediately set in response to the change to the low level.
As a result, the 8-bit output operation can be performed at high speed.

A 16-bit output operation can be realized by setting the switching signal BHE to low level. In this case, since the output signal (BH) of the NOR gate circuit G3 is set to the high level together with the chip selection state, the switch circuit (Q7
And Q8) are turned on, and the NOR gate circuit G2 is opened. Then, the output signals of the NOR gate circuits G6 and G8 both become low level, and the control signals S1, S2 and S1 'are generated. As a result, the sense amplifiers SA0 to SA15 are activated, and the respective output signals are sent out from the terminals D0 to D15. At this time, since the output signal of the NOR gate circuit G9 forming the delay circuit is fixed to the low level due to the high level of the signal BH, the switch control signal S2 'is maintained at the low level. This keeps the switch MOSFETs Q3 and Q4 in the off state.

The operation and effect obtained from the above embodiment is as follows. That is, (1) a read signal composed of a plurality of bits is divided into a lower bit and an upper bit, each of which is supplied to a sense amplifier divided into two groups corresponding thereto, and the operation of these sense amplifiers is grouped. In accordance with the output switching control signal and the specific address signal in units of
By complementarily controlling the first and second switch circuits that switch the output signals of the sense amplifiers corresponding to the lower bit and the upper bit, respectively, at a timing delayed from the operation timing, Among them, when only the read signal of the above-mentioned divided number of bits is sent to the external terminal, there is a time difference between the operation of the sense amplifier and its output switching, so that only the true read signal is transmitted to the output signal path. The effect that high speed can be realized is obtained.

(2) By delaying only the rising edge of the control signal supplied to the first and second switch circuits, it is possible to achieve high-speed switch switching corresponding to address switching.

(3) When selectively outputting the high-order bit and the low-order bit, only the sense amplifier corresponding to the read signal to be output is brought into the operating state, so that the power consumption can be reduced. .

Although the present invention has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and it goes without saying that various modifications can be made without departing from the scope of the invention. For example, as an output circuit, an inverter circuit N in FIG. 1 is used in order to connect another mask type ROM or RAM with a wired OR configuration on a common data bus.
A three-state output circuit whose operation is controlled by an output enable signal formed by a chip selection signal or the like may be provided in the subsequent stage of 4, N5. Further, the memory array can adopt various embodiments such as one in which a plurality of bits are output from one memory array or a memory mat. The specific circuit configuration of the timing generation circuit that forms the timing signal of the switch circuit that sends the operation timing signal of the sense amplifier and the output signal thereof to the common output terminal at a delayed timing as described above is different from that of the various embodiments. Can be taken. The output bit number can take various modifications such as switching between 4 bits and 8 bits.

In addition to the mask type ROM, the present invention is provided with a function to switch the number of output bits as described above,
For example, it can be widely used for semiconductor memory devices such as EPROM (erasable programmable read only memory).

〔The invention's effect〕

The effect obtained by the representative one of the inventions disclosed in the present application will be briefly described as follows. That is, a read signal composed of a plurality of bits is divided into a lower bit and an upper bit, each of which is supplied to a sense amplifier which is divided into two groups, and the operation of these divided sense amplifiers is performed in group units. First control is performed at an early timing according to the output switching control signal and a specific address signal, and the output signals of the sense amplifiers corresponding to the lower bit and the upper bit are switch-controlled at a timing delayed from the operation timing. , Second
When the read signal of the divided bit number among the plurality of bits is sent to the external terminal by complementary control of the switch circuit of, a time difference is provided between the operation of the sense amplifier and its output switching. Since only the true read signal is transmitted to the output signal path, the speedup can be realized.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of an output circuit in a mask-type ROM to which the present invention is applied, and FIG. 2 is a timing chart for explaining an example of its operation. M0 to M15 …… Memory array, SA0, SA8 …… Sense amplifier,
SWC: Switch control circuit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Masayoshi Shirai 1450, Kamimizuhoncho, Kodaira-shi, Tokyo Inside Musashi Factory, Hitachi, Ltd. (72) Masahiro Ogata 1448, Kamisuihonmachi, Kodaira-shi, Tokyo Hitachi Ultra El・ SII Engineering Co., Ltd.

Claims (2)

[Claims] 1. A first set of sense amplifiers for receiving read signals divided into lower bit groups, and a second set of sense amplifiers for receiving read signals divided into upper bit groups, respectively. A first switch circuit for transmitting each of the output signals of the first set of sense amplifiers to an output node corresponding to the output signal of the lower bit group; and each of the output signals of the second set of sense amplifiers for the lower bit group Switch circuit for transmitting to the output node corresponding to the output signal of the above, and a third switch circuit for transmitting each of the output signals of the sense amplifiers of the second set to the output node corresponding to the output signal of the upper bit group. And a chip selection signal and an output switching control signal are supplied, and either half of the divided lower bit group or higher bit group A first logic gate circuit for forming a first control signal for instructing whether to perform an output operation of the above or a simultaneous output operation of the lower bit group and the upper bit group, the first control signal, the lower bit group, and the upper bit. A second signal which is valid only when an address signal designating any one of the groups is received and an output operation of either half of the divided lower bit group or upper bit group is performed. A second logic gate circuit for forming a control signal, and in the case of an output operation of the half bit group divided by the first control signal, the third switch circuit is produced by the first control signal. Of the first or second switch corresponding to the sense amplifier of either the first group or the second group is activated based on the second control signal. Times Is turned on, and when the lower bit group and the upper bit group are simultaneously output by the first control signal, the second switch circuit is kept off based on the second control signal, and After activating both the first and second sets of sense amplifiers by the first control signal, the corresponding first and second switch circuits are turned on. Storage device. 2. The first switch circuit is switch-controlled by a switch control signal formed by a third logic gate circuit which receives an activation signal of a first set of sense amplifiers and a delay signal thereof, and is turned off. Switching to the ON state is delayed corresponding to the delay signal, and the second switch circuit is configured by logically combining the activation signal of the second set of sense amplifiers with the first control signal. Is formed by a fourth logic gate circuit for receiving the delay signal and is controlled to be off by a switch control signal generated only when the control signal directs the output operation of the divided half bit group. The semiconductor memory device according to claim 1, wherein the switching from the ON state to the ON state is delayed corresponding to the delay signal.