JPH0794852A - Solder film forming method - Google Patents

Solder film forming method

Info

Publication number
JPH0794852A
JPH0794852A JP23934493A JP23934493A JPH0794852A JP H0794852 A JPH0794852 A JP H0794852A JP 23934493 A JP23934493 A JP 23934493A JP 23934493 A JP23934493 A JP 23934493A JP H0794852 A JPH0794852 A JP H0794852A
Authority
JP
Japan
Prior art keywords
solder
film
forming
copper circuit
solder film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP23934493A
Other languages
Japanese (ja)
Other versions
JP2531451B2 (en
Inventor
Eiji Maehata
栄治 前畑
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP5239344A priority Critical patent/JP2531451B2/en
Publication of JPH0794852A publication Critical patent/JPH0794852A/en
Application granted granted Critical
Publication of JP2531451B2 publication Critical patent/JP2531451B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Abstract

PURPOSE:To form a solder film by nonelectrolytic solder plating which can easily form uniform thickness without deterioration of solder wetability and short-circuit due to fused solder bridge, and is applicable to the mounting of present fine SMT parts. CONSTITUTION:The title method consists of the following; a process for forming a solder-plated resist film 2 on the copper circuit 1 of a printed wiring board, a process for forming a first solder film 3 having dense structure on the copper circuit 1 of the part where the solder-plated resist film 2 is not formed, a process for eliminating the solder-plated resist film 2, a process for forming a second solder film 4 having porous structure on the copper circuit 1 of the part where the first solder film 3 is not formed, and a process for fusing the first solder film 3 and the second solder film 4 and unifying them in an integral body by heating and for forming a solder film 5 on the copper circuit 1.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半田膜形成方法に関し、
特にプリント配線板における半田膜形成方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solder film forming method,
In particular, it relates to a method for forming a solder film on a printed wiring board.

【0002】[0002]

【従来の技術】プリント配線板の銅回路表面には、半田
付けや防食を目的として半田が被覆されている。従来の
プリント配線板の銅回路に半田を被覆する方法として
は、溶融半田めっき法が用いられている。この方法は、
一般的には、溶融半田浴に銅回路パターンが形成された
プリント配線板を浸漬した後、銅回路上に過剰に付着し
た半田を240℃程度に加熱された空気を吹き付けて除
去する方法である。
2. Description of the Related Art The surface of a copper circuit of a printed wiring board is coated with solder for the purpose of soldering and corrosion protection. As a conventional method for coating a copper circuit of a printed wiring board with solder, a molten solder plating method is used. This method
Generally, this is a method in which a printed wiring board having a copper circuit pattern formed thereon is dipped in a molten solder bath, and then solder excessively attached to the copper circuit is removed by blowing air heated to about 240 ° C. .

【0003】近年、表面実装技術の進展に伴い、プリン
ト配線板上に形成される半田膜は、均一かつ20μm程
度の膜厚が要求されており、溶融半田のめっき膜厚が
0.5〜30μmの範囲で大きくばらつくことが大きな
問題点となっている。溶融半田めっき法で形成された半
田膜が薄い場合には、銅−スズの合金層が半田膜表面に
拡散し半田濡れを著るしく損ね、逆に半田膜が厚い場合
には、プリント配線板の回路間隔が狭い部分で溶融半田
のブリッジによるショート不具合が多発するという問題
点があった。
In recent years, with the progress of surface mounting technology, a solder film formed on a printed wiring board is required to have a uniform thickness of about 20 μm, and a plating thickness of molten solder is 0.5 to 30 μm. A big problem is that there is a large variation within the range. When the solder film formed by the hot-dip solder plating method is thin, the copper-tin alloy layer diffuses on the surface of the solder film, which significantly impairs solder wetting. Conversely, when the solder film is thick, the printed wiring board However, there is a problem that short circuit problems frequently occur due to the bridge of the molten solder in the portion where the circuit interval is narrow.

【0004】一方、プリント配線板のパターンめっき法
でエッチングレジストとして使用される電気半田めっき
皮膜を再溶融することによって半田を形成する方法が実
施されているが、この場合、半田めっき皮膜の厚みを1
0μm以上にすることは、めっきレジストの厚みの制限
等から難かしい。その改善方法として、特開昭63−1
42893号公報に電気半田めっき上に半田ペースト等
により補助半田膜を形成後、再溶融することによって充
分な膜厚を有する半田膜を形成する方法が開示されてい
るが、スクリーン印刷技術の技術的制限により0.5m
mピッチのSMT(Surface Mount Te
chnology)部品パッドに対してこの技術を適用
することは難かしい。
On the other hand, a method of forming a solder by remelting an electric solder plating film used as an etching resist in a pattern plating method of a printed wiring board is practiced. In this case, the thickness of the solder plating film is reduced. 1
It is difficult to set the thickness to 0 μm or more because of the limitation of the thickness of the plating resist. As a method for improving it, Japanese Patent Laid-Open No. 63-1
Japanese Patent No. 428993 discloses a method of forming a solder film having a sufficient film thickness by forming an auxiliary solder film on an electric solder plating with a solder paste or the like and then remelting it. 0.5m due to restrictions
m pitch SMT (Surface Mount Te)
It is difficult to apply this technology to the chology) component pad.

【0005】[0005]

【発明が解決しようとする課題】以上説明した様に、従
来の溶融半田めっき方法は、均一な膜厚を有する半田膜
の形成が困難であり、半田濡れ性の劣化,溶融半田のブ
リッジによるショートといった問題点があった。
As described above, in the conventional hot-dip solder plating method, it is difficult to form a solder film having a uniform film thickness, the solder wettability is deteriorated, and a short circuit occurs due to a bridge of the hot-melt solder. There was a problem such as.

【0006】また、電気半田めっき法では、充分な半田
膜厚が得られないという問題点があり、充分な半田量を
半田ペースト等で補充する技術でも現在の微細なSMT
部品パッドには適用ができないという問題点があった。
In addition, the electric solder plating method has a problem that a sufficient solder film thickness cannot be obtained, and even with the technique of replenishing a sufficient amount of solder with a solder paste or the like, the present minute SMT is used.
There is a problem that it cannot be applied to component pads.

【0007】本発明の目的は、半田濡れ性の劣化や溶融
半田のブリッジによるショートがなく均一な半田膜の形
成が容易で、現在の微細なSMT部品パッドにも適用で
きる半田膜形成方法を提供することにある。
An object of the present invention is to provide a solder film forming method which can easily form a uniform solder film without deterioration of solder wettability and short circuit due to a bridge of molten solder and can be applied to the present minute SMT component pads. To do.

【0008】[0008]

【課題を解決するための手段】本発明の半田膜形成方法
は、プリント配線板の銅回路上にドライフィルムレジス
トを含む感光性レジストよりなる半田めっきレジスト膜
を被覆する工程と、この半田めっきレジスト膜が被覆さ
れていない部分の前記銅回路上に緻密質な構造を有する
薄付用無電解半田めっきを施し第1の半田皮膜を形成す
る工程と、前記半田めっきレジスト膜を除去する工程
と、前記第1の半田皮膜が形成されていない部分の前記
銅回路上に多孔質な構造を有する厚付け用無電解半田め
っきを施し第2の半田皮膜を形成する工程と、加熱によ
り前記第1の半田皮膜と前記第2の半田皮膜とを溶融一
体化し前記銅回路上に半田膜を形成する工程とを含む。
A method for forming a solder film according to the present invention comprises a step of coating a copper circuit of a printed wiring board with a solder plating resist film made of a photosensitive resist containing a dry film resist, and the solder plating resist. A step of forming a first solder film by applying thin electroless solder plating having a dense structure on the copper circuit in a portion where the film is not covered; a step of removing the solder plating resist film; A step of forming a second solder coating by applying electroless solder plating for thickening having a porous structure on a portion of the copper circuit where the first solder coating is not formed; and heating the first solder coating. A step of melting and integrating a solder film and the second solder film to form a solder film on the copper circuit.

【0009】[0009]

【実施例】次に、本発明の実施例について図面を参照し
て説明する。
Embodiments of the present invention will now be described with reference to the drawings.

【0010】図1(a)〜(e)は本発明の第1の実施
例を説明する工程順に示した断面図である。本発明の第
1の実施例は、まず、図1(a)に示す様に、サブトラ
クティブ法等により幅0.3mmの銅回路1を0.3m
mのピッチで形成し、銅回路1間にスクリーン印刷等に
より半田保護膜6を印刷しプリント配線板を形成する。
次に、図1(b)に示す様に、膜厚50μmの感光性ド
ライフィルムレジストをラミネートし、露光,現象によ
り銅回路中央部に幅0.2mmの半田めっきレジスト膜
2を形成する。
1 (a) to 1 (e) are sectional views showing the first embodiment of the present invention in the order of steps. In the first embodiment of the present invention, first, as shown in FIG. 1A, a copper circuit 1 having a width of 0.3 mm is 0.3 m thick by a subtractive method.
Formed at a pitch of m, a solder protective film 6 is printed between the copper circuits 1 by screen printing or the like to form a printed wiring board.
Next, as shown in FIG. 1B, a photosensitive dry film resist having a film thickness of 50 μm is laminated, and a solder plating resist film 2 having a width of 0.2 mm is formed in the central portion of the copper circuit by exposure and phenomenon.

【0011】次に、図1(c)に示す様に、このプリン
ト配線板に前処理として過酸化水素水溶液で30℃、1
分間のエッチングを行い水洗処理後、液温55℃の薄付
用無電解半田めっき液に約30間浸漬し、約3μmの緻
密質な構造を有する第1の半田皮膜3を得た。薄付用無
電解半田めっき液としては、チオ尿素100g/l,ホ
ウフッ化スズ0.1mol/l,フッ化鉛0.03mo
l/lの組成のものを用いた。次に、図1(d)に示す
様に、半田めっきレジスト膜2をドライフィルムレジス
ト剥離液により除去した後、厚付用無電解半田めっき液
に約1時間浸漬し約20μmの多孔質な第2の半田皮膜
4を得た。厚付用無電解半田めっき液としては、上村工
業(株)のビームソルダーPCを用いた。その後、図1
(e)に示す様に、200℃の溶融油に約20秒間浸漬
し第1の半田皮膜3と第2の半田皮膜4を溶融一体化さ
せ20μmの膜厚を有する半田膜5を得た。
Next, as shown in FIG. 1 (c), this printed wiring board is pretreated with an aqueous solution of hydrogen peroxide at 30 ° C. for 1 hour.
After etching for 1 minute and washing with water, it was dipped in an electroless solder plating solution for thinning at a liquid temperature of 55 ° C. for about 30 minutes to obtain a first solder film 3 having a dense structure of about 3 μm. As an electroless solder plating solution for thinning, thiourea 100 g / l, tin borofluoride 0.1 mol / l, lead fluoride 0.03 mo
A composition of 1 / l was used. Next, as shown in FIG. 1 (d), after removing the solder plating resist film 2 with a dry film resist stripping solution, the solder plating resist film 2 is immersed in an electroless solder plating solution for thickening for about 1 hour to form a porous first layer of about 20 μm. A solder film 4 of 2 was obtained. As the electroless solder plating solution for thickening, a beam solder PC manufactured by Uemura Industry Co., Ltd. was used. Then, Figure 1
As shown in (e), the first solder film 3 and the second solder film 4 were melt-integrated by immersing in a molten oil at 200 ° C. for about 20 seconds to obtain a solder film 5 having a film thickness of 20 μm.

【0012】この結果、図1(d),(e)に示す様
に、銅回路1の表面は凹状となり、凹部の半田膜5の厚
みは約20μm,凹部肩部分の半田膜5の厚みは約3μ
mとなった。これは、第1の半田皮膜3が緻密質な構造
を有しているため、第2の半田皮膜4形成時にめっき液
が銅回路1の銅と置換反応を生じることがないため、第
2の半田皮膜4は第1の半田皮膜3に被覆されていな銅
回路1上のみに析出するためである。
As a result, as shown in FIGS. 1 (d) and 1 (e), the surface of the copper circuit 1 is concave, the thickness of the solder film 5 in the concave portion is about 20 μm, and the thickness of the solder film 5 in the shoulder portion of the concave portion is About 3μ
It became m. This is because the first solder film 3 has a dense structure, and therefore the plating solution does not cause a substitution reaction with the copper of the copper circuit 1 when the second solder film 4 is formed. This is because the solder film 4 is deposited only on the copper circuit 1 which is not covered with the first solder film 3.

【0013】図2(a)〜(e)は本発明の第2の実施
例を説明する工程順に示した断面図である。本発明の第
2の実施例は、図2(a)〜(e)に示す様に、幅が
0.3mmの銅回路1上に0.3mm幅の半田めっきレ
ジスト膜2を形成した以外は、図1(a)〜(e)に示
す第1の実施例と同じである。第2の実施例では、図2
(d),(e)に示す様に、銅回路1の断面は長方形に
なり、厚み約18μmの半田膜5が銅回路1上に均一に
形成された。一方、第1の半田皮膜3と第2の半田皮膜
4の濡れ性が良いため、隣接する銅回路1同士のブリッ
ジによるショートや半田ボール等の不具合の発生は皆無
であった。
FIGS. 2A to 2E are sectional views showing the second embodiment of the present invention in the order of steps. In the second embodiment of the present invention, as shown in FIGS. 2A to 2E, a solder plating resist film 2 having a width of 0.3 mm is formed on a copper circuit 1 having a width of 0.3 mm. The same as the first embodiment shown in FIGS. 1 (a) to 1 (e). In the second embodiment, FIG.
As shown in (d) and (e), the copper circuit 1 had a rectangular cross section, and the solder film 5 having a thickness of about 18 μm was uniformly formed on the copper circuit 1. On the other hand, since the first solder film 3 and the second solder film 4 have good wettability, no defects such as short circuits and solder balls due to bridges between adjacent copper circuits 1 occurred.

【0014】[0014]

【発明の効果】以上説明した様に本発明は、銅回路上に
緻密質な構造を有する第1の半田皮膜と、第1の半田皮
膜が形成されていない銅回路上に多孔質な構造の第2の
半田皮膜を形成し、加熱により第1の半田皮膜と第2の
半田皮膜とを溶融一体化し銅回路上に半田膜を形成する
ことにより、半田濡れ性の劣化や溶融半田のブリッジに
よるショートがなく均一な半田膜の形成が容易で、現在
の微細なSMT部品の実装にも適用できる半田膜形成方
法を提供できるという効果がある。
As described above, according to the present invention, the first solder film having a dense structure on the copper circuit and the porous structure on the copper circuit on which the first solder film is not formed are provided. By forming a second solder film and heating and melting the first solder film and the second solder film to form a solder film on the copper circuit, deterioration of solder wettability and bridge of molten solder may occur. There is an effect that it is possible to provide a solder film forming method which can easily form a uniform solder film without short circuit and can be applied to the mounting of the present minute SMT components.

【図面の簡単な説明】[Brief description of drawings]

【図1】(a)〜(e)は本発明の第1の実施例を説明
する工程順に示した断面図である。
1A to 1E are cross-sectional views showing a process sequence for explaining a first embodiment of the present invention.

【図2】(a)〜(e)は本発明の第2の実施例を説明
する工程順に示した断面図である。
2 (a) to 2 (e) are sectional views showing a second embodiment of the present invention in the order of steps.

【符号の説明】[Explanation of symbols]

1 銅回路 2 半田めっきレジスト膜 3 第1の半田皮膜 4 第2の半田皮膜 5 半田膜 6 半田保護膜 1 Copper Circuit 2 Solder Plating Resist Film 3 First Solder Film 4 Second Solder Film 5 Solder Film 6 Solder Protective Film

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 プリント配線板の銅回路上に半田めっき
レジスト膜を被覆する工程と、この半田めっきレジスト
膜が被覆されていない部分の前記銅回路上に薄付用無電
解半めっきを施し第1の半田皮膜を形成する工程と、前
記半田めっきレジスト膜を除去する工程と、前記第1の
半田被膜が形成されていない部分の前記銅回路上に厚付
用無電解半田めっきを施し第2の半田皮膜を形成する工
程と、加熱により前記第1の半田被膜と前記第2の半田
被膜とを溶融一体化し前記銅回路上に半田膜を形成する
工程とを含むことを特徴とする半田膜形成方法。
1. A step of coating a solder plating resist film on a copper circuit of a printed wiring board, and a thin electroless half-plating for thinning is applied to a portion of the copper circuit not covered by the solder plating resist film. No. 1 step of forming a solder film, a step of removing the solder plating resist film, and a step of applying thick electroless solder plating on the copper circuit in a portion where the first solder film is not formed, And a step of forming a solder film on the copper circuit by melting and integrating the first solder film and the second solder film by heating. Forming method.
【請求項2】 前記半田めっきレジスト膜がドライフィ
ルムレジストを含む感光性レジストであることを特徴と
する請求項1記載の半田膜形成方法。
2. The method for forming a solder film according to claim 1, wherein the solder plating resist film is a photosensitive resist including a dry film resist.
【請求項3】 前記第1の半田皮膜が緻密質な構造を有
することを特徴とする請求項1記載の半田膜形成方法。
3. The solder film forming method according to claim 1, wherein the first solder film has a dense structure.
【請求項4】 前記第2の半田皮膜が多孔質な構造を有
することを特徴とする請求項1記載の半田膜形成方法。
4. The method for forming a solder film according to claim 1, wherein the second solder film has a porous structure.
JP5239344A 1993-09-27 1993-09-27 Solder film forming method Expired - Fee Related JP2531451B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5239344A JP2531451B2 (en) 1993-09-27 1993-09-27 Solder film forming method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5239344A JP2531451B2 (en) 1993-09-27 1993-09-27 Solder film forming method

Publications (2)

Publication Number Publication Date
JPH0794852A true JPH0794852A (en) 1995-04-07
JP2531451B2 JP2531451B2 (en) 1996-09-04

Family

ID=17043349

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5239344A Expired - Fee Related JP2531451B2 (en) 1993-09-27 1993-09-27 Solder film forming method

Country Status (1)

Country Link
JP (1) JP2531451B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6806939B2 (en) * 1999-07-02 2004-10-19 Seiko Instruments Inc. Display device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6806939B2 (en) * 1999-07-02 2004-10-19 Seiko Instruments Inc. Display device

Also Published As

Publication number Publication date
JP2531451B2 (en) 1996-09-04

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