JPH0793220A - Virtual memory managing system - Google Patents

Abstract

PURPOSE:To accelerate address translation processing at a shared bus coupled parallel computer system. CONSTITUTION:Inside a shared memory control circuit 12, an address translation circuit common for each PE is composed of a microcomputer 121 and a control memory 122. A cache 41 is accessed by a logical address designated by a memory access request issued from a processor 40 and when requested data are not held there, a data transfer request command containing the logical address designated by that access request is sent to a shared bus 2. When a block containing those data is held at the other PE, that block is transferred to the request source PE. When the block is held at no PE, the shared memory control circuit 12 converts this logical address to a physical address, reads out that block of a shared memory 1 and transfers it through the shared bus 2 to the request source PE.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a virtual memory management system in a shared bus coupled parallel computer system.

[0002]

2. Description of the Related Art Conventionally, "Symmetry Tec
hnical Summary ”(Sequent, USA, Manual 1003-4
7396-00, pp2.2-2.5, 1987).

In the above-mentioned prior art, a cache memory is provided in each of a plurality of processors coupled to a shared memory by a shared bus, an address translation device is provided in each processor, and a logic for a memory operand specified by a program is provided. The address is translated into a corresponding physical address by this address translation device, and the cache in the processor is accessed with this physical address. If this memory operand is not in the cache,
Sends a data transfer command specifying its physical address to the shared bus, and if there is another processor holding that data in the cache, that processor transfers that data to the requesting processor via the shared bus. Has become.

For this address translation, each processor reads the address translation table held in the shared memory, translates the logical address into a physical address in its own processor, and the logical address and the translated physical address. Is stored in the address translation buffer. This translation buffer is used later when the same logical address is translated into a physical address.

When the processor accesses the page table in the shared memory 1 to translate a logical address not registered in the address translation buffer into a physical address, the data corresponding to the logical address is stored in the shared memory. It may not be registered. At this time, the processor generates a page fault exception. In response to this signal, the shared memory allocates the physical memory to the logical address, but at this time, the allocation of the real memory address already allocated to one of the logical addresses is released, and the data of that address is saved. Paged out to auxiliary memory. Therefore, in order to invalidate this logical address / physical address pair, the processor invalidates the address translation buffer included in itself and invalidates the contents of the address translation buffer to all other processors. A command requesting conversion is transferred via the shared bus.

[0006]

In the above prior art, when a page fall occurs, the entire address translation buffer of all the processors is invalidated, so that each of the processors does not deal with the subsequent address translation. It is necessary to access the shared memory each time.

Since this access is performed via the shared bus, more contention occurs with respect to the right to use this shared bus, and the address translation becomes slower.

It is an object of the present invention to solve the above problems and realize high-speed virtual memory management even when a page fault occurs in a shared bus coupled parallel computer system.

[0009]

In order to achieve the above object, according to the present invention, each processor has a cache memory accessible at a logical address specified by a memory access request issued by a processing device. The cache memory, when the data requested by the access request is not held in the cache memory, means for sending a data transfer request command including the logical address specified by the access request to the shared bus, and other means. If the data block containing the data of the logical address specified by the data transfer request sent from the processor to the shared bus is held in the cache memory of the processor, and the data block is held Has
And a means for transferring the data block to the requesting processor via the shared bus, wherein the shared memory control circuit, the shared memory control circuit, the logical address sent from any of the plurality of processors via the shared bus, A means for accessing the address conversion table in the shared memory and converting it to a corresponding physical address, and a data block including the data of the logical address specified by the data transfer request is not transferred to the bus from any processor. A means for reading the data block from the shared memory based on the physical address obtained by the converting means for the logical address, and transferring the data block to the requesting processor via the shared bus. Have.

[0010]

Since each processor is not provided with the address translation means, but the shared memory control circuit is provided with the address translation means common to a plurality of processors, the shared bus shares information for address translation from each processor. There is no need to transfer to the memory control circuit or in the opposite direction, contention at the time of transfer of these information on the shared bus is reduced, and the address conversion itself is speeded up.

[0011]

1 is a block diagram of a parallel computer system according to the present invention. This system includes processors PE0 to PE
It is a memory sharing type multiprocessor in which E2 and the shared memory 1 are connected by a shared bus 2. The shared memory 1 is connected to the shared bus 2 via the shared memory control circuit 12, and is connected to the disk device 3 via the I / O interface circuit 13.

The shared memory 1 has data 1 of each page.
4. It has a page table 11 in addition to key information 15 for each page data. In this embodiment, one page is composed of 4 words. Of each key information, the figure shows a change bit C and a reference bit R used for page replacement. Of these, the C bit indicates whether or not the content of the corresponding page has been updated, and the R bit is information known per se indicating whether or not the corresponding page has been referenced.

The page table 11 has, for each page data, a valid flag, a logical address and a physical address,
Register page information consisting of UIC (Unused Interval Counter). Here, the UIC is information known per se, which indicates a system or time since the corresponding page was recently referred to the present time.

The shared memory control circuit 12 is a microcomputer 12
1 and a control memory 122 for holding a micro program for controlling this microcomputer. This microcomputer 121
Accesses the data 14 or the key information 15 in the shared memory 1 and the page table 11. In particular, this microcomputer realizes an address conversion circuit. That is, referring to this page table, a logical address is translated into a corresponding physical address, and an address translation buffer (not shown) holding a translation pair of the logical address and the physical address obtained by such translation is built-in. is doing. The details will be described later.

The shared memory control circuit 12 sets the effective bit of the page table to 1 every one million cycles, for example.
Of all the entries, the UIC is incremented by 1 for the page whose R bit is "0", and the UIC and R bit are reset to 0 for the page whose R bit is "1".

Each processor has a CPU 40 and a cache 41, 42 or 43. Each processor does not have an address conversion circuit. Therefore, a logical address is designated as an address for memory access from the CPU 40. Each cache holds cache block data having a size of 2 words and cache block information including a valid flag, a cache state, and a logical address for the block data. The cache status is
When the valid flag of the block data is on, information indicating whether or not the data is updated after being registered in the cache and whether or not the data is held in the cache of another processor (that is, Information indicating whether or not the data is shared with another processor).

The operation of the system according to this embodiment will be described below.

(1) Data read (1a) Any processor, for example, C in PE1
When the PU 40 issues a memory data read request and the block containing the data of the logical address designated by the request exists in the cache of the processor, for example, 41, the requested data is read to the block and the CPU 40 is read. Transfer and terminate the processing of the request.

(1b) However, when the block containing the requested data does not exist in the cache,
The processor sends to the shared bus 2 a data transfer request command including the logical address specified by the request.

In response to this command, each of the other processors determines whether or not there is a block containing the data of this logical address in its cache, and if there is, the block is shared via the shared bus 2. To the requesting processor. At this time, the transfer source processor changes the state of the data block in the cache to the unchanged state and the shared state.

On the other hand, the requesting processor is the shared bus 2
Registers the block transferred via () in its own cache. At this time, the cache state of this block is set to the shared state. Further, the data of the requested logical address in the block is transferred to the CPU.

(1c) On the other hand, when this block is not in the cache from any of the other processors and the transfer of this block cannot be performed from any of the processors,
The shared memory control circuit 12 transfers the block requested by the transfer request command from the shared memory 1 to the request source processor.

Prior to this transfer, the logical address designated by this transfer request command is converted into a corresponding logical address. The method is as follows.

That is, in converting this logical address into a physical address, an address conversion buffer (not shown) provided in the shared memory control circuit 12 is referred to, and a pair of the physical address corresponding to this logical address is stored therein. If registered, the physical address corresponding to the logical address is read and used as the converted address. If the pair is not registered in this address translation buffer, the page table 11 of the shared memory is accessed, the pair of the physical address corresponding to the logical address is read, and the read physical address is set as the translated address. To use. Further, this read pair is registered in the address translation buffer.

The shared memory control circuit 12 thus converts the logical address into a physical address, reads the block data including the data of the physical address from the shared memory 1 by using the converted physical address, and requests the block data of the request source. Transfer to processor. Further, the reference bit R for this page in the shared memory 1 is set to 1 (reference state).

It is possible that a page containing the data of this physical address does not exist in the shared memory (page fault), but the processing in that case will be described later.

(2) Writing of data (2a) Either processor, for example, C in PE1
When the PU 40 issues a memory data write request, if the block containing the data of the logical address specified by the request exists in the cache of the processor, for example, 41, the data transferred from the CPU to the block. Write.

Further, when the state of the block is the shared state, the invalidation command designating this logical address is transferred to the shared bus 2. At this time, the other processor, in response to this command, determines whether or not it holds this block in its own cache, and the other processor that determines that it holds this block will Invalidate the block.

On the other hand, in response to this command, the shared memory control circuit 12 changes the C bit of the page including this block to the 1 (rewritten) state.

In the processor that has executed the write request,
Change the block in the processor to unmodified and unshared.

(2b) However, when the block containing the write-requested data does not exist in the cache in the processor in which the request was issued, the processor assigns the shared bus 2 the logical address specified by the request. A data transfer request command for requesting transfer of data at the address and invalidation of the data after the transfer is sent.

That is, in response to this command, the other processor performs the same operation as described in (1b) above, and the block containing the data is held in the cache of any of the other processors. Sometimes, the processor transfers the block to the requesting processor and, after the transfer of the data, invalidates the data in the same manner as described in (2a) above.

On the other hand, the requesting processor registers the transferred block in its own cache. At this time, the state in the cache of this block is changed to the non-shared state.

(2c) On the other hand, if there is no block containing the data requested by this data transfer request command in the cache of any other processor, the shared memory control circuit 12 causes the block requested by this transfer request command. From the shared memory 1 to the request source processor. The method is the same as the method described in (1c) above.

Thereafter, the request source processor writes the data designated by the write request into the transferred block. However, unlike the case of (2a) above, the invalidation command is not transmitted.

Even in the case of this (2c), the page including the data of this physical address may not exist in the shared memory (page fault), but the processing in that case will be described later.

(3) Processing at the time of page fault FIG. 2 is a detailed flow of the block transfer operation by the shared memory control circuit 12 according to the present invention.

(3a) In the above (1c) or (2c), when the data transfer request command is transferred to the shared bus and the block is not in the cache in any other processor, the shared memory control circuit 12 In transferring the block requested by the data transfer request, first, it is determined whether the block having the logical address specified by the request is assigned a physical address in the shared memory 1 (step c1).

In this page fault judgment c1, it is determined whether or not the data corresponding to the relevant logical address exists in the shared memory, and whether or not the valid flag corresponding to the logical address of the page table 11 is "1" (valid). Determined by

(3b) When it is determined that the block is assigned a physical address, that is, it is not a page fault, the block is transferred as described above (step c5).

(3c) However, when no physical address is assigned to the logical address, that is, when a page fault occurs, the shared memory control circuit 12 selects one page to be replaced in the replacement page selection processing c2. To do. For example, a page with a valid flag of 1 and a maximum UIC value is selected.

The shared memory control circuit 12 further transfers a swap-out request command requesting write-back of each of a plurality of blocks included in the selected page to each processor via the shared bus 2. In response to this command, each processor determines whether or not the block designated by the command is held in the cache in its own processor, and if so, the block has been rewritten. Whether or not it is judged from the information indicating the cache state of the block, and if it has been rewritten, the block is written back to the shared memory 1 via the shared bus 2.

If there is even one block written back in this way, the shared memory control circuit 12 changes the C bit of the selected page to 1.

(3d) The shared memory control circuit 12 executes the process c3. That is, C of this selected page
When the bit becomes 1, this page is paged out to the disk device 3 via the I / O interface circuit 13. When the value of this C bit is "0", this page out is not performed.

After that, the shared memory control circuit 12 allocates a physical address to the block designated by the data transfer request, and transfers the block from the disk device 3 to the position of the physical address in the shared memory 1.

(3e) The shared memory control circuit 12 updates the page table in process c4. That is, the logical address designated by the data transfer request command, the physical address assigned to it, and the valid flag are set to "1" (valid). The valid flag of the entry relating to the replaced page is reset to "0" (invalid).

At the same time, the shared memory control circuit 12 invalidates the entry relating to the replaced page in the address translation buffer contained therein, and is assigned to the logical address requested for data transfer and the address. Register the pair with the registered physical address.

(3f) The shared memory control circuit 12 selects the block containing the data of the logical address designated by the data transfer request command among the pages paged in as described above in (1c) or (2c). And transfer to the requesting processor.

As described above, in this embodiment, since the block requested to be transferred by each processor is not held by a plurality of processors, the block is shared by the shared memory 1.
By rewriting the R bit in the shared memory 1 only when reading from, the frequency of rewriting the R bit is reduced.

Similarly, in this embodiment, when a block in one of the processors is requested to be invalidated by a data invalidation command issued by each processor, and when the block rewritten in the shared memory is set in the shared memory. By rewriting the C bit in the shared memory 1 for the page including these blocks only at the time of writing back, the frequency of rewriting the C bit is reduced.

As is clear from the above, in the present embodiment,
The conversion from the logical address to the physical address is not performed by each processor, is performed by the shared memory control circuit 12, and the address translation conversion buffer is not separately provided for each processor.
The shared memory control circuit 12 is provided commonly to each processor.

As a result, it is not necessary to transfer the contents of the page table in the shared memory between each processor and the shared memory control circuit, and delay of address translation due to contention of the shared bus can be prevented.

Furthermore, it is not necessary to purge the address translation buffer in each processor when a page fault occurs, which occurs when each processor is provided in the related art. Delays due to contention for use are reduced.

After all, in the present embodiment, there is no need to use the shared bus in relation to the address conversion or related thereto.

As in the case of (1b) or (2b) above, a data transfer request command is issued from either processor, and the block containing the requested data is transferred from any processor to the request source. Also in this case, the present embodiment can be modified so that the virtual memory control error is detected by causing the shared memory control circuit 12 to determine whether or not the page including the block of the shared memory 1 is invalid. Is.

[0056]

According to the present invention, the address conversion means is not provided in each processor, but the shared memory control circuit is provided with the address conversion circuit common to a plurality of processors.
The shared bus does not need to transfer information for address translation from each processor to the shared memory control circuit or vice versa, which reduces contention during the transfer of such information on the shared bus, and the address translation itself. Will be faster.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an embodiment of a parallel computer system according to the present invention.

FIG. 2 is a flowchart of control executed by a shared memory control circuit of the apparatus of FIG. 1 when a page fault occurs.

[Explanation of symbols]

 1 ... shared memory, 2..shared bus.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Tokuyasu Imon Tokuyasu 1-280, Higashi Koigokubo, Kokubunji City, Tokyo Inside the Central Research Laboratory, Hitachi, Ltd.

Claims (2)

[Claims] 1. A plurality of processors coupled to a shared bus, a shared memory shared by the plurality of processors, and a shared memory control circuit connected to the shared bus and controlling access to the shared memory. Each processor has a processor and a cache memory accessible at a logical address specified by a memory access request issued by the processor, and the cache memory stores the data requested by the access request. Is stored in the cache memory, means for sending a data transfer request command containing the logical address specified by the access request to the shared bus, and data transfer sent from the other processor to the shared bus. A data block containing the data of the logical address specified by the request is stored in the cache memory of the processor. The shared memory control circuit, the shared memory control circuit includes a means for detecting whether the data block is held, and transferring the data block to the requesting processor via the shared bus when the data block is held. A means for converting a logical address sent from any of the plurality of processors via the shared bus into a corresponding physical address by accessing an address conversion table in the shared memory; When a data block including data of a designated logical address is not transferred to the bus from any processor, the data block is shared based on the physical address obtained by the conversion means for the logical address. Virtual memory having means for reading from the memory and transferring the data block to the requesting processor via the shared bus Management method. 2. The shared memory control circuit, when any page data including data of a logical address designated by the data transfer request is not stored in the shared memory, holds the shared memory. A cache of each processor, comprising means for selecting page data for page out, and means for requesting the plurality of processors to write back a plurality of blocks belonging to the selected page data to the shared memory. The memory holds the write-back requested data block in its cache memory,
Further, the shared memory control circuit has means for determining whether the data block has been rewritten, and writing back the rewritten block held in the cache memory to the shared memory via the shared bus. Means for page-out of the selected page data to an auxiliary storage device connected to the shared memory control circuit when at least one rewritten block is written back to the shared memory from the plurality of processors, Means for page-in of page data including data of a logical address designated by the data transfer request from the auxiliary storage device into the shared memory, and data designated by the logical address of the page-in page data And a means for transferring a block including the block to the requesting processor via the shared bus. Memory management method.