JPH0786507A - Semiconductor device and fabrication thereof - Google Patents

Abstract

PURPOSE:To provide a semiconductor device and a method of fabrication of the same, the device including a coil for an analog circuit, a spring of micromachining, and a fine spiral pattern capable of being utilized for a flagellate motor, etc. CONSTITUTION:An insulating layer 2 is formed on a semiconductor substrate 1, and a first wiring layer 3 is formed on the insulating layer 2. A layer insulating layer 5 is formed on the first wiring layer 3, and a second wiring layer 7 is formed on the layer insulating layer 5 which serves to connect one ends of the adjacent first wiring layer 3 and the other end of the first wiring layer 3 so as to surround the layer insulating layer 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a minute spiral pattern and a manufacturing method thereof. The minute spiral pattern is used for coils such as analog circuits,
It can be used as a spring for micromachining, a bristle motor, and the like.

[0002]

2. Description of the Related Art In recent years, the demand for higher integration of analog LSIs has increased, and miniaturization of analog elements has been studied.
Elements used in analog LSIs include capacitors, resistors, and coils. Among these, the capacitance and the resistance have been miniaturized, but the coil has not been miniaturized. Therefore, when the coil is used as the element, it must be an external component.

Therefore, in the conventional analog circuit, L
Since it is necessary to externally attach a coil component having a size larger than that of the SI chip, it is not possible to downsize the entire analog circuit even if the analog LSI is miniaturized. For this reason, for example, in a power supply circuit, in order to make external components such as a transformer and a core thin and small, an unreasonable circuit configuration that raises the operating frequency has been used for miniaturization. But,
Forcibly increasing the switching frequency increases power loss, and heat generation from the transformer or core becomes a serious problem.

Moreover, even if such an unreasonable circuit structure is used for miniaturization, at present, it is assumed that the Mn--Zn type ferrite or Co type amorphous alloy foil strip, which is under development for 1 MHz, is used. The core could be miniaturized only to a diameter of 5 mmφ and a height of about 5 mm, and there was a limit to the size of an LSI chip for a switching regulator.

Most of the power loss in the power supply circuit is switching loss and iron loss of the magnetic material used for the transformer core. Regarding iron loss, eddy current loss is more dominant than hysteresis loss during high frequency operation. this is,
This is because as the frequency increases, the electrical resistance of the material decreases and eddy currents easily flow. As measures against such eddy current loss, in the case of Mn—Zn-based ferrite and Co-based amorphous alloy foil strips, the thickness of the foil strip is reduced, and the particles constituting the material are reduced to increase the surface area of the particles. We are making efforts such as increasing electric resistance. As a result, trial manufacture of a film thickness of 1 to 5 μm has been succeeded at present.

In medical micromachining, springs and actuators having a size of several tens of μm or less are required. In the case of an actuator having a size of several tens of μm, the resistance becomes larger than the inertia, and therefore the conventional motor or piston cannot drive the actuator. Therefore, the use of a flagellar motor, which is used by bacteria, is being studied.

[0007]

As described above, in the conventional analog circuit technology, the most advanced technology is used to miniaturize the external parts such as the coil, the transformer and the core. As long as components are used, there was a limit to downsizing the entire analog circuit. Therefore, it has been expected to form a minute spiral pattern on an LSI chip.

Further, although the use of a beveled hair motor has been studied in micromachining, it requires a minute spiral pattern, and it is required to easily manufacture such a minute spiral pattern. It was The present invention has been made in view of the above circumstances, and an object thereof is to provide a semiconductor device having a minute spiral pattern and a method for manufacturing the same.

[0009]

The above object is to provide a semiconductor substrate, an insulating layer formed on the semiconductor substrate, a plurality of first wiring layers formed on the insulating layer, and the first wiring layer. A second wiring layer formed above the wiring layer and connecting one end of the first wiring layer and the other end of the first wiring layer adjacent to each other, the first wiring layer and the second wiring layer; This is achieved by a semiconductor device characterized in that a spiral pattern is formed by the second wiring layer.

The above-described semiconductor device further includes an interlayer insulating layer formed between the first wiring layer and the second wiring layer, and the interlayer wiring layer is formed by the first wiring layer and the second wiring layer. It is desirable that a spiral pattern surrounding the insulating layer is formed. The semiconductor device described above further includes a magnetic layer formed in the interlayer insulating layer and penetrating the spiral pattern, and the spiral surrounding the magnetic layer by the first wiring layer and the second wiring layer. It is desirable that the pattern is formed.

In the semiconductor device described above, it is preferable that the insulating layer is formed in a concave shape, and the first wiring layer is formed in a concave shape on the concave portion of the insulating layer. In the semiconductor device described above, it is preferable that a convex portion is formed on the upper surface of the interlayer insulating layer, and the second wiring layer is concavely formed on the convex portion of the interlayer insulating layer.

In the above-mentioned semiconductor device, it is desirable that the first wiring layer and the second wiring layer are connected to each other through a connection hole or a groove formed in the interlayer insulating layer. The above-mentioned objects include a step of forming an insulating layer on a semiconductor substrate, a step of forming a plurality of first wiring layers on the insulating layer, and a step of forming an interlayer insulating layer on the first wiring layer. Forming a second wiring layer on the interlayer insulating layer so as to surround the interlayer insulating layer and connect one end of the first wiring layer and the other end of the first wiring layer adjacent to each other. And a method for manufacturing a semiconductor device.

In the method of manufacturing a semiconductor device described above,
It is desirable to further include a step of removing the interlayer insulating layer surrounded by the first wiring layer and the second wiring layer. The purpose is to form an insulating layer on a semiconductor substrate, to form a plurality of first wiring layers on the insulating layer, and to form a first interlayer insulating layer on the first wiring layer. And a step of forming a magnetic layer that extends in a direction intersecting the first wiring layer on the first interlayer insulating layer, and a second interlayer insulating layer on the magnetic layer. And a step of connecting one end of the first wiring layer and the other end of the first wiring layer adjacent to each other so as to surround the magnetic layer on the second interlayer insulating layer. And a step of forming two wiring layers.

In the method of manufacturing a semiconductor device described above,
It is preferable that the method further includes the step of etching the insulating layer to form a concave portion on the upper surface, and forming a plurality of concave first wiring layers on the concave portion of the insulating layer. In the method for manufacturing a semiconductor device described above, the method further includes the step of forming a convex portion on the upper surface of the interlayer insulating layer in a region where the second wiring layer is to be formed. On the department
It is desirable to form the second wiring layer in a concave shape. The method for manufacturing a semiconductor device described above, further comprising a step of forming connection holes or grooves on both ends of the first wiring layer of the interlayer insulating layer, and forming the second wiring layer on the interlayer insulating layer. It is desirable to form and connect to the first wiring layer through the connection hole or groove of the interlayer insulating layer.

[0015]

According to the present invention, a semiconductor substrate, an insulating layer formed on the semiconductor substrate, a plurality of first wiring layers formed on the insulating layer, and formed on the first wiring layer, Since it has the second wiring layer that connects one end of the first wiring layer and the other end of the first wiring layer adjacent to each other, the spiral pattern is formed by the first wiring layer and the second wiring layer. Are formed.

Further, according to the present invention, an insulating layer is formed on the semiconductor substrate, a plurality of first wiring layers are formed on the insulating layer, and an interlayer insulating layer is formed on the first wiring layer. Since the second wiring layer which connects one end of the first wiring layer and the other end of the first wiring layer which are adjacent to each other is formed on the interlayer insulating layer so as to surround the interlayer insulating layer, the first wiring layer is formed. A spiral pattern can be formed by the wiring layer and the second wiring layer.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device and a method of manufacturing the same according to a first embodiment of the present invention will be described with reference to FIGS.
First, the insulating layer 2 made of a silicon oxide film having a thickness of about 1 μm is formed on the semiconductor substrate 1 by the CVD method. Subsequently, an Al thin film or Cu thin film having a thickness of about 0.5 μm is deposited by the sputtering method. Subsequently, a resist (not shown) is patterned by a normal photolithography technique, and Al is formed by an RIE method using the patterned resist as a mask.
The thin film or the Cu thin film is patterned to form the lower wiring layer 3 which will be the lower part of the spiral pattern. A plurality of lower wiring layers 3 having a width of about 1 μm are arranged at intervals of about 1 μm (for example, 10
(00 lines) are formed (FIG. 1A).

Next, an interlayer insulating layer 5 made of a silicon oxide film having a thickness of about 1 μm is deposited on the lower wiring layer 3 by the CVD method. As the interlayer insulating layer 5, a silicon oxide film having a thickness of about 1.5 μm is deposited by the CVD method, and then about 1 μm is formed.
Applying a thick SOG (Spin on Glass) film,
After that, the surface may be flattened and etched back to a thickness of about 1 μm. Also, about 1.0μ by the CVD method
It is also possible to deposit an m-thick silicon oxide film, apply an SOG (Spin on Glass) film with a thickness of about 0.5 μm, and then flatten the surface.

Then, a magnetic layer 11 extending in a direction orthogonal to the plurality of lower wiring layers 3 is formed on the interlayer insulating film 5 (FIG. 1B). As the magnetic layer 11, Mo permalloy having a thickness of about 0.5 μm, ferrite, Fe containing 5% or less of Si, or the like is formed. Next, the interlayer insulating layer 12 made of a silicon oxide film having a thickness of about 1 μm is deposited on the magnetic layer 11 by the CVD method. Subsequently, contact holes 6 are formed in the interlayer insulating films 5 and 12 on both ends of the lower wiring layer 3.

Next, an Al thin film or a Cu thin film having a thickness of about 0.5 μm is deposited by the sputtering method. Subsequently, a resist (not shown) is patterned by a normal photolithography technique, and the Al thin film or the Cu thin film is patterned by the RIE method using the patterned resist as a mask to form the upper wiring layer 7 to be the upper part of the spiral pattern. Form. The upper wiring layer 7 connects one end of the adjacent lower wiring layer 3 and the other end of the lower wiring layer 3 which are adjacent to each other through the connection portion 9 in the contact hole 6 (FIG. 2A).

As a result, as shown in FIG. 2B which is a sectional view taken along the longitudinal direction of the upper wiring layer 7, the upper wiring layer 7 is formed.
Crosses over the convex portion 13 formed of the interlayer insulating layer 5, the magnetic layer 11, and the interlayer insulating layer 12, and connects one end and the other end of the adjacent lower wiring layer 3. Therefore, the spiral pattern 10 in which the magnetic layer 11 as the core is wound by the lower wiring layer 3 and the upper wiring layer 7 is formed.

According to the manufacturing method of this embodiment, the CM
Since it is compatible with the standard manufacturing process for manufacturing the OS, the bipolar, etc., it can be easily incorporated into the conventional manufacturing process. When the lower wiring layer is the first wiring layer and the upper wiring layer is the second wiring layer, it is possible to perform the patterning of the multilayer wiring layer, the etching of the interlayer insulating film, and the flattening process. The spiral pattern can be formed without increasing the number of steps.

The spiral pattern is shown in FIG.
As shown in FIG. 5, the magnetic layer 11 may be a ring, and the ring-shaped magnetic layer 11 may be wound around the lower wiring layer 3 and the upper wiring layer 7 to form a toroidal (annular) coil. As shown in FIG. 3B, the magnetic layer 11 may be linear, and the linear magnetic layer 11 may be wound by the lower wiring layer 3 and the upper wiring layer 7 to form a cylindrical coil.

The spiral pattern of this embodiment is shown in FIG.
The magnetic field H in the case of the toroidal pattern as shown in (a) will be examined. Generally, in the toroidal coil, the magnetic field H is expressed by the following equation. H = NI / 2πr where N is the number of turns of the coil, I is the current value, and r is the radius of the toroidal coil.

According to the structure of this embodiment, it is possible to easily increase the number of turns N while keeping the radius r to a minimum, so that a large magnetic field can be obtained with a small element area. Further, since the magnetic layer 11 that is the core can be easily thinned and thinned, the eddy current loss which is a problem during high frequency operation can be easily reduced. The magnetic field H and magnetic flux density B of this example were numerically calculated.

A toroidal coil having a radius of 318 μm was formed by 1000 lower wiring layers 3 and 1000 upper wiring layers 7. If a current of 1 mA is passed, the magnetic field H is H = 1000 · 1 × 10 ⁻³ / 2π · 318 × 10 ⁻⁶ = 500 [A / m].

The magnetic flux density B is about 830 [mT] when the magnetic layer 11 that is the core is Mo permalloy, and about 400 [mT] when it is Ni-Zn ferrite, and is 4% Si-Fe. It becomes about 1980 [mT].
The area occupied by the toroidal coil at this time is only 0.32 mm ² .

In the semiconductor device shown in FIGS. 1 to 3, the magnetic material layer 11 is provided as the core in the interlayer insulating layers 5 and 12, but as shown in FIG. 4, the magnetic material layer 11 is not provided and the core is not provided. The spiral pattern 10 may be used. FIG. 4B is a sectional view taken along the longitudinal direction of the upper wiring layer 7. An interlayer insulating layer 5 made of a silicon oxide film having a thickness of about 2 μm is formed on the lower wiring layer 3 below the spiral pattern by a CVD method.
Deposit. Subsequently, contact holes 6 are formed in the interlayer insulating film 5 on both ends of the lower wiring layer 3.

Next, an upper wiring layer 7 which is an upper portion of the spiral pattern is formed on the interlayer insulating film 5. Upper wiring layer 7
Connects one end of the lower wiring layer 3 and the other end of the lower wiring layer 3 which are adjacent to each other via the connection portion 9 in the contact hole 6. As the same structure as the semiconductor device shown in FIGS. 1 to 3, the magnetic flux density B of the toroidal coil without core was obtained.

The relative dielectric constant ε of the silicon oxide film which is the interlayer insulating film 5 is ε = 3.9, and the refractive index (= εμ / ε ₀ μ ₀ ) ^1/2 =
Since it is 1.46, the relative permeability of the silicon oxide film μ =
0.55, magnetic permeability μμ ₀ = 0.55 × 1.25 × 10 ⁻⁶
= 6.8 × 10 ⁻⁷ [H / m]. Since the magnetic field H of the toroidal coil having the structure of this embodiment is H = 500 [A / m], the magnetic flux density B is: B = μμ ₀ H = 3.4 × 10 ⁻⁴ [Wb / m ² ] = 34 [ mT], and even if there is no core, a sufficiently practical magnetic flux density can be obtained.

A semiconductor device and a method of manufacturing the same according to a second embodiment of the present invention will be described with reference to FIGS. The same members of the present embodiment as those of the semiconductor device according to the first embodiment shown in FIGS. 1 to 4 are represented by the same reference numbers not to repeat or to simplify their explanation. In the semiconductor device according to the present embodiment, a recess is formed in the insulating layer, and a lower wiring layer is formed on this recess. A method of manufacturing the semiconductor device according to this embodiment will be described with reference to FIG. FIG. 5 is a sectional view taken along the longitudinal direction of the lower wiring layer 3. In this embodiment, the thick insulating layer 2 made of a silicon oxide film having a thickness of about 3 μm is formed on the semiconductor substrate 1 by the CVD method.
To form. Then, the thick insulating layer 2 is HF-approx.
Etching is performed to a depth of m to form the recess 14 (FIG. 5).
(A)).

Next, an Al thin film or Cu thin film having a thickness of about 0.5 μm is deposited by the sputtering method. Subsequently, a resist (not shown) is patterned by a normal photolithography technique, and the Al thin film or the Cu thin film is patterned by the RIE method using the patterned resist as a mask to form the lower wiring layer 3 to be the lower part of the spiral pattern. Formed (FIG. 5A).

Next, an interlayer insulating layer 5 made of a silicon oxide film having a thickness of about 1.5 μm is deposited on the lower wiring layer 3 by the CVD method. Subsequently, the magnetic layer 11 extending in the direction orthogonal to the plurality of lower wiring layers 3 is formed on the interlayer insulating film 5 (FIG. 5B). As the magnetic layer 11, for example, about 0.
A 5 μm thick Mo permalloy is formed. Next, the interlayer insulating layer 12 made of a silicon oxide film having a thickness of about 1.5 μm is deposited on the magnetic layer 11 by the CVD method. Subsequently, contact holes 6 are formed in the interlayer insulating films 5 and 12 on both ends of the lower wiring layer 3.

Next, an Al thin film or Cu thin film having a thickness of about 0.5 μm is deposited by the sputtering method. Subsequently, a resist (not shown) is patterned by a normal photolithography technique, and the Al thin film or the Cu thin film is patterned by the RIE method using the patterned resist as a mask to form the upper wiring layer 7 to be the upper part of the spiral pattern. Form. The upper wiring layer 7 connects one end of the lower wiring layer 3 and the other end of the lower wiring layer 3 which are adjacent to each other through the connecting portion 9 in the contact hole 6 (FIG. 5C).

Thus, the upper wiring layer 7 connects one end and the other end of the adjacent lower wiring layer 3. Therefore, a spiral pattern wound by the lower wiring layer 3 and the upper wiring layer 7 is formed so as to surround the magnetic layer 11 that is the core. The concave portion 14 formed in the thick insulating layer 2
As shown in FIG. 6A, it may be formed such that only the region where the lower wiring layer 3 is formed is recessed.
As shown in (b), it may be formed such that a long and narrow region including the region where the lower wiring layer 3 is formed and continuous along the magnetic layer 11 is recessed.

Further, in FIG. 4, both ends of the lower wiring layer 3 are formed so as to reach the flat portions around the recesses 14 of the insulating layer 2, and the flat portions are connected by the connecting portions 9. However, as shown in FIG. 7A, only one end of the lower wiring layer 3 may be formed so as to reach the flat portion around the recess 14 of the insulating layer 2. Further, as shown in FIG. 7B, both ends of the lower wiring layer 3 may be formed in the recess 14 of the insulating layer 2.

A semiconductor device and a method of manufacturing the same according to the third embodiment of the present invention will be described with reference to FIGS. The same members of the present embodiment as those of the semiconductor device according to the second embodiment shown in FIGS. 5 to 7 are represented by the same reference numbers not to repeat or to simplify their explanation. The semiconductor device according to the present embodiment is one in which a concave portion is formed in an insulating layer, a lower wiring layer is formed on this concave portion, and an upper wiring layer is formed on a convex portion of an interlayer insulating layer. A method of manufacturing the semiconductor device according to the present embodiment will be described with reference to FIG.
FIG. 8 is a sectional view taken along the longitudinal direction of the lower wiring layer 3. In this embodiment, as in the second embodiment, the thick insulating layer 2 is formed on the semiconductor substrate 1, and the thick insulating layer 2 is formed on the surface thereof. The recess 14 is formed. Then, the lower wiring layer 3 is formed on the concave portion 14 of the thick insulating layer 2 (FIG. 8A).

Next, a silicon oxide film having a thickness of about 1.0 μm is deposited on the lower wiring layer 3 by the CVD method, and then about 0.5 is formed.
A SOG film having a thickness of μm is applied, and then the surface is flattened to form an interlayer insulating layer 5 (FIG. 8B). As the interlayer insulating layer 5, a silicon oxide film having a thickness of about 1.5 μm is deposited by a CVD method, and then an SOG film having a thickness of about 1 μm is applied, and then the surface is flattened to have a thickness of about 1 μm. You may etch back.

Subsequently, the magnetic layer 11 extending in the direction orthogonal to the plurality of lower wiring layers 3 is formed on the interlayer insulating film 5 (FIG. 8B). As the magnetic layer 11, Mo permalloy having a thickness of about 0.5 μm, ferrite, Fe containing 5% or less of Si, or the like is formed. Next, the interlayer insulating layer 12 made of a silicon oxide film having a thickness of about 1.5 μm is deposited on the magnetic layer 11 by the CVD method. Subsequently, contact holes 6 are formed in the interlayer insulating films 5 and 12 on both ends of the lower wiring layer 3.

Next, a curved upper wiring layer 7 is formed across the convex portion 13 composed of the magnetic layer 11 and the interlayer insulating layer 12, and one end and the other end of the adjacent lower wiring layer 3 are connected to the contact hole 6. Connection is made via the connecting portion 9 in the inside (FIG. 8).
(C)). Therefore, according to this embodiment, as shown in FIG. 9, both the lower wiring layer 3 and the upper wiring layer 7 are curved,
A spiral pattern is formed so as to surround the magnetic layer 11 that is the core.

A semiconductor device and a method of manufacturing the same according to a fourth embodiment of the present invention will be described with reference to FIG. Figure 8
The same components as those of the semiconductor device of the third embodiment shown in FIG. 9 are designated by the same reference numerals to omit or simplify the description. In the semiconductor device according to the present embodiment, the interlayer insulating film below the magnetic layer is not flattened, but the interlayer insulating film on the magnetic layer 11 is flattened. The method for manufacturing the semiconductor device according to the present embodiment will be described with reference to FIGS. FIG. 10 is a sectional view taken along the longitudinal direction of the lower wiring layer.

In this embodiment, similarly to the third embodiment, the thick insulating layer 2 is formed on the semiconductor substrate 1 and the recess 14 is formed on the surface of the thick insulating layer 2. Then, the lower wiring layer 3 is formed on the concave portion 14 of the thick insulating layer 2 (FIG. 10A). Next, the interlayer insulating layer 5 made of a silicon oxide film having a thickness of about 1.5 μm is formed on the lower wiring layer 3 by the CVD method (FIG. 1).
0 (b)). Here, the interlayer insulating layer 5 is not flattened.
Subsequently, the magnetic layer 11 extending in the direction orthogonal to the plurality of lower wiring layers 3 is formed on the interlayer insulating film 5 (FIG. 10).
(B)).

Next, a silicon oxide film having a thickness of about 1.0 μm is deposited on the magnetic layer 11 by the CVD method, and thereafter, a silicon oxide film having a thickness of about 1.0 μm is formed.
An SOG film having a thickness of 5 μm is applied, and then the surface is flattened to form an interlayer insulating layer 12 (FIG. 10B). In addition,
The interlayer insulating layer 12 has a thickness of about 1.5 μm formed by the CVD method.
After depositing thick silicon oxide film, SOG of about 1 μm thick
The film may be applied and then the surface may be planarized and etched back to a thickness of about 1 μm.

Next, the upper wiring layer 7 is formed on the flattened surface of the interlayer insulating layer 12, and one end and the other end of the adjacent lower wiring layer 3 are connected via the connecting portion 9 in the contact hole 6. Connect (Fig. 10 (c)). Therefore, according to the present embodiment, the lower wiring layer 3 and the upper wiring layer 7 form a spiral pattern wound so as to surround the magnetic layer 11 as the core. A semiconductor device and a method for manufacturing the same according to a fifth embodiment of the present invention will be described with reference to FIGS. The same members of the present embodiment as those of the semiconductor device according to the first embodiment shown in FIGS. 1 to 4 are represented by the same reference numbers not to repeat or to simplify their explanation.

The semiconductor device according to the present embodiment is one in which a convex portion is formed in a space portion between lower wiring layers on an insulating layer, and an upper wiring layer is formed on the convex portion via an interlayer insulating film.
In this embodiment, about 2 μm is formed on the semiconductor substrate 1 by the CVD method.
An insulating layer 2 made of a silicon oxide film having a thickness of m is formed. Subsequently, a portion other than the space portion 15 between the areas where the lower wiring layer is to be formed is etched by about 1 μm to form the convex portion 16 in the space portion 15 (FIG. 11A).

Next, an Al thin film or Cu thin film having a thickness of about 0.5 μm is deposited by the sputtering method. Subsequently, a resist (not shown) is patterned by a normal photolithography technique, and the Al thin film or the Cu thin film is patterned by the RIE method using the patterned resist as a mask to form a lower portion on the flat portion 17 between the convex portions 16. The wiring layer 3 is formed (FIG. 11B).

Next, an interlayer insulating layer 5 made of a silicon oxide film having a thickness of about 1 μm is deposited on the lower wiring layer 3 by the CVD method. Then, the interlayer insulating film 5 on both ends of the lower wiring layer 3 is formed.
A contact hole 6 is formed in (FIG. 12 (a)). Next, an Al thin film or C having a thickness of about 0.5 μm is formed by the sputtering method.
u Deposit a thin film. Subsequently, a resist (not shown) is patterned by a normal photolithography technique, and the Al thin film or the Cu thin film is patterned by the RIE method using the patterned resist as a mask to form the upper wiring layer 7 to be the upper part of the spiral pattern. Form. The upper wiring layer 7 connects one end of the lower wiring layer 3 and the other end of the lower wiring layer 3 which are adjacent to each other through the connection portion 9 in the contact hole 6 (FIG. 12A).

As a result, a spiral pattern without a core is formed by winding the lower wiring layer 3 and the upper wiring layer 7 so as to surround the interlayer insulating layer 5. When forming the core, as shown in FIG. 12B, the concave portion 19 is formed by etching the portion of the convex portion 16 of the interlayer insulating layer 5 where the magnetic layer is formed, and the concave portion 19 is formed. Then, the magnetic layer 11 is formed. FIG. 12B is a cross-sectional view of the upper wiring layer 7 cut diagonally.

Further, as in the second to fourth embodiments described above, a region of the insulating layer 2 where the lower wiring layer is to be formed is etched to form a recess, and the lower wiring layer is formed in the recess of the insulating layer 2. You may do it. A semiconductor device and its manufacturing method according to a sixth embodiment of the present invention will be described with reference to FIGS.
Will be explained. The same components as those of the semiconductor device of the fifth embodiment shown in FIGS. 11 and 12 are designated by the same reference numerals to omit or simplify the description.

In the semiconductor device according to the present embodiment, after forming the lower wiring layer and the magnetic layer, the convex portion is formed in the space portion between the lower wiring layers on the interlayer insulating layer, and the upper wiring layer is formed on the convex portion. It was done. In this embodiment, the insulating layer 2 made of a silicon oxide film having a thickness of about 1 μm is formed on the semiconductor substrate 1 by the CVD method. Then, the sputtering method was performed to obtain about 0.
A 5 μm thick Al thin film or Cu thin film is deposited. continue,
A resist (not shown) is patterned by a normal photolithography technique, and the Al thin film or Cu thin film is patterned by the RIE method using the patterned resist as a mask to form the lower wiring layer 3 (FIG. 13).
(A)).

Next, the interlayer insulating layer 5 made of a silicon oxide film having a thickness of about 1 μm is deposited on the lower wiring layer 3 by the CVD method (FIG. 13B). In addition, as the interlayer insulating layer 5,
After depositing a silicon oxide film having a thickness of about 1.5 μm by the CVD method, an SOG film having a thickness of about 1 μm may be applied, and then the surface may be flattened and etched back to a thickness of about 1 μm. It is also possible to deposit a silicon oxide film having a thickness of about 1.0 μm by the CVD method, apply an SOG film having a thickness of about 0.5 μm, and then flatten the surface.

Next, the magnetic layer 11 extending in the direction orthogonal to the plurality of lower wiring layers 3 is formed on the interlayer insulating film 5 (FIG. 13B). About 0.5 μm as the magnetic layer 11
Thick Mo permalloy, ferrite, Fe containing 5% or less of Si, and the like are formed. Next, CVD is performed on the magnetic layer 11.
The interlayer insulating layer 12 made of a silicon oxide film having a thickness of about 2 μm is deposited by the method. The interlayer insulating layer 12 is C
After depositing a silicon oxide film having a thickness of about 1.5 μm by the VD method, an SOG film having a thickness of about 1 μm may be applied, and then the surface may be flattened and etched back to a thickness of about 1 μm. Alternatively, after depositing a silicon oxide film having a thickness of about 1.0 μm by the CVD method, an SOG film having a thickness of about 0.5 μm may be applied and then the surface may be flattened.

Subsequently, the space portion 15 between the lower wiring layers 3 is formed.
Other portions are etched by about 1 μm to form the convex portions 16 in the space portions 15 of the interlayer insulating layer 12 (FIG. 14).
(A)). Next, contact holes 6 are formed in the interlayer insulating films 5 and 12 on both ends of the lower wiring layer 3.

Then, an Al thin film or Cu thin film having a thickness of about 0.5 μm is deposited by the sputtering method. Subsequently, a resist (not shown) is patterned by a normal photolithography technique, and the Al thin film or the Cu thin film is patterned by the RIE method using the patterned resist as a mask to form the upper wiring layer 7 to be the upper part of the spiral pattern.
To form. The upper wiring layer 7 connects one end of the lower wiring layer 3 and the other end of the lower wiring layer 3 which are adjacent to each other through the connection portion 9 in the contact hole 6 (FIG. 14B).

As a result, a spiral pattern is formed with the magnetic layer 11 wound by the lower wiring layer 3 and the upper wiring layer 7 as a core so as to surround the interlayer insulating layer 5. A semiconductor device and a method of manufacturing the same according to a seventh embodiment of the present invention will be described with reference to FIGS. The same members of the present embodiment as those of the semiconductor device according to the first embodiment shown in FIGS. 1 to 4 are represented by the same reference numbers not to repeat or to simplify their explanation.

The semiconductor device according to the present embodiment has a spiral pattern formed by connecting the upper wiring layer and the lower wiring layer without forming a contact hole. In this embodiment, the thick insulating layer 2 made of a silicon oxide film having a thickness of about 4 μm is formed on the semiconductor substrate 1 by the CVD method. Subsequently, the thick insulating layer 2 is etched with HF to a depth of about 2 μm to form the recess 14 (FIG. 15A).

Next, an Al thin film or Cu thin film having a thickness of about 0.5 μm is deposited by the sputtering method. Subsequently, a resist (not shown) is patterned by a normal photolithography technique, and the Al thin film or the Cu thin film is patterned by the RIE method using the patterned resist as a mask to form a spiral on the inner surface of the recess 14 of the insulating layer 2. A lower wiring layer 3 to be the lower part of the pattern is formed (FIG. 15).
(A)).

Next, a silicon oxide film having a thickness of about 1.5 μm is deposited on the lower wiring layer 3 by the CVD method, and then about 1 μm.
After applying an m-thick SOG film and flattening the surface, etching back is performed until both ends of the lower wiring layer 3 are exposed to form an interlayer insulating layer 5 (FIG. 15B). Membrane 5
A magnetic material layer 11 made of, for example, Mo permalloy having a thickness of about 0.5 μm is formed thereon, and thereafter, an interlayer insulating layer 12 made of a silicon oxide film having a thickness of about 1.5 μm is formed on the magnetic material layer 11.
Deposit. Subsequently, the magnetic layer 11 and the interlayer insulating layer 12
Is a width 1 extending in a direction orthogonal to the plurality of lower wiring layers 3.
Patterning is performed in a band of μm (FIG. 15C).

Next, a silicon oxide film having a thickness of about 1.5 μm is deposited on the entire surface and anisotropically etched to form the magnetic layer 11.
Then, the interlayer insulating layer 20 is formed on the sidewall of the interlayer insulating layer 12.
Both ends of the lower wiring layer 3 are exposed just outside the interlayer insulating film 20 (FIG. 16A). Next, an Al thin film or Cu thin film having a thickness of about 0.5 μm is deposited by the sputtering method. Subsequently, a resist (not shown) is patterned by a normal photolithography technique, and the patterned resist is used as a mask by an RIE method to form an Al thin film or Cu.
The thin film is patterned to form the upper wiring layer 7 which is an upper part of the spiral pattern across the interlayer insulating layer 12 and the interlayer insulating layer 20 formed on the side wall thereof. Upper wiring layer 7
Directly connects one end of the lower wiring layer 3 and the other end of the lower wiring layer 3 which are adjacent to each other without passing through a contact hole (FIG. 16B).

As a result, as shown in FIG. 17, a spiral pattern formed by winding the lower wiring layer 3 and the upper wiring layer 7 so as to surround the magnetic layer 11 as the core and the interlayer insulating layers 5 and 12 is formed. It In order to prevent the exposed lower wiring layer 3 from being etched when the upper wiring layer 7 is etched for patterning, different materials are used for the lower wiring layer 3 and the upper wiring layer 7. May be selectively etched with respect to the lower wiring layer 3.

In order to prevent the underlying insulating layers 2, 5 and 12 from being etched when the interlayer insulating layer 20 is formed on the sidewalls of the interlayer insulating layer 12, these insulating layers 2 and 5 are formed.
Different materials may be used for 5, 12, and 20, and the interlayer insulating layer 20 may be selectively etched with respect to the insulating layer 2 and the interlayer insulating layers 5 and 12. Since insulating materials that can be selectively etched include silicon oxide, PSG, silicon nitride, polyimide, and the like, these materials may be used as appropriate.

A semiconductor device and a method of manufacturing the same according to the eighth embodiment of the present invention will be described with reference to FIG. Figure 1
The same components as those of the semiconductor device of the seventh embodiment shown in FIGS. 5 to 17 are designated by the same reference numerals to omit or simplify the description. In the semiconductor device according to the present embodiment, a wiring layer is formed on each semiconductor substrate, and then the two are bonded together to form a spiral pattern.

Similarly to the seventh embodiment, the lower wiring layer 3 is formed in the concave portion of the insulating layer 2 on one semiconductor substrate 1,
The upper wiring layer 7 is formed in the recess of the insulating layer 2 on the other semiconductor substrate 1 (FIG. 18). Next, both semiconductor substrates 1 are bonded together by a method such as electrostatic pressure bonding so that the lower wiring layer 3 and the upper wiring layer 7 are connected (FIG. 18).

As a result, a spiral pattern formed by winding the lower wiring layer 3 and the upper wiring layer 7 so as to surround the interlayer insulating layer 5 is formed. In the case of forming the core, the magnetic layer is embedded in the interlayer insulating layer 5 of the one semiconductor substrate 1, and then both the semiconductor substrates 1 are bonded together by a method such as electrostatic pressure bonding.

A semiconductor device and a method of manufacturing the same according to a ninth embodiment of the present invention will be described. The semiconductor device according to the present embodiment has an air isolation structure in which the interlayer insulating layer between the upper wiring layer and the lower wiring layer is removed to form a space. After forming the spiral pattern by the lower wiring layer 3 and the upper wiring layer 7 so as to surround the interlayer insulating layers 5 and 12 on the insulating layer 2 of the semiconductor substrate 1, only the interlayer insulating layers 5 and 12 may be removed by etching. . For that purpose, appropriate materials are selected for the lower wiring layer 3, the upper wiring layer 7, the insulating layer 2, and the interlayer insulating layers 5 and 12.

For example, when Cu is used for the lower wiring layer 3 and the upper wiring layer 7, only the interlayer insulating layers 5 and 12 made of a silicon oxide film by the CVD method can be selectively removed by etching with HF. At this time, if PSG is used for the interlayer insulating layers 5 and 12, the selectivity can be further improved. Further, Al is used as the lower wiring layer 3 and the upper wiring layer 7.
When a system alloy is used, if a resin such as polyimide is used as the interlayer insulating layers 5 and 12, the oxygen plasma causes
Only the interlayer insulating layers 5 and 12 can be selectively removed.

When the air isolation structure is used as in the semiconductor device of this embodiment, the relative permeability μ = 0.55 when the silicon oxide film is used as the interlayer insulating layer, so that the inductance can be improved. The magnetic field generated by the coil can be increased. In addition, when the minute spiral pattern is used in the bevel motor, it is necessary to remove the interlayer insulating layer as in the semiconductor device of this embodiment.

In the above embodiment, the wiring width of the spiral pattern, which is the element size, is set to 1 μm and its pitch is set to 2 μm from the viewpoint of semiconductor manufacturing process technology.
When it is used as a hair-belt motor, it must be sized as required for a drug delivery system or microsurgery in the body. For example, in order to treat the phagocytes and discharge them to the outside, it is desirable that the size of the entire spiral be 2 μm or less.

A semiconductor device and a method of manufacturing the same according to the tenth embodiment of the present invention will be described with reference to FIG. When the spiral pattern formed according to the above-described embodiment is used as a coil, it is difficult to form each dimension of the spiral pattern without error. Therefore, it is necessary to finely adjust the inductance after forming the spiral pattern.

In this embodiment, as shown in FIG. 19, the spiral pattern 1 formed on the insulating layer 2 of the semiconductor substrate 1
A plurality of tap lead wires 23 are formed from 0. The inductance is measured after the spiral pattern 10 is manufactured, and laser trimming is performed as necessary to realize a desired inductance. A semiconductor device according to an eleventh embodiment of the present invention and a method for manufacturing the same will be described with reference to FIGS.
Will be explained.

The semiconductor device according to the present embodiment is characterized in that a shield is formed around the spiral pattern so as to minimize the influence of the magnetic field on other elements and coils. In the semiconductor device according to the present embodiment, the MO
A MOS part 31 in which an SFET is formed, a bipolar part 32 in which a bipolar transistor is formed, and a coil part 33 in which a coil having the spiral pattern of this embodiment is formed are formed on the same semiconductor substrate 1. . In the following description, detailed description of the structures of the MOS part 31 and the bipolar part 32 will be omitted.

In the coil portion 32, the shield lower portion 24 made of polycrystalline silicon is formed on the field oxide film 28 of the semiconductor substrate 1, and the insulating layer 2 made of a silicon oxide film is formed on the lower shield layer 24 ( (Fig. 20). Next, using the first aluminum wiring layer in the MOS portion 31 and the bipolar portion 32, the shield side portion 25 is formed together with the lower wiring layer 3 which is the lower portion of the spiral pattern (FIG. 20).

Next, the interlayer insulating layer 5 is formed on the lower wiring layer 3, and then the magnetic layer 1 serving as a core is formed on the interlayer insulating layer 5.
1 (FIG. 21). Next, the interlayer insulating layer 12 is formed on the magnetic layer 11, and the contact holes 6 opening on both ends of the lower wiring layer 3 are formed (FIG. 21). Then M
Using the second aluminum wiring layer in the OS portion 31 and the bipolar portion 32, the shield side portion 25 'is formed together with the upper wiring layer 7 which is the upper portion of the spiral pattern (FIG. 22).

Next, the shield upper portion 26 is formed using the third aluminum wiring layer in the MOS portion 31 and the bipolar portion 32 (FIGS. 22 and 23). This allows
The spiral pattern formed from the lower wiring layer 3 and the upper wiring layer 7 is formed into a shield lower portion 24, shield side portions 25, 2.
5 ', surrounded by shield upper part 26, MOS part 30
The influence of the magnetic field on the bipolar part 31 can be minimized.

Incidentally, as shown in FIG. 24, the semiconductor substrate 1
The shield lower portion 27 may be formed by a conductive layer formed by adding impurities to the surface. Further, in the above-mentioned embodiment, the shield is surrounded and shielded on all four sides of the spiral pattern. However, a part of the spiral pattern may be deleted and shielded only in the long side direction, or may be shielded in the short side direction. .

The present invention is not limited to the above embodiment, but various modifications can be made. For example, the conductor forming the spiral pattern as the coil may be a refractory metal such as tungsten, molybdenum, tantalum, or titanium, or a silicide thereof, or polycrystalline silicon or amorphous silicon doped with impurities.

When the spiral pattern of the present invention is used as the flagellar portion of the flagellar motor, a material such as a protein that suppresses the rejection reaction in the body is desirable in addition to the above materials. In terms of hardness, 0.6% Cu / 0.3% Mo
/3.3%Ni/0.1%C/95.7%Fe iron alloy, 0.4% Mn / 1.2% Cr / 0.25% Mo /
An iron alloy of 0.16% C / 93.94% Fe may be used.

[0078]

As described above, according to the present invention, a semiconductor substrate, an insulating layer formed on the semiconductor substrate, a plurality of first wiring layers formed on the insulating layer, and a first wiring. The first wiring layer and the second wiring layer are formed above the layer and have the second wiring layer that connects one end of the first wiring layer and the other end of the first wiring layer that are adjacent to each other. A fine spiral pattern can be realized by the wiring layer.

Further, according to the present invention, an insulating layer is formed on the semiconductor substrate, a plurality of first wiring layers are formed on the insulating layer, and an interlayer insulating layer is formed on the first wiring layer. Since the second wiring layer which connects one end of the first wiring layer and the other end of the first wiring layer which are adjacent to each other is formed on the interlayer insulating layer so as to surround the interlayer insulating layer, the first wiring layer is formed. A fine spiral pattern can be formed by the wiring layer and the second wiring layer.

Therefore, when the spiral pattern according to the present invention is used as a coil, it can be integrally formed on the LSI chip like other elements. In addition, if the spiral pattern according to the present invention is used as bengle hair,
A beveled hair motor in micromachining can be realized.

[Brief description of drawings]

FIG. 1 is a process diagram (1) showing a method for manufacturing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a process diagram (2) showing the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 3 is a diagram showing a semiconductor device according to a first embodiment of the present invention.

FIG. 4 is a diagram showing a modification of the semiconductor device according to the first embodiment of the present invention.

FIG. 5 is a process drawing showing the manufacturing method of the semiconductor device according to the second embodiment of the present invention.

FIG. 6 is a diagram showing a semiconductor device according to a second embodiment of the present invention.

FIG. 7 is a diagram showing a modification of the semiconductor device according to the second embodiment of the present invention.

FIG. 8 is a process drawing showing the manufacturing method of the semiconductor device according to the third embodiment of the present invention.

FIG. 9 is a diagram showing a semiconductor device according to a third embodiment of the present invention.

FIG. 10 is a process drawing showing the manufacturing method of the semiconductor device according to the fourth embodiment of the present invention.

FIG. 11 is a process drawing (1) showing the method for manufacturing a semiconductor device according to the fifth embodiment of the present invention.

FIG. 12 is a process diagram (2) showing the method for manufacturing the semiconductor device according to the fifth embodiment of the present invention.

FIG. 13 is a process diagram (1) showing the method for manufacturing the semiconductor device according to the sixth embodiment of the present invention.

FIG. 14 is a process diagram (2) showing the method for manufacturing the semiconductor device according to the sixth embodiment of the present invention.

FIG. 15 is a process drawing (1) showing the method for manufacturing the semiconductor device according to the seventh embodiment of the present invention.

FIG. 16 is a process diagram (2) showing the method for manufacturing the semiconductor device according to the seventh embodiment of the present invention.

FIG. 17 is a diagram showing a semiconductor device according to a seventh embodiment of the present invention.

FIG. 18 is a process drawing showing the manufacturing method of the semiconductor device according to the eighth embodiment of the present invention.

FIG. 19 is a diagram showing a semiconductor device according to a tenth embodiment of the present invention.

FIG. 20 is a process diagram (1) showing the method for manufacturing the semiconductor device according to the eleventh embodiment of the present invention.

FIG. 21 is a process diagram (2) showing the method for manufacturing the semiconductor device according to the eleventh embodiment of the present invention.

FIG. 22 is a process diagram (3) showing the method for manufacturing the semiconductor device according to the eleventh embodiment of the present invention.

FIG. 23 is a diagram showing a semiconductor device according to an eleventh embodiment of the present invention.

FIG. 24 is a diagram showing a modification of the semiconductor device according to the eleventh embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate 2 ... Insulating layer 3 ... Lower wiring layer 5 ... Interlayer insulating layer 6 ... Contact hole 7 ... Upper wiring layer 9 ... Connection part 10 ... Spiral pattern 11 ... Magnetic material layer 12 ... Interlayer insulating layer 13 ... Convex part 14 ... Recessed portion 15 ... Space portion 16 ... Convex portion 17 ... Flat portion 19 ... Recessed portion 20 ... Interlayer insulating layer 23 ... Tap lead wiring 24 ... Shield lower portion 25, 25 '... Shield side portion 26 ... Shield upper portion 27 ... Shield lower portion 28 ... Field Oxide film 30 ... MOS part 31 ... Bipolar part 32 ... Coil part

Claims (12)

[Claims] 1. A semiconductor substrate, an insulating layer formed on the semiconductor substrate, a plurality of first wiring layers formed on the insulating layer, and formed on the first wiring layer, A second wiring layer that connects one end of the first wiring layer and the other end of the first wiring layer that are adjacent to each other, and the spiral pattern is formed by the first wiring layer and the second wiring layer. A semiconductor device comprising: 2. The semiconductor device according to claim 1, further comprising an interlayer insulating layer formed between the first wiring layer and the second wiring layer, the first wiring layer and the second wiring layer. A semiconductor device, wherein a spiral pattern surrounding the interlayer insulating layer is formed by a wiring layer. 3. The semiconductor device according to claim 2, further comprising a magnetic layer formed in the interlayer insulating layer and penetrating the spiral pattern, the first wiring layer and the second wiring layer. The semiconductor device is characterized in that a spiral pattern surrounding the magnetic layer is formed. 4. The semiconductor device according to claim 1, wherein the insulating layer is formed in a concave shape, and the first wiring layer is formed in a convex shape on a concave portion of the insulating layer. A semiconductor device characterized in that 5. The semiconductor device according to claim 2, wherein a protrusion is formed on an upper surface of the interlayer insulating layer, and the second wiring layer is provided on the protrusion of the interlayer insulating layer. A semiconductor device characterized by being formed in a concave shape. 6. The semiconductor device according to claim 2, wherein the first wiring layer and the second wiring layer are connected via a connection hole or a groove formed in the interlayer insulating layer. A semiconductor device characterized by being connected together. 7. A step of forming an insulating layer on a semiconductor substrate, a step of forming a plurality of first wiring layers on the insulating layer, and a step of forming an interlayer insulating layer on the first wiring layer. And the first wiring layer on the interlayer insulating layer, the first wiring layer being adjacent to one end of the first wiring layer so as to surround the interlayer insulating layer.
And a step of forming a second wiring layer that connects the other end of the wiring layer on the opposite side to the second wiring layer. 8. The method of manufacturing a semiconductor device according to claim 7, further comprising the step of removing the interlayer insulating layer surrounded by the first wiring layer and the second wiring layer. Manufacturing method of semiconductor device. 9. A step of forming an insulating layer on a semiconductor substrate, a step of forming a plurality of first wiring layers on the insulating layer, and a first interlayer insulating layer on the first wiring layer. A step of forming, a step of forming, on the first interlayer insulating layer, a magnetic layer that extends in a direction intersecting with the first wiring layer, and a step of forming a second interlayer insulating layer on the magnetic layer. Forming a magnetic layer on the second interlayer insulating layer so as to surround one end of the first wiring layer and the other end of the first wiring layer opposite to the other end of the first wiring layer. And a step of forming a second wiring layer for connecting the two. 10. The method of manufacturing a semiconductor device according to claim 7, further comprising the step of etching the insulating layer to form a recess on the upper surface, and forming a recess on the insulating layer. A method of manufacturing a semiconductor device, comprising forming a plurality of first wiring layers in a concave shape. 11. The method for manufacturing a semiconductor device according to claim 7, wherein a convex portion is formed on the upper surface of the interlayer insulating layer in a region where the second wiring layer is to be formed. A method of manufacturing a semiconductor device, further comprising a step of forming, wherein the second wiring layer is formed in a convex shape on the convex portion of the interlayer insulating layer. 12. The method for manufacturing a semiconductor device according to claim 7, further comprising the step of forming a connection hole or a groove on both ends of the first wiring layer of the interlayer insulating layer. A method for manufacturing a semiconductor device, comprising forming the second wiring layer on the interlayer insulating layer and connecting the second wiring layer to the first wiring layer through the connection hole or groove of the interlayer insulating layer. .