JPH0786332A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To improve reliability of plating bonding in irregularity of height direction of an inner lead by a method wherein a plurality of electrode pads are short-circuited by wiring pattern, and the potential from the lead terminal which is brought into contact with the electrode pads is applied to non-contact electrode parts too. CONSTITUTION:The electrode pads 12 of a semiconductor chip 11 is short- circuited by a wiring pattern 11a. When the semiconductor chip 11 and a lead frame 13 are adhered, at least one of lead terminals 14 is brought into contact with one of the electrode pads 12. As a result, uniform potential can be applied to each electrode pad of the semiconductor chip 11 from the lead terminals 14 when a plating-bonding operation is conducted. Accordingly, potential is applied to each electrode pad 12 when a plating-bonding operation is conducted, highly efficient plated junction can be formed by the growth of a metal-plated layer 15 from both lead terminals 14 and the electrode pad 12, and the reliability of plating bonding can be improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which lead terminals of a lead frame and electrodes on a semiconductor chip are electrically connected by metal plating, and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, as a method of electrically connecting an electrode pad on a semiconductor chip and an inner lead of a lead frame, for example, a joining method using metal plating (plating bonding method) has been devised.

In this state, the electrode pads of the semiconductor chip and the inner leads of the lead frame are aligned,
Both are soaked in an electrolytic plating solution to form a metal plating layer at the joint between the electrode pad and the inner lead.

FIG. 8 shows an example of plating joining in the conventional method.

For example, conventionally, the inner lead 3 of the lead frame is positioned on the electrode pad 2 on the surface of the semiconductor chip 1 (FIG. 1 (a)), and in this state, a potential is applied to the lead 3 side. The metal plating layer 4 was grown to connect the inner lead 3 and the electrode pad 2 (FIG. 2 (b)).

In the above-mentioned conventional method, when the electrode pad 2 and the inner lead 3 are in contact with each other in advance, the metal plating layer 4 grows from both of them, so that they can be connected without any problem.

However, when the electrode pad 2 and the inner lead 3 are not in contact with each other, the metal plating layer 4 is grown from the side of the lead 3 while filling the gap between the electrode pad 2 and the electrode pad 2. By the growth above 2, the connection between the two will be made.

That is, the inner lead 3 of the lead frame has a variation in the Z direction, that is, the distance from the electrode pad 2. Therefore, the inner lead 3 and the electrode pad 2
It is possible to form a sufficiently grown metal plating layer 4 in a place where the distance is short, but it is not possible to form a sufficiently grown metal plating layer 4 in a place where the distance is far from There is a drawback that it takes time to form No. 4.

As described above, the variation in the height direction of the inner leads 3 affects the reliability of the plating bonding.

In particular, when the distance between the inner leads 3 and the electrode pads 2 is larger than the distance between the inner leads 3, the metal plating layer 4 is placed between the leads 3 before connection.
However, there was a problem in that a short circuit occurred between the leads due to the growth.

[0011]

As described above, conventionally, when the inner lead and the electrode pad are not in contact with each other, a sufficiently grown metal plating layer is formed between the inner lead and the electrode pad. Variations in the height direction of the inner leads had an influence on the reliability of the plating bonding because it was difficult to form.

Therefore, according to the present invention, the electrode of the semiconductor chip and the lead terminal of the lead frame can be surely connected by plating, and the reliability of the plating bonding due to the variation in the height direction of the inner lead can be improved. An object is to provide a device and a manufacturing method thereof.

[0013]

To achieve the above object, in a semiconductor device of the present invention, a semiconductor chip provided with a plurality of electrodes and the electrodes of the semiconductor chip are respectively connected. A lead frame having a plurality of lead terminals, a connecting portion for individually connecting the lead terminals of the lead frame and the electrodes of the semiconductor chip by metal plating, and at the time of the metal plating at this connecting portion,
It is composed of an electrode portion that applies the same potential as the lead terminal of the lead frame to each electrode of the semiconductor chip, and a cutting portion that separates the electrode portion from each electrode of the semiconductor chip after the metal plating.

Further, in the method of manufacturing a semiconductor device of the present invention, the plurality of electrodes provided on the upper surface of the semiconductor chip and the plurality of lead terminals of the lead frame are brought close to each other, or a part thereof is brought into contact. Then, the step of adhering the lead frame onto the semiconductor chip, and through each wiring of the semiconductor chip through a wiring pattern that is drawn from each electrode of the semiconductor chip and short-circuited at one end thereof And applying the same potential to each lead terminal of the lead frame, and in this state, both the semiconductor chip and the lead frame are immersed in an electrolytic plating solution to form the lead terminal of the lead frame and the electrode of the semiconductor chip. And a step of forming a metal plating layer for individually connecting and, after forming the metal plating layer, cutting the wiring pattern It consists a step of disconnecting the electrodes of the semiconductor chip.

[0015]

According to the present invention, even when the electrodes of the semiconductor chip and the lead terminals of the lead frame are not in contact with each other by the above-mentioned means, plating is deposited from both the electrodes of the semiconductor chip and the lead terminals of the lead frame. As a result, it becomes possible to efficiently form a sufficiently grown metal plating layer between the non-contact inner lead and the electrode pad.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 schematically shows a main part of the structure of a semiconductor device according to the present invention.

That is, in this semiconductor device, for example, the electrode pads 12 provided on the main surface of the semiconductor chip 11 are provided.
And a lead terminal (inner lead portion) 14 of the lead frame 13 are electrically connected by a metal plating layer 15 as a connecting portion made of nickel (Ni) or the like.

The peripheral surface of the semiconductor chip 11 excluding the outer lead portions of the lead terminals 14 is sealed with a sealing resin which will be described later, so that packaging is performed.

Reference numeral 11a in the figure denotes the electrode pad 12
A wiring pattern made of a conductive material that is further drawn out, and 11b is a cut portion obtained by cutting the wiring pattern 11a.

The semiconductor chip 11 and the lead frame 13 are adhered by the adhesive tape layer 16 in a state where the electrode pads 12 and the lead terminals (inner lead portions) 14 are aligned, that is, the inner lead portions, respectively. The tips of the electrodes are brought close to the respective electrode pads 12,
Moreover, at least a part of the contacting portion is attached.

2 and 3 show the semiconductor chip 11 described above.
1 schematically shows the configuration of. Note that FIG. 2 is a plan view of the semiconductor chip 11, and FIG. 3 is a side sectional view of the same main part.

That is, the semiconductor chip 11 is provided with a plurality of electrode pads 12 and a wiring pattern 11a drawn from each electrode pad 12 on its main surface.

The electrode pads 12 are arranged in a line along the central portion of the semiconductor chip 11 in the longitudinal direction, for example, at regular intervals.

The other end (one end opposite to the semiconductor chip 12 side) of the wiring pattern 11a is connected to each other at the end on the main surface of the semiconductor chip 11, and each of the electrode pads 12 is short-circuited (short-circuited) in advance. It is in a state where it has been made.

In the vicinity of the connection end of the wiring pattern 11a, a cutting portion 11b for cutting the mutual connection of the wiring patterns 11a along the cutting line shown in the drawing is formed.

The main surface of the semiconductor chip 11 excluding the portion where the electrode pad 12 is formed is covered with an insulating surface protection film 11c such as a passivation film.

It should be noted that the semiconductor chip 11 does not have an active portion or a passive portion directly below the electrode pad 12 and directly below the cutting portion 11b (that is, the electrode pad 12 does not exist at a position where the active portion or the passive portion does not exist). And the cut portion 11b is formed).

Further, in the present embodiment, for example, a conductive wiring such as aluminum (Al) is formed on the main surface of the semiconductor chip 11, and the portion of the conductive wiring exposed from the surface protection film 11c is electrode pad 12. The surface protective film 11
The portion covered by c is used as the wiring pattern 11a.

FIG. 4 schematically shows the structure of the lead frame 13.

That is, the lead frame 13 is manufactured by, for example, photoetching or stamping a thin metal plate, and a plurality of lead terminals (inner lead portions) 14 are alternately arranged in the left-right direction of the frame. It has been configured.

Further, an outer lead portion (not shown) for mounting is formed on each of the lead terminals 14 so as to correspond to each inner lead portion.

The semiconductor chip 11 is attached to the lead frame 13 in a state where the tips of the inner lead portions are aligned so as to correspond to the respective electrode pads 12.

In this case, in the electrode pad 12 with which the tips of the inner leads are in contact, the lead terminals 14 are
Electrical connection between the electrode pad 12 and the electrode pad 12 is achieved.

Further, at least one of the inner leads of the plurality of lead terminals 14 has a tip portion which is the electrode pad 12.
All electrode pads 1 by being contacted with one of the
Electrical connection to 2 is achieved.

That is, since each of the electrode pads 12 is short-circuited by the wiring pattern 11a, at least one of the electrode pads 12 is brought into contact with the tip portion of the inner lead portion so as to be brought into contact therewith. Even the non-existing electrode pad 12 can be brought into a state in which its electrical continuity is achieved.

Therefore, it is possible to apply a uniform potential from the lead terminal 14 (the same potential as the lead terminal 14) to each electrode pad 12 of the semiconductor chip 11 during plating bonding.

Thus, the above-mentioned metal plating layer 15 is formed between the lead terminal 14 and the electrode pad 12 which are electrically connected to each other.

FIG. 5 shows the lead terminal 14 and the electrode pad 12.
2 shows an example of joining with the metal plating layer 15.

That is, the metal plating layer 15 is formed by plating the lead frame 13 to which the semiconductor chip 11 is adhered with the plating electrode (see the figure) in a state where at least one of the lead terminals 14 is in contact with one of the electrode pads 12. (Not shown) together with, for example, a nickel plating bath.

Then, by applying a predetermined DC voltage so that the plating electrode serves as an anode or an anode and the lead frame 13 serves as a cathode or a cathode,
Well-known electrolytic plating is performed, and the lead terminal 14 and the electrode pad 12 are electrically connected to each other by the metal plating layer 15 grown between them.

At this time, the negative potential applied to the lead frame 13 is applied to each of the lead terminals 14 and also to each of the electrode pads 12 of the semiconductor chip 11 via some of the lead terminals 14. It will be.

As a result, at the same time that the plating is deposited from the lead terminal 14 side, the plating is also deposited from the electrode pad 12 side, and the lead terminal 14 and the electrode pad 1 are also deposited.
Even when the two are not in contact with each other, the metal plating layer 15 grown from both sides enables efficient and stable connection.

Since the formation of the metal plating layer 15 is disclosed in, for example, Japanese Patent Application No. 2-141684, detailed description thereof will be omitted.

In the semiconductor chip 11 in which the lead terminals 14 and the electrode pads 12 are bonded by the metal plating layer 15 in this way, the wiring pattern 11a is cut along the cutting line by, for example, a YAG laser (not shown). And cut the semiconductor chip 11 so that it is cut on the main surface of the semiconductor chip 11.
By forming the, the electrode pads 12 which have been in the short-circuited state are separated from each other.

Since the cut portion 11b can be formed with a width of 50 μm or less when the YAG laser is used, it is possible to prevent the semiconductor chip 11 from becoming large.

Thereafter, as shown in FIG. 6, for example, the periphery of the semiconductor chip 11 including the lead terminals (inner lead portions) 14 is sealed with the sealing resin 17, so that the packaging is performed. The obtained semiconductor device is obtained.

As described above, even when the electrode pad of the semiconductor chip and the lead terminal of the lead frame are not in contact with each other, plating can be deposited from both the electrode pad of the semiconductor chip and the lead terminal of the lead frame. I have to.

That is, a plurality of electrode pads are short-circuited by a wiring pattern so that the potential from the lead terminal which is in contact with the electrode pad is applied to the electrode pad which is not in contact with other lead terminals. I have to. As a result, a uniform electric potential can be applied to each of the electrode pads during plating bonding, so that a sufficiently grown metal plating layer can be efficiently formed between the non-contact lead terminals and the electrode pads. It becomes possible. Therefore, even if there is a gap between the lead terminal and the electrode pad, a reliable connection can be achieved without causing a connection failure or a short circuit between leads, and the stability of the bonding by plating can be improved. is there.

Further, according to the apparatus of this embodiment, at least one of the lead terminals is in contact with one of the electrode pads, and it is not necessary to forcibly bring the non-contact lead terminals into contact with the electrode pad. Therefore, the electrode pad is not damaged by the forcible contact.

In the above embodiment, the case where at least one of the lead terminals is brought into contact with one of the electrode pads so that a uniform potential is also applied to the other electrode pads has been described. Not limited to, for example, FIG.
As shown in, a dedicated electrode 21 for directly applying a potential to each electrode pad 12 may be prepared on the main surface of the semiconductor chip 11.

In this case, the lead terminal 14 and the electrode pad 1
Even if there is no contact between the two, plating joining can be easily performed.

Further, not only when there are a plurality of electrode pads,
For example, it can be applied to one case, and an electric potential can be applied to each electrode pad.

Further, the structure is not limited to a lead frame formed of a thin metal plate, but may be, for example, TAB (Tape Aut).
The present invention can also be applied to a lead frame of an animated bonding system.

Of course, various modifications can be made without departing from the scope of the invention.

[0056]

As described above in detail, according to the present invention, the electrodes of the semiconductor chip and the lead terminals of the lead frame can be reliably connected by plating, and the reliability of the plating bonding due to the variation of the inner leads in the height direction. It is possible to provide a semiconductor device and a method for manufacturing the same that can improve the property.

[Brief description of drawings]

FIG. 1 is a plan view showing a main part of a configuration of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a plan view showing a configuration on a main surface of a semiconductor chip, similarly.

FIG. 3 is a sectional view schematically showing the main part of the configuration of the semiconductor chip.

FIG. 4 is a plan view showing a schematic structure of a lead frame.

FIG. 5 is a diagram showing an example of joining with a metal plating layer.

FIG. 6 is a sectional view of the packaged semiconductor device.

FIG. 7 is a plan view showing a main part of a configuration according to another embodiment of the present invention.

FIG. 8 is a diagram for explaining a conventional technique and its problems.

[Explanation of symbols]

11 ... Semiconductor chip, 11a ... Wiring pattern, 11b ...
Cutting part, 12 ... Electrode pad, 13 ... Lead frame, 1
4 ... Lead terminal, 15 ... Metal plating layer, 21 ... Dedicated electrode.

Front page continued (72) Inventor Kento Tsukamoto 1-5-1, Taito, Taito-ku, Tokyo Toppan Printing Co., Ltd. (72) Inventor, Sotaro Toki 1-5-1, Taito, Taito-ku, Tokyo Within the corporation

Claims (4)

[Claims] 1. A semiconductor chip having a plurality of electrodes, a lead frame having a plurality of lead terminals respectively connected to the electrodes of the semiconductor chip, a lead terminal of the lead frame and an electrode of the semiconductor chip. A connecting portion for individually connecting the electrodes by metal plating, an electrode portion that applies the same potential as the lead terminal of the lead frame to each electrode of the semiconductor chip during the metal plating at the connecting portion, and the electrode after the metal plating. And a cutting part for separating the part from each electrode of the semiconductor chip. 2. The electrode part comprises a wiring pattern which is drawn out from each electrode of the semiconductor chip and short-circuited at one end thereof, and at least one of lead terminals of the lead frame is an electrode of the semiconductor chip. Of 1
The semiconductor device according to claim 1, wherein the same electric potential as that of the lead terminal of the lead frame is applied to each electrode of the semiconductor chip through the wiring pattern by being in contact with one of the lead terminals. 3. The wiring pattern, wherein the electrode portion is drawn out from each electrode of the semiconductor chip and short-circuited at one end thereof, and the electrode pattern is connected to each electrode of the semiconductor chip via the wiring pattern. The semiconductor device according to claim 1, comprising a dedicated electrode for applying the same potential as the lead terminal. 4. A plurality of electrodes provided on the upper surface of a semiconductor chip and a plurality of lead terminals of a lead frame are brought into close proximity to each other or part of them are brought into contact with each other to adhere the lead frame onto the semiconductor chip. The same electric potential as that of each lead terminal of the lead frame is applied to each electrode of the semiconductor chip through a process and a wiring pattern which is drawn out from each electrode of the semiconductor chip and short-circuited at one end thereof. And, in this state, immersing both the semiconductor chip and the lead frame in an electrolytic plating solution to form a metal plating layer for individually connecting the lead terminals of the lead frame and the electrodes of the semiconductor chip. And, after forming the metal plating layer, cutting the wiring pattern to separate each electrode of the semiconductor chip. A method of manufacturing a semiconductor device, comprising: