JPH0784947A - Interface device - Google Patents

Abstract

PURPOSE:To decrease the scale of the interface device between a single-clock- phase synchronous system and a 4-cycle asynchronous system. CONSTITUTION:When a request signal (reqi) is 0, a (dataout) from a synchronous side is stored, and when an acknowledgement signal(acki) is 0 and the(clock) clck of the synchronous side is 1, the reqi is set to 1 and the dataout is transferred as (datain) to the asynchronous side; when the clock clock becomes 0 and the acki becomes 1, the reqi is set to 0 and new data from the synchronous side are stored. When the acki becomes 0, the initial state of data transfer from the synchronous side is entered; when an acknowledgement signal (acko) is 0, dataout from the asynchronous side are stored and when a request signal (reqo)and the clock clock of the synchronous side are 1, the acko is set to l and the dataout is transferred as datain to the synchronous side. When the reqo and clock clock are 0, the acko is set to 0, new data from the asynchronous side are stored, and a return to the initial state of data transfer from the asynchronous side is made.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a single-phase clock synchronous system.
m) and 4-cycle asynchronous system (four-cycle-signalli
ng asynchronous system) and the configuration of the interface device.

[0002]

2. Description of the Related Art A single-phase clock has been used to reduce power consumption and increase in skew as the clock frequency increases. A system using this clocking is described in the technical paper "DW Dobberpuhl et al.," A
200-Mhz 64-b Dual-Issue CMOS Microprocessor "IEEE J
ournal of Solid-State Circuits, Vol.27, No.11, pp.
The DEC chip 21064 of "1555-1567, No. 1992" is one of them. When designing such a system, the clock frequency is determined according to the slowest functional block between the registers. With this design method, it is considered that the high speed of the element obtained by the current circuit technology cannot be enjoyed.

On the other hand, recently, an asynchronous system (self-synchronous system) has been actively researched. With conventional technology,
Implementation of an all-self-synchronous system is considered to be rather difficult. To alleviate this, there is a trend towards incorporating self-synchronous functional blocks within synchronization systems. Therefore, an interface device between the synchronous system and the asynchronous system is required. As such an interface device, a technical paper "R. Traylor and D. Dunnin"
g, "Routing Chip Set for Intel Paragon Parallel Su
percomputer, "Hot Chips IV Symposium Record pages
7.1.1-7.1.13, August, 1992 ”, NIC (Network Int
erface Chip) shows one example.

[0004]

With regard to the handshake device according to the present invention, a technical paper "AJ Marti
n, SMBurns, TKLee, D. Borkovic and PJHazewindu
s, "The Design of an Asynchronous Microprocessor,"
in Charles L. Seits (Eds.) Decennial Caltech confe
rence, pp.351-373, MIT Press, 1989 '' and `` TH-Y. Meng,
RWBrodersen and DG Messerschmitt, "Automatic Sy
nthesis of Asynchronous Circuits from High-Level S
pecifications, "IEEE Trans. on CAD, Vol.8, No.11,
pp.1185-1205, Nov.1989 "and" Kagoya, Minatani, "A method of asynchronous control circuit synthesis by process description," IEICE technical report, Vol.91, VLD91-98, pp.75- 82,199
1 ”etc. However, due to the recent tendency to incorporate self-synchronizing functional blocks within synchronization systems, much has been announced about what acts as an interface device between the systems. Also,
Technical paper "R. Traylor and D. Dunning," Routing Chi
p Set for Intel Paragon Parallel Supercomputer, "H
ot Chips IV Symposium Record pages 7.1.1-7.1.13, A
ugust, 1992 "is for the whole handshake protocol and the control is based on the First-In-Firts-Out (FIFO) flags used on the input and output sides of the interface device circuit. Therefore, the scale of the interface device is large. By implementing it on a dedicated chip, problems such as area and power consumption are alleviated, but it is not used as an interface device with the subsystem by making a part of the existing synchronization system self-synchronized. For this reason, interface device arrangements that facilitate the incorporation of self-synchronizing subsystems on a small scale are desirable. It is an object of the present invention to provide such an interface device device.

[0005]

According to the present invention, an element having two states of storing and latching input data is provided to transfer data from the synchronous side, and a data input request signal reqi to the asynchronous side is provided. Is "0", the device is in the memory state, and when the data input acknowledge signal acki from the asynchronous side is "0" and the clock clock on the synchronous side is "1", reqi is "1".
Then, the device is latched and the data is transferred, and when the clock clock becomes "0" and acki becomes "1", r
Set eqi to "0" to put the device in the memory state, and acki is "0".
When it becomes, it returns to the initial state of data transfer from the synchronous side,
An element having two states of storing and latching input data is provided to perform data transfer from the asynchronous side, and when the data output acknowledge signal acko to the asynchronous side is "0", the element is set to the storing state. , When the data output request signal reqo from the asynchronous side and the clock clock on the synchronous side are "1", ack
When o is “1”, the device is latched and the data transfer is performed, and when reqo and the clock clock are “0”, acko
Is set to "0" to bring the element into a storage state, and control is performed so as to return to the initial state of data transfer from the asynchronous side (see FIG. 1).

[0006]

In the present invention, the clock cloc is used as described above.
When k is “1”, acki rises after the rising of reqi, reqi falls at the rising of clock “0” and acki, and acki falls after the falling of reqi. Data transfer to the asynchronous side is 4-
It is performed according to the cycle handshake, and when the clock clock is "1", acko rises after the rising edge of reqo and the clock clock goes to "0" and the falling edge of reqo
When cko falls, data transfer from the asynchronous side to the synchronous side is also performed according to the 4-cycle handshake. Therefore, it can be confirmed that the above device acts as an interface device between the synchronous system and the (self-synchronous) asynchronous system according to the 4-cycle handshake.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A general block diagram of the present invention is shown in FIG. A four-cycle handshake protocol is shown in FIG. FIG. 3 shows an embodiment for realizing the transfer from the synchronous side to the asynchronous side of FIG. Further, FIG. 5 shows an embodiment for realizing the transfer from the asynchronous side to the synchronous side of FIG. First, the circuit of FIG. 3 will be described.

The circuit for realizing the transfer from the synchronous side to the asynchronous side in FIG. 3 is one p-type MOS transistor 100 and two n-type MOS transistors 2, 00 and 201.
It consists of two negative elements 0 and 301 and one C-Muller element 400. The two-input C-Muller element outputs its value only when both inputs match, and keeps the existing output value when both inputs differ.
An embodiment of the C-Muller element of FIG. 3 having one denied input is shown in FIG. When the clock and acki signals in FIG. 7 are different, two p-type MOS transistors 102 and 103 and 20
The output "1" of the exclusive OR element composed of four n-type MOS transistors 4,205,206 and 207 is applied to the n-type MOS transistor 208 and the p-type MOS transistor 104, and the transistor 208 is in a conductive state. Next to 104
Transistor becomes a high impedance, and the negative value of the clock value is passed through the transistor of 208 and the p-type MO of 106
The output of the exclusive OR element is "0" when applied to a negative element composed of an S-transistor and an n-type MOS transistor of 210, and the output of the element is output as reqi and the values of the clock and acki signals match. Therefore, the transistor of 104 becomes conductive, the transistor of 208 becomes high impedance, and the p-type MOS transistor of which the reqi is already 105 is 105 and the n-type MOS of 209 are 104 transistors.
106 p-type MO through a negative element consisting of a transistor
The S-transistor and the n-type MOS transistor 210 are circulated and held by a negative element. In FIG. 3, re
When qi is "0", 100 transistors are turned on, and the data data out from the synchronous side is negated by the negation element 300 through the transistor and stored. acki is “0”
And clock is "1", reqi becomes "1" and transistor 100 is high impedance, and transistors 200 and 201
Is made conductive and the denied data out is a transistor
It is applied to the negative element 301 through 201. The negation value of the negated data out is negated by the negation element and is output to the asynchronous type side as data in. The output value is circulated and held in the negative element 300 by the transistor 200. Figure 4
The relationship of transitions between the control signals clock, reqi and acki in Fig. 3 is shown in the technical paper "TH-Y Meng, RW Brodersen and D.
G. Messerschmitt, "Automatic Synthesis of Asynchro
nous Circuits from High-Level Specifications, "IEE
E Trans. On CAD, Vol.8, No.11, pp.1185-1205, Nov.
STG (Signalling Transition Graph) proposed in 1989
Indicated by. The plus (+) of each signal in this graph indicates whether the signal rises to "1" or the value of "1", and the minus (-) indicates whether the signal falls to "0" or the value of "0". Represent The arrows on the graph represent the dependencies between the signals.

The circuit for realizing the transfer from the asynchronous side to the synchronous side in FIG. 5 is one p-type MOS transistor 101, two n-type MOS transistors 202 and 203, and 30
It consists of two negative elements 2 and 303 and one C-Muller element 401. An example of the C-Muller element of FIG. 5 is shown in FIG. When the clock and reqo signals in Fig. 8 match, 211 and
An n-type MOS having an output "1" of 213 is an exclusive NOR element constituted by two n-type MOS transistors 212 and four p-type MOS transistors 107, 108, 109 and 110.
Applied to the transistor and the p-type MOS transistor of 111, the transistor of 213 becomes conductive, the transistor of 111 becomes high impedance, the negative value of the clock value is passed through the transistor of 213, the p-type MOS transistor of 113 and the n-type of 215 Since the output of the exclusive-NOR element is “0” when the output of the negative element is output as acko and the values of the clock and reqo signals are different, the output of the exclusive-NOR element is “0”. The transistor becomes conductive, the transistor 213 becomes high impedance, and the 111 transistor is a p-type MOS transistor with an acco existing value of 112 and an n-type MOS transistor of 214.
113 p-type MO through a negative element consisting of a transistor
It is circulated and held by a negative element composed of an S transistor and an n-type MOS transistor 215. In FIG. 5, ac
When ko is “0”, the transistor 101 becomes conductive, and the data out from the asynchronous side is negated by the negating element 302 through the transistor and stored. reqo and c
When lock is “1”, ackco becomes “1” and transistor 101 is high impedance, and transistors 202 and 203 are high impedance.
Is made conductive and the denied data out is a transistor
It is applied to the negative element 303 through 203. The negation value of the negated data out is negated by the negation element and is output to the asynchronous type side as data in. The output value is circulated to and held in the NOT element 302 by the transistor 202. Figure 6
The relationship of transitions between the control signals clock, reqo and acko of FIG. 5 is shown in the above STG (Signalling Transition Graph). Another embodiment of the two-state device of FIGS. 3 and 5 is shown in FIG. This circuit is based on the technical paper "DW Dobberpu
hl et al., "A 200-Mhz 64-b Dual-Issue CMOS Micropro
cessor "IEEE Journal of Solid-State Circuits, Vol.2
7, No. 11, pp.1555-1567, No. 1992 ".

[0010]

The present invention is advantageous in terms of circuit area because it facilitates incorporation of a self-synchronous system into a synchronous system because of its simple structure and small scale.

[Brief description of drawings]

FIG. 1 is a diagram showing a general configuration of the present invention.

FIG. 2 is a time diagram of a protocol called 4-cycle and semi-handshake.

FIG. 3 is an embodiment for performing transfer from the synchronous side to the asynchronous side of the present invention.

4 is a STG (Signallin) for the control unit of the circuit of FIG.
g Transition Graph).

FIG. 5 is an embodiment for performing a transfer from the asynchronous side to the synchronous side according to the present invention.

FIG. 6 is a STG (Signallin) for the control unit of the circuit of FIG.
g Transition Graph).

7 is a C-Mull having one negated input of FIG. 3;
It is an implementation example of an er element.

FIG. 8 is an implementation example of the C-Muller element of FIG.

9 is another implementation of the latch portion of FIGS. 3 and 5. FIG.

[Explanation of symbols]

reqi ... Data input request signal to asynchronous side, acki ... Data input acknowledge signal to asynchronous side, reqo ... Data output request signal from asynchronous side, acco ... Data output acknowledge signal from asynchronous side, data out ... output Data, data in ... Input data, clock ... Clock, VDD ... Power supply, GND ... Ground, 300-303 ... Negative logic element, 100-116 ... P-type MOS transistor, 200-218 ... N-type MOS transistor, 400
~ 401 ... C-Muller element.

Claims (3)

[Claims] 1. A data output line and a clock on the synchronizing system side.
It has a clock input line and a data input line, and a data input line, data input request signal line (reqi), data input acknowledge signal line (acki), data output line, data output request signal line (reqo) on the asynchronous system side. And a data output acknowledge signal line (acko), and when the control signals of the reqi, acki, reqo and acko are "0", data transfer from the synchronous side to the asynchronous side or from the asynchronous side to the synchronous side You can start the
When the reqi control signal is "0", the data from the synchronous side is stored, and when the control signal of the acki is "0" and the clock clock is "1", the reqi signal on the asynchronous side is set to "1", The stored synchronous side data is latched and transferred to the asynchronous side, and when the asynchronous side acki signal is "1" and the clock clock is "0", the reqi signal is set to "0" and the data Transition from the latched state of to the state of synchronous side data storage,
When the control signal of the reqo and acko is "0", the data from the asynchronous side is stored, and when the reqo signal of the asynchronous side is "1" and the clock clock is "1", the acko signal of the asynchronous side is " 1 ", the stored asynchronous data is latched and transferred to the synchronous side, and when the asynchronous side reqo signal is" 0 "and the clock clock is" 0 ", the acco signal is" 0 ". The data latching state to the asynchronous side data storing state, and a cycle of data input from the asynchronous side to the synchronous side and data input from the synchronous side to the asynchronous side. An interface device between a synchronous system and an asynchronous system characterized by repeating. 2. In order to transfer data from the synchronous side to the asynchronous side, it has two inputs of negative values of the clock and acki, and only when both inputs match, the value is set as the reqi. The interface device apparatus according to claim 1, wherein a C-Muller element that outputs and outputs the existing output value when the both inputs are different is used. 3. In order to transfer data from the asynchronous side to the synchronous side, it has two inputs of the clock and reqo,
The C-Muller element that outputs the value as the acco only when both inputs match and uses the existing output value when the both inputs are different is used. The interface device described.