JPH0784835A - Microcomputer system - Google Patents

Abstract

PURPOSE:To prevent the microcomputer system from stopping operation unless 'H' is sent out of the ready terminal RDY of an external circuit consisting of a memory and an I/O device connected to the microcomputer. CONSTITUTION:When the microcomputer accesses the memory and I/O device, a counter 34 counts a system clock CLK unless 'H' is sent out of the ready terminal RDY of the memory and I/O device, and a system reset RST is generated by a D-FF 36 a certain time later in synchronism with the system clock CLK.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention
A microcomputer (hereinafter referred to as a microcomputer) formed by a chip or the like, an external memory connected to the microcomputer and input / output (hereinafter referred to as I / O)
The present invention relates to a microcomputer system including an external circuit such as a device, and particularly to a bus interface for accessing the external circuit.

[0002]

2. Description of the Related Art For example, in a one-chip microcomputer, when a memory or an I / O device having a long access time is used, a ready (R) is provided for the purpose of extending the access cycle.
EADY (hereinafter, referred to as RDY) terminals are provided. FIG. 2 is a schematic block diagram showing a configuration example of a conventional microcomputer system. The microcomputer 1 is composed of one chip, and a central processing unit (hereinafter referred to as CPU) that performs arithmetic processing according to a program, a program memory that stores the program, and a CPU.
Data memory for writing and reading data from and to I / O for exchanging data with external devices
It has an O section and the like. The microcomputer 1 has address terminals A0 to A15 for address output, data terminals D0 to D7 for data input / output, a negative phase read strobe terminal RD / for outputting a memory read signal, and a negative phase write strobe for outputting a memory write signal. The terminal WR /, the anti-phase IO read strobe terminal IORD / that outputs the I / O device read signal, the anti-phase IO write strobe terminal IOWR / that outputs the I / O device write signal, and the completion signal of the operation preparation of the external circuit It has a ready terminal RDY for input.

The address terminals A0 to A15 and the data terminals D0 to D7 are, via the address bus 2 and the data bus 3, address terminals A0 to A of the memory 4 for storing data.
15 and data terminals D0 to D7,
It is connected to the address terminals A0 to A15 and the data terminals D0 to D7 of the I / O device 5 for exchanging data with an external device. The anti-phase read strobe terminal RD / and the anti-phase write strobe terminal WR / are the anti-phase output enable terminal OE / and the anti-phase write enable terminal W of the memory 4.
It is connected to E / respectively. The negative-phase IO read strobe terminal IORD / and the negative-phase IO write strobe terminal IOWR / are connected to the negative-phase output enable terminal OE / and the negative-phase write enable terminal WE / of the I / O device 5, respectively. The ready terminal RDY of the memory 4 and the I / O device 5 is the ready terminal R of the microcomputer 1.
It is connected to DY. These address bus 2, data bus 3, anti-phase read strobe terminal RD /, anti-phase write strobe terminal WR /, anti-phase IO read strobe terminal IORD /, anti-phase IO write strobe terminal IOWR
The / and the ready terminal RDY function as an interface between the microcomputer 1 and the memory 4 and the I / O device 5. FIG. 3 is a time chart for explaining the operation of FIG. 2, in which the horizontal axis represents time and the vertical axis represents voltage. The operation of reading data from the I / O device 5 of FIG. 2 will be described with reference to this figure. First, the address held in the address register inside the microcomputer 1 is output from the address terminals A0 to A15 to the address bus 2, and at the same time, the reverse-phase IO read strobe terminal IORD / of the microcomputer 1 is reversed to the reverse of the I / O device 5. Low level to phase output enable terminal OE / (hereinafter referred to as "L")
Is sent. The I / O device 5 sends a high level (hereinafter referred to as “H”) to the ready terminal RDY of the microcomputer 1 when it is ready to respond to “L” from the negative-phase IO read strobe terminal IORD /. . As a result, the data designated by the address propagated through the address bus 2 becomes the data terminal D of the I / O device 5.
It is read from 0 to D7 and sent to the microcomputer 1 via the data bus 3.

[0004]

However, the conventional microcomputer 1 has the following problems. For example, I
When the / O device 5 is ready to respond to "L" from the negative-phase IO read strobe terminal IORD / of the microcomputer 1, it shifts to the next bus cycle, so "H" is set to the ready terminal RDY of the microcomputer 1. Send out. However, the ready terminal RD of the I / O device 5 is affected by noise or the like.
If "H" is not sent from Y, the bus cycle is not completed and the next operation cannot be started. Figure 4 shows I / O
3 is a time chart of FIG. 2 when “H” is not sent from the ready terminal RDY of the device 5. In FIG. 4, the microcomputer 1 is waiting for "H" to be input from the ready terminal RDY, and is in a state in which the operation is stopped. As described above, the microcomputer 1 has a problem that the operation is stopped unless "H" is input to the ready terminal RDY.
The present invention has the problem that the conventional technique has a problem that when the microcomputer accesses the memory and the I / O device, if "H" is not sent from the ready terminal RDY of the memory and the I / O device, the operation is stopped. The present invention provides a microcomputer that solves the problem of being lost and returns to operation after a certain period of time.

[0005]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, a first invention provides a CPU provided in a microcomputer for program-controlling a microcomputer system in synchronization with a system clock, and an external bus to the microcomputer. Connected,
An external circuit that activates a completion signal when preparation of a response to the instruction of the CPU is completed, and an external circuit provided in the microcomputer and controlled by the CPU, and the external circuit and the CPU when the completion signal is activated. The following measures are taken in a microcomputer system including a bus controller that controls an external bus cycle for transmitting and receiving data between the two. That is, the microcomputer includes counting means for counting the system clock while the completion signal is inactive after the start of the external bus cycle controlled by the bus controller, and a count value of the counting means is a predetermined value. And a reset means for generating a system reset signal for initializing the CPU when it reaches 0. In a second invention, in the same microcomputer as in the first invention, counting means for counting the system clock while the completion signal is inactive after the start of the external bus cycle controlled by the bus controller, A holding means for holding a value, a comparing means for comparing a match / mismatch between the output of the counting means and the output of the holding means, and the central processing unit is initialized when the comparison result of the comparing means is a match. Reset means for generating a system reset signal is provided in the microcomputer.

[0006]

According to the first aspect of the invention, since the microcomputer system is configured as described above, after the start of the external bus cycle, the external circuit completes the preparation for the response to the instruction of the CPU, and the completion signal from the external circuit. The counting means counts the system clock until is activated. After a certain period of time when the count value reaches a predetermined value, a system reset signal is generated from the reset means and the CPU is initialized. According to the second aspect of the invention, after the external bus cycle is started, the external circuit is
Until the completion of the response to the PU instruction and the activation of the completion signal, the comparison means compares the output of the counting means with the output of the holding means that holds the set value. When the comparison results match, the reset means generates a system reset signal, and the CPU is initialized. Therefore, the above problem can be solved.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment FIG. 5 is a block diagram of the essential parts of a microcomputer showing a first embodiment of the present invention. The microcomputer 10 is composed of one chip, and includes a CPU 20, a bus interface 30 which is one of I / O units, a program memory (not shown) for storing programs, and a data memory (not shown) for writing and reading data from the CPU 20. And so on. C for program control of the operation of the microcomputer system
The PU 20 has an internal data bus 21. The internal data bus 21 has a function of storing a program counter 22 for storing addresses for sequentially designating instructions stored in a program memory and a function of holding addresses of registers in a stack. Stack pointer 23, address register 2 that stores the execution address that specifies the operand of the instruction
4 and an instruction register 25 for fetching an instruction read from the program memory are connected. The instruction register 25 has a programmable logic array (Progra) having a function of outputting a signal for controlling each circuit in the microcomputer based on an instruction held in the instruction register 25.
A mmableLogic Array (hereinafter referred to as PLA) 26 is connected. In addition, the internal data bus 21 stores an accumulator 27 for temporarily storing a calculation result, data,
A register 28 used for temporary storage of data is connected. The accumulator 27 and the register 28 perform an operation on the data held in the accumulator 27 and the register 28, and the operation result is stored in the internal data bus 21.
The ALU 29 and the like for outputting to are connected. The input side of the bus interface 30 is connected to the internal data bus 21, the program counter 22, and the address register 24, and the output side address terminals A0 to A15 and the data terminals D0 to D7 are connected to the address bus 41 and the data bus 42, respectively. It is connected.

The bus interface 30 further includes a memory anti-phase read strobe terminal RD /, a memory anti-phase write strobe terminal WR /, an I / O device anti-phase read strobe terminal IORD /, and an I / O device anti-phase. The phase write strobe terminal IOWR / is provided. The address bus 41 and the data bus 42 are connected to a memory 43, which is an external circuit for storing data, and an I / O device 44, which is an external circuit for exchanging data with external devices. Anti-phase read strobe terminal RD / for memory and anti-phase write strobe terminal WR for memory
/ Is connected to the negative phase output enable terminal OE / and the negative phase write enable terminal WE / of the memory 43, respectively. Reverse phase read strobe terminal IO for I / O device
The reverse phase write strobe terminal IOWR / for RD / and I / O device is connected to the reverse phase output enable terminal OE / and the reverse phase write enable terminal WE / of the I / O device 44, respectively. The ready terminal RDY that outputs a completion signal of the memory 43 and the I / O device 44 is connected to the ready terminal RDY of the bus interface 30.

FIG. 1 shows a first embodiment of the present invention, which is shown in FIG.
It is a circuit diagram of the inside bus interface 30. The bus interface 30 includes a bus controller 31, and the bus controller 31 is connected to the memory 43 and the I / O device 44 of FIG. 5 via the address bus 41 and the data bus 42. Bus controller 31
Receives an address of the program counter 22 of FIG. 5 or an effective address designating an operand of an instruction stored in the address register 24, and supplies those addresses to the memory 43 and the I / O device 44 via the address bus 41. It has a function. Further, the bus interface 30 includes a counter 34, which is a counting unit, and a delay flip-flop (hereinafter, D−), which is a reset unit.
FF) 36 is provided. The ready terminal RDY of the bus controller 31 is connected to the ready terminal RDY of the memory 43 and the I / O device 44, and is also connected to one input side of the 2-input NAND gate 33 via the inverter 32. The signal line that outputs the bus cycle start signal S31 of the bus controller 31 is a NAND
It is connected to the other input side of the gate 33. Furthermore, N
The output side of the AND gate 33 is connected to the reset terminal R of the counter 34. The output terminal Q1, of the counter 34
Q2 and Q3 are respectively connected to the input side of a 3-input AND gate 35, and the output side of the AND gate 35 is a D-FF.
It is connected to the input terminal D of 36. A clock generation circuit (not shown) that generates the system clock CLK is connected to the clock input terminals of the counter 34 and the D-FF 36. . The system reset signal RST is output from the output terminal Q of the D-FF 36 in synchronization with the system clock CLK.
Is sent.

FIG. 6 is a time chart of FIGS. 1 and 5 when “H” is input to the ready terminal RDY.
Shows the case when "H" is not input to the ready terminal RDY.
6 is a time chart of FIG. 6 and 7
Indicates time on the horizontal axis and voltage on the vertical axis. The operation of reading data from the I / O device 44 of FIG. 5 will be described with reference to these drawings. (1) When "H" is input to the ready terminal RDY: Predetermined data is written in the address register 24 via the internal data bus 21 by an instruction from the CPU 20 of FIG. 6, the address register 24 of FIG.
Becomes the address designating the I / O device 44, and the instruction read cycle is started. And I / O
The device 44 is accessed, and at the same time, the bus cycle start signal S31 becomes "H". At this time, I / O device 4
Since "H" is not yet output from the ready terminal RDY of No. 4, the output of the inverter 32 is "H". That is, since the output signal S33 of the NAND gate 33 becomes "L" by the bus cycle start signal S31, the counter 3
4, the reset is released and the counting is started. Further, the address held in the address register 24 is sent from the bus controller 31 to the I / O device 44 via the address bus 41. At the same time, "L" is transmitted from the reverse phase read strobe terminal IORD / of the bus controller 31. The negative-phase output enable terminal OE / of the I / O device 44 is the negative-phase read strobe terminal IO.
When "L" is received from RD / and preparation for response to the signal is completed, "H" is sent from the ready terminal RDY. Ready terminal RDY of bus controller 31 is "H"
Data is received from the I / O device 44 via the data bus 42. The data read thereafter is sent to the accumulator 27 via the internal data bus 21. In addition, “H” sent from the ready terminal RDY of the I / O device 44 is NANDed by the inverter 32.
It is also input to the gate 33. And the NAND gate 33
Output signal S33 becomes "H" and the counter 34 is reset.

(2) When the ready signal RDY is not input In FIG. 7, the bus cycle is started and the counter 34 starts counting similarly to (1) when “H” is input to the ready terminal RDY. However, I / O device 4
Since the ready terminal RDY of No. 4 does not send "H", the ready terminal RDY of the bus controller 31 waits until "H" arrives. On the other hand, the counter 34 continues counting, and when all the outputs of the output terminals Q1, Q2 and Q3 of the counter 34 become "H", the D-FF is passed through the AND gate 33.
The input terminal D of 36 becomes "H", and the system clock C
The system reset signal RST is sent from the output terminal Q of the D-FF 36 in synchronization with LK. As described above, in the first embodiment, the ready terminal R is set after the start of the bus cycle.
When “H” is not input to DY, when the count value of the counter 34 reaches a predetermined value, the input terminal D of the D-FF 36 becomes “H” via the AND gate 33, synchronizing with the system clock CLK. The system reset signal RST is sent from the output terminal Q of the D-FF 36 to reset the microcomputer. Therefore, the memory 43 may be affected by noise or the like.
If the I / O device 44 or the I / O device 44 malfunctions and cannot send the ready signal, the microcomputer is reset, and the CPU executes the initialization program again, so that the microcomputer 1
0, the memory 43, and the I / O device 44 can be returned to the normal operation state.

Second Embodiment FIG. 8 is a circuit diagram of a bus interface 30A showing a second embodiment of the present invention, which is common to the elements shown in FIGS. 1 and 5 showing the first embodiment. Are assigned common reference numerals. In the first embodiment, the output terminal Q of the counter 34
1, Q2 and Q3 are connected to the input side of the AND gate 35, but in the second embodiment, they are connected to the first input side of the comparison circuit 38 which is the comparison means, and the register which is the holding means. 37 have been added. Second comparator circuit 38
A register 37 for holding the data of the internal data bus 21 is connected to the input side of. Output terminal of the comparison circuit 38
comp is connected to the input terminal D of the D-FF 36. The clock input terminals of the counter 34 and the D-FF 36 are
The system clock CLK is input to each. DF
The system reset signal RST is transmitted from the output terminal Q of F36 in synchronization with the system clock CLK. . Next, the operation of reading data from the I / O device 44 of FIG. 5 will be described. According to an instruction from the CPU 20, predetermined data is stored in the register 37 in the internal data bus 2
Written through 1. After that, when a bus cycle occurs, the address in the address register 24 becomes I / O.
The address for designating the device 44 is set to start the instruction read cycle. When the I / O device 44 is accessed, the bus cycle start signal S31 becomes "H".
At this time, the ready terminal RDY is "L", and the counter 3
4 is released from reset and starts counting. The output terminals Q1, Q2, and Q3 of the counter 34 are input to the comparison circuit 38 and compared with the data held in the output terminals D1 to D3 of the register 37. CPU2 during normal operation
By inputting “H” to the ready terminal RDY within the access time designated by 0, the output terminals Q1, Q2 and Q3 of the counter 34 and the output terminals D1 to D1 of the register 37 are input.
Before the data held in D3 matches, the counter 3
4 is reset.

As described above, the second embodiment has the same advantages as the first embodiment. Further, since the data held in the output terminals D1 to D3 of the register 37 can be set by the program stored in the memory, the timing at which the system reset RST occurs at the stage of adjusting the system can also be set by the program. The present invention is not limited to the above embodiment, and various modifications can be made. The following are examples of such modifications. (A) The counter 34 of the first and second embodiments may be composed of other counting means such as a shift register. (B) The timing at which the system reset RST in FIG. 7 occurs may be earlier or later than in the first embodiment. (C) The D-FF 36 may be replaced with another FF such as JK-FF. (D) The register 37 may be replaced with other holding means such as a D-FF. (E) The comparison circuit 38 only needs to have a function of detecting the coincidence of the outputs of the counter 34 and the register 37.
It may be replaced with an -OR circuit, an EX-NOR circuit, an AND circuit, or the like. (F) The present invention can be applied to a multi-chip microcomputer in which a CPU and a memory are separated by adding a reset circuit to the outside.

[0014]

As described in detail above, according to the first aspect of the invention, when the ready signal is not input after the start of the bus cycle, the system clock is counted and the reset signal is generated when the count value reaches a predetermined count value. However, since the circuit for resetting the system of the microcomputer is provided, the microcomputer is reset when the ready signal cannot be transmitted due to the malfunction of the memory or the I / O device due to the influence of noise or the like. After that, the system can be returned to the normal operating state by executing the initialization program again. According to the second aspect of the invention, when the ready signal is not input after the start of the bus cycle, the system clock is counted, a reset signal is generated when a predetermined count value is reached, and a circuit for resetting the system of the microcomputer is provided. The microcomputer is reset when the ready signal cannot be transmitted due to the malfunction of the memory or the I / O device due to the influence of noise or the like. Further, since the timing for resetting this microcomputer can be set by a program, the timing for returning the system to the normal operating state can be set to an optimum value.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a bus interface in a microcomputer showing a first embodiment of the present invention.

FIG. 2 is a schematic block diagram of a conventional microcomputer system.

FIG. 3 is a time chart of FIG.

FIG. 4 is a time chart when there is no RDY input in FIG.

FIG. 5 is a configuration block diagram of a main part of a microcomputer system showing a first embodiment of the present invention.

6 is a time chart of FIGS. 1 and 5. FIG.

FIG. 7 is a time chart when there is no RDY input in FIGS. 1 and 5.

FIG. 8 is a circuit diagram of a bus interface in a microcomputer showing a second embodiment of the present invention.

[Explanation of symbols]

 10 Microcomputer 20 CPU 30, 30A Bus Interface 31 Bus Controller 32 Inverter 33 2 Input NAND Gate 34 Counter 35 3 Input AND Gate 36 D-FF 37 Register 38 Comparison Circuit 43 Memory 44 I / O Device

Continuation of the front page (51) Int.Cl. ⁶ Identification number Office reference number FI technical display location H03K 19/018

Claims (2)

[Claims] 1. A central processing unit provided in a microcomputer for controlling a microcomputer system program in synchronization with a system clock; and a central processing unit connected to the microcomputer via an external bus for responding to a command from the central processing unit. An external circuit for activating a completion signal when preparation is completed, and a circuit provided in the microcomputer and controlled by the central processing unit, and between the external circuit and the central processing unit when the completion signal is activated. And a bus controller for controlling an external bus cycle for transmitting and receiving data in the microcomputer system, wherein the completion signal is inactive after the start of the external bus cycle controlled by the bus controller. Counting means for counting the system clock, and the counting means Microcomputer system count value, characterized in that the reset means for generating a system reset signal for initializing said central processing unit upon reaching a predetermined value, is provided in the microcomputer. 2. A central processing unit, which is provided in the microcomputer and program-controls the microcomputer system in synchronization with a system clock, and a central processing unit which is connected to the microcomputer via an external bus and which responds to a command of the central processing unit. An external circuit for activating a completion signal when preparation is completed, and a circuit provided in the microcomputer and controlled by the central processing unit, and between the external circuit and the central processing unit when the completion signal is activated. And a bus controller for controlling an external bus cycle for transmitting and receiving data in the microcomputer system, wherein the completion signal is inactive after the start of the external bus cycle controlled by the bus controller. Counting means for counting the system clock and holding set value Holding means, comparing means for comparing the output of the counting means with the output of the holding means for a match / mismatch, and a system reset signal for initializing the central processing unit when the comparison result of the comparing means is a match. And a resetting means for generating the above, provided in the microcomputer.