JPH0766730A - Delta-sigma modulation type a/d converter - Google Patents

Abstract

PURPOSE:To prevent a digital output signal from including noise due to circuit drifting by increasing the frequency of an operation clock so as to be less than a threshold indicating no inclusion of noise within a prescribed frequency band. CONSTITUTION:A clock frequency setting part 62 judges whether a power- calculated value exceeds a threshold or not. Since a judged result that the power-calculated result is larger than the threshold indicates the mixture of a noise component in a frequency band less than the cut-off frequency, a clock frequency setting part 62 updates a clock by adding frequency increment DELTAf to current clock frequency fck in order to move the frequency of the noise component to the outside of the cut-off frequency. Since the setting part 62 applies set voltage CO corresponding to the clock frequency (fck+DELTAf) to a VCO 63, the VCO 63 applies a clock CK having the clock frequency (fck+DELTAf) to a comparator 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an A / D converter, and more particularly to a delta-sigma modulation type A / D converter.

For example, on the reception side of a transmission device in ISDN, it is preferable that the circuit mounting scale be small. From this fact, a 1-pin structure delta-sigma modulation type A is used.
The / D converter is drawing attention.

[0003]

2. Description of the Related Art FIG. 7 shows a basic structure of a conventionally known delta-sigma modulation type A / D converter.
1 is an integrator (amplifier) for integrating an analog input signal, 2
Is the output value of the integrator 1 is a threshold value V _C (for example, 0.5 V)
Comparator that outputs 1-bit data in comparison with
Is an averaging filter (low-pass filter) that averages 1-bit data from the comparator 2 and passes only components within a predetermined frequency band, and 4 is a 1-bit D that converts the 1-bit data from the comparator 2 into a corresponding analog signal. / A converter, 5 is a subtracter that subtracts the analog signal from the 1-bit D / A converter 4 with respect to the input signal A _IN and gives it to the integrator 1, and CKO generates the clock signal CK for the comparator 2. It is a clock generator for doing.

The operation of such a delta-sigma modulation type A / D converter will be described with reference to the numerical examples shown in FIGS.

Now, assuming that the analog input signal A _IN = 0 [V] for simplification of description, as shown in FIG. 8, when the number of clocks CK is “1”, that is, in the initial state, subtraction is performed. The output signal V1 of the integrator 5 is not output, so that the output signal V2 of the integrator 2 is also "0". Therefore, since a voltage lower than the threshold value V _C is input to the input terminal P of the comparator 2, an L level output signal DI is generated from the output terminal O thereof, and the averaging filter 3 and the 1-bit D signal are output.
It is sent to the / A converter 4.

In the 1-bit D / A converter 4, when the output signal DI from the comparator 2 is at H level, +
1 [V] is generated as the output signal A _O , and the output signal DI
Is at the L level, -1 [V] is generated as the output signal A _O and is given to the subtractor 5.

In the above example, since the output signal DI of the comparator 2 is L level, the output signal A _O of the D / A converter 4 becomes -1 [V] and is given to the subtractor 5.

At the next clock (the number of clocks = 2), the analog input signal A _IN of the subtractor 5 is 0 [V] and the output signal A _O from the D / A converter 4 is -1 [V]. Therefore, the output signal V1 of the subtractor 5 becomes 1 [V] and is given to the integrator 1. Therefore, the output signal V of the integrator 2
2 also has a voltage 1 [V] corresponding thereto, and becomes larger than the threshold value V _C in the comparator 2, so that the output signal DI at the output terminal O becomes H level. As a result, the output signal A _O of the D / A converter 4 is +1 [V].
Is given to the subtractor 5.

In this way, each time the number of clocks increases, the output of the comparator 2 alternately repeats the L level and the H level as shown in the figure, and similarly the 1-bit D / A converter 4
The output signal A _{O of} -1 [V] and +1 [V] also repeats (see FIG. 9).

Therefore, the output signal D of the averaging filter 3
The output signal DI of the comparator 2 is regularly repeated between the L level and the H level as shown in FIGS. 8 and 9, so that _OUT becomes closer to 0 [V] as the number of averaging clocks increases. .

In this way, the difference between the analog input signal and the signal obtained by converting the digitized data of one clock before into the analog signal again by the D / A converter is integrated, so that the delta-sigma modulation type A / D is used. Although called a converter, the number of quantization bits in such a conversion operation is extremely small at 1 bit, and therefore the averaging filter 3 is used to reduce the quantization noise. By passing only the low frequency component at, the accurate analysis with less noise component can be expected in the subsequent FFT analysis device or the like (not shown).

Although it has been described that the analog input signal A _IN is 0 [V] in FIGS. 8 and 9, the output signal DI of the comparator 2 is L because the analog input signal A _IN naturally changes. Instead of repeating the level and the H level, the L level is continuously output or the H level is continuously output, and the digital output signal D _OUT corresponding to the analog input signal A _IN is averaged by the averaging filter. 3 will be generated.

[0013]

In the delta-sigma modulation type A / D converter as described above, the 1-bit D / A converter 4 has a dynamic range of +1 [V depending on the logic level of the input signal DI thereof. ] And -1 [V] is the ideal operating state, but in the case of an LSI, an extreme case is that an error of 0.2 V occurs on the positive side. There are ideal operating conditions.

Therefore, the input / output relationship of the 1-bit D / A converter 4 is +0.8 [V] for the H level input and -1.0 [V] for the L level input. In some cases, the error of the integrator itself is added to this, and the ideal operation example shown in FIG. 8 becomes a non-ideal operation example as shown in FIG.

That is, for example, in the initial state as shown in the drawing,
Outputs -1 [V] from the 1-bit D / A converter 4,
As a result, even in this example, the analog input signal of 0 [V] is obtained.
Issue A _INAnd the output signal V1 from the subtractor 5 is 1
[V] is given to the integrator 1, and output from the integrator 1
Force signal V2 becomes 1 [V], and the output signal of comparator 2
The number DI becomes H level.

Then, the output signal D of this comparator 2
When I becomes H level, the D / A converter 4 outputs 0.8 [V] as the output signal A _O unlike the example of FIG. 8, and this is given to the subtractor 5, whereby the subtracter 5 Output signal V1 of -0.8 [V], and thus the output voltage V2 of the integrator 1 becomes 0.2 [V].

In this way, the output signal V1 of the subtractor 5 is +
1 [V] and -0.8 [V] are alternately repeated, and similarly, the output signal of the 1-bit D / A converter 4 is also -1 [V] and 0.8 [V] alternately repeated. The output signal V2 of the integrator 1 is 0 → 1 → 0.2 → 1.2 → 0.4.
[V] ... fluctuates as shown in FIG. 11 and is shown by a dotted line.

What can be understood from FIG. 11 is that the output signal V2 of the integrator 1 shows a periodic drift of a new cycle T1 (frequency f1).

This periodicity is shown in FIG. 2 (1).
When the cutoff frequency F of the averaging filter 3 is lower than
If it does, it will pass the filter 3 and the digital output signal
Issue D _OUTWill be included in.

Therefore, there is a problem that the noise characteristic is extremely deteriorated during the FFT analysis in the FFT device connected to such an A / D converter.

Therefore, according to the present invention, an integrator for integrating an analog input signal, a comparator for comparing an output value of the integrator with a threshold value to output 1-bit data, and an average of the 1-bit data for a predetermined frequency band. A filter for passing only the internal component, a 1-bit D / A converter for converting the 1-bit data into a corresponding analog signal, and the 1-bit D / A
In a delta-sigma modulation type A / D converter having a subtracter for subtracting an analog signal from a converter with respect to the input signal and giving the subtractor to the integrator, due to a circuit drift in a final digital output signal. The purpose is not to include noise.

[0022]

In order to achieve the above object, a delta-sigma modulation type A / D converter according to the present invention has an output value of an averaging filter 3 as shown in principle in FIG. Is obtained, and a control unit 6 for increasing the operation clock frequency of the comparator 2 is provided so that this power becomes equal to or less than a threshold value indicating that noise due to drift is not included within a predetermined frequency band. is there.

In the above case, the control section 6 generates a power calculation section, a voltage generation section for generating an output voltage value according to the calculation result of the power calculation section, and a clock having a frequency corresponding to the output voltage value. It can be configured with a voltage controlled oscillator.

Further, in the above, the voltage generator is the RO
It is possible to configure with M and a resistance voltage dividing circuit that selectively generates an analog voltage according to the output signal of the ROM.

[0025]

In the present invention, as shown in FIG.
The period T1 of the waveform of the output of the integrator shown in FIG. 2 is contracted to the period T2 as shown in FIG. 12, whereby the drift noise component f1 (period of the period due to the D / A converter 4 and the like as shown in FIG. 1 / D1) is increased, and thereby the frequency of the cutoff frequency F of the averaging filter 3 is to be moved out of the band.

Therefore, in the control unit 6, in order to detect the periodic component based on the drift state of the circuit as shown in FIG. 11, the power of the output value of the filter 3 is obtained as the one corresponding to the frequency, and this power is obtained. The clock frequency of the comparator 2 is increased so that is equal to or less than a threshold value indicating that noise due to drift is not included within the band of the predetermined cutoff frequency F of the averaging filter 3.

By thus increasing the frequency of the noise component from the frequency f1 to f2, it is possible to avoid the noise component from being included in the FFT analysis or the like using the output of the A / D converter.

[0028]

FIG. 3 shows a delta-sigma modulation type A according to the present invention.
An example of the A / D converter is shown.
The control unit 6 controls the digital output signal from the averaging filter 3.
D _OUTPower calculation unit 6 for inputting and calculating the power
1 and the calculation result (n bits) of this power calculation unit 61
Input to set the clock frequency of comparator 2.
Frequency setting unit 62 for generating a set voltage CO for
And the frequency corresponding to this by inputting this set voltage CO
f_CKVoltage control to supply the clock CK of
It is composed of an oscillator (VCO) 63. In addition, other
Since the configuration is the same as the conventional example shown in FIG. 7, the description is omitted.
To do.

Next, the operation of the control section 6 of the embodiment shown in FIG. 3 will be described below with reference to the flow chart of FIG.

First, the clock frequency setting unit 62 initializes the operating clock frequency f _CK of the comparator 2 in advance (step S1).

Then, the power calculator 61 samples the digital output signal D _OUT of the averaging filter 3 N times and inputs it (step S2).

Power calculation is performed from the N digital output signals D _OUT thus fetched (step S
3).

Then, the clock frequency setting unit 62 determines whether or not the power-calculated value P exceeds the threshold value P _H (step S4). In this case, this threshold value P _H indicates a power threshold value corresponding to a frequency that is equal to or lower than the cutoff frequency F of the averaging filter 3 shown in FIG. 2 and indicates that the noise of the circuit drift by the D / A converter 4 is not included. There is.

As a result of the judgment in step S4, when it is found that the power calculation result P is larger than the threshold value P _H , the frequency f is lower than the cutoff frequency F as shown in FIG.
Since the noise component due to 1 is mixed, the clock frequency setting unit 62 adds the frequency increment Δf to the current clock frequency f _CK in order to move the noise component frequency f1 to the outside of the cutoff frequency F. To update the clock (step S5).

At this time, the clock frequency setting unit 62 gives the set voltage CO corresponding to the clock frequency (f _CK + Δf) to the VCO 63, so that the VCO 63 gives the clock CK having this clock frequency (f _CK + Δf) to the comparator 2. Will be done.

After the steps S2 to S5 are repeated in this way, when the power calculation result P becomes less than or equal to the threshold value P _H , the frequency f2 at which the noise component frequency f1 is higher than the cutoff frequency F as shown in FIG. Since it can be seen that the clock frequency of the comparator 2 has been moved to, the clock frequency of the comparator 2 is fixed at this point.

FIG. 5 shows an embodiment of the clock frequency setting unit 62 shown in FIG. 3. In this embodiment, the n-bit output from the power calculation unit 61 is inputted and the corresponding n-bit control is carried out. It is composed of a ROM 621 which outputs a signal, and a resistance voltage dividing circuit 622 which receives an n-bit output of the ROM 621 and generates a desired clock setting voltage CO.

The resistance voltage dividing circuit 622 is
Switches SW1 to SWn that are turned on / off by the n-bit output of M621 and these switches SW1 to S
A resistor Ro commonly connected to the fixed contact side of Wn and a switch S connected in series with each other and between the resistor Ro and the resistor Ro.
W1 to SWn are connected to resistors R1 to Rn. Further, a set voltage output CO is given from the connection point of the resistors R1 and R2 and output to the VCO 63.

FIG. 6 shows the memory table of the ROM 621 shown in FIG. 5 and the input / output values of the VCO 63.
In this embodiment, the number of input / output bits of the ROM 621 is 5 bits.

As shown in this embodiment, since the power calculation is not performed in the ROM 621 before the data is input, all the power calculation values are "0".
The output of OM621 becomes "00001" and the switch SW1
Only the bit that turns ON only is "1". At this time, the combined resistance of the resistor Ro and the resistor R1 is Ro /
(Ro + R1). Then, the input voltage signal CO of the VCO 63 becomes 1 [V], so that the output is 1 MHz.

On the other hand, when the calculation result from the power calculation unit 61 is input to the ROM 621, the higher output bit of the ROM 621 is "1" according to the input data, and the higher output bit is "1". The output signal CO is generated so that the bit of the lower one becomes "1".

For example, when the calculated power value is "00100", the output of the ROM 621 is also "00100", and the output voltage CO due to this is closed by the switch SW3.
(R1 + R2 + R3) / R1 + R2 + R3 + Ro), and the voltage is given as 3 [V], so VCO6
The output frequency of 3 is 20MHz.

In this way, the output frequency of the VCO 63 is made variable, and the output of the VCO 63 according to the power calculation result,
That is, the clock frequency for the comparator 2 is determined.

[0044]

As described above, according to the delta-sigma modulation type A / D converter of the present invention, the power of the output value of the averaging filter is obtained, and this power is within the cutoff frequency band of the filter. Since the clock frequency of the comparator is increased so that it is below the threshold value indicating that noise due to drift is not included, it is possible to move the drift noise component due to the error in the circuit to the high frequency band, and average it. Since it can be blocked by the digitizing filter, the noise component can be improved in the subsequent FFT analysis and the like.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing in principle the configuration of a delta-sigma modulation type A / D converter according to the present invention.

FIG. 2 is a diagram for explaining the operation of the delta-sigma modulation type A / D converter according to the present invention.

FIG. 3 is a block diagram showing an overall configuration of an embodiment of a delta-sigma modulation type A / D converter according to the present invention.

FIG. 4 is a flow chart diagram for explaining the operation of the control unit shown in FIG.

5 is a circuit diagram showing an embodiment of a clock frequency setting unit shown in FIG.

6 is a table diagram showing an example of input / output data of the ROM and VCO shown in FIG.

FIG. 7 is a circuit diagram showing a conventionally known delta-sigma modulation type A / D converter.

8 is a diagram showing an operation example when an analog input signal is set to 0 [V] in the conventional example shown in FIG.

9 is a graph showing the operation example shown in FIG. 8 with respect to a comparator output.

10 is a diagram showing a numerical example at the time of non-ideal operation in the conventional example of FIG.

FIG. 11 is a graph showing an integrator output when performing a normal operation in the conventional example.

FIG. 12 is a graph showing an integrator output when the operation shown in FIG. 11 is developed into a high speed operation as in the present invention.

[Explanation of symbols]

 1 integrator 2 comparator 3 averaging filter 4 1-bit D / A converter 5 subtractor 6 control unit 61 power calculation unit 62 clock frequency setting unit 63 voltage controlled oscillator (VCO) 621 ROM 622 resistance voltage dividing circuit SW1 to SWn switch Ro, R1 to Rn voltage dividing resistors In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (3)

[Claims] 1. An integrator (1) for integrating an analog input signal, and an output value of the integrator (1) is compared with a threshold value to obtain 1
A comparator (2) that outputs bit data, a filter (3) that averages the 1-bit data and passes only a component within a predetermined frequency band, and a 1-bit D / that converts the 1-bit data into a corresponding analog signal. A converter (4)
And a subtracter (5) for subtracting an analog signal from the 1-bit D / A converter (4) with respect to the input signal and giving the subtractor (5) to the integrator (1). In the D / D converter, the power of the output value of the filter (3) is calculated, and the clock frequency of the comparator (2) is adjusted so that the power is equal to or less than a threshold value indicating that noise due to drift is not included in the predetermined frequency band. A delta-sigma modulation type A / D converter characterized in that a control section (6) for raising the temperature is provided. 2. The control unit (6) includes a power calculation unit, a voltage generation unit that generates an output voltage value according to a calculation result of the power calculation unit, and a clock having a frequency corresponding to the output voltage value. 2. A delta-sigma modulation type A / according to claim 1, characterized in that
D converter. 3. The delta converter according to claim 2, wherein the voltage generator is composed of a ROM and a resistance voltage dividing circuit that selectively generates an analog voltage according to an output signal of the ROM. Sigma modulation type A / D converter.