JPH0760571B2 - Address data processing method of disk reproducing device - Google Patents

Description

TECHNICAL FIELD OF THE INVENTION The present invention relates to an apparatus for reproducing a compact disc or the like on which digital audio information is recorded, and to an address data processing system of the disc reproducing apparatus.

[Technical Background of the Invention] An optical disk reproducing device has been developed which uses a laser beam for pickup. This type of device has a random access function for controlling movement of the pickup unit to an arbitrary position on the disc. As a result, it is possible not only to continuously reproduce the audio signal from the beginning of recording the disk but also to reproduce the arbitrary music piece according to the user's request.

Therefore, address data is recorded on the recording track of the disc. The random access function controls the position of the pickup unit by searching the address data. In this case, some of the address data may be missing or may be mixed with noise, so that an error check code is usually added to obtain the accuracy of data determination. That is, as shown in FIG. 6, the error check code 12 is added to the address data 11.

[Problems of Background Art] By the way, an optimum method is selected for the error check code depending on an error occurrence form such as a random error which occurs relatively sporadically or a burst error which occurs continuously.

The basic conditions required for the above error check code are as follows.

(A) High error detection capability for all types of errors.

(B) Redundancy for data is low.

(C) An error detection algorithm has been established and can be embodied in integration and the like.

The conditions (a) and (b) are contradictory to each other and are greatly influenced by the structure of the data to be reproduced. Therefore, it is almost impossible to satisfy both of these conditions at the same time.
That is, if the error detection capability is increased, the redundancy, that is, the number of bits of the error check code will naturally increase.

In the case of a compact disc reproducing device, 16 bit error check bits are prepared for 80 data bits. However, even with such a format, error error detection occurs at a ^{probability of} 2- ^(80-16) , that is, 1/2 ⁶⁴ times, for a burst-like error of 18 bits or more. In other words, even if there is an error in the data, it may be judged as normal. Since there is no means for judging such a situation in the reproducing apparatus, there is a problem that the system is controlled by using the originally incorrect data.

Now, consider the case of trying to search for an arbitrary position. When a device search start operation is performed, the target address data A and the address data B at the current position are compared in size, the absolute value difference between them is calculated, and the movement direction and movement distance of the pick-up portion are calculated. Can be decided In such a case, if the address data B at the current position is determined as the address data B1 by the error error detection, naturally,
The calculation result may be incorrect, and the pickup unit may be moved in a position direction completely different from the target position. FIG. 7 shows the situation of the malfunction.

The invention of [Object of the invention] is made in view of the above, and paying attention to the fact that the address data determined to be correct by the error check code are correlated with each other.
It is an object of the present invention to provide an address data processing method for a disc reproducing apparatus, which can significantly reduce the data error determination probability by monitoring the correlation.

[Outline of the Invention] In the present invention, for example, as shown in FIG. 1, the address data reproduced in time is compared with each other, and the correlation between them is observed. It is determined whether or not it is within the range. Then, if it is within the predetermined range, the data reproduced later is determined as true data, and if it is outside the predetermined range, the data before and after being reproduced one after another is compared and the predetermined condition is satisfied. It is determined whether or not it is satisfied. As a result, the data used for controlling the system is always normal data.

[Embodiment of the Invention] An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of the present invention, in which 20 is an optical disc and 21 is an optical pickup section. The signal detected by the optical pickup unit 12 is amplified by the amplifier 13,
The data is input to the data demodulator 14, separated into control data and audio data, and the audio data is input to the digital-analog converter 15 and output to the speaker 16 side as an analog audio signal. Of the control data, the address data is error-checked by the error checker 17 using the error check code. Here, when the determination result that there is no error is obtained, the address data is stored in the first address data memory 18. Also the first so far
The address data stored in the address data memory 18 is transferred to the second address data memory 20.
Next, the address data of the first address data memory 18 and the address data of the second address data memory 20 are compared in size by the comparator 19. Here, the address data A (contents of the memory 18) is the address data B (contents of the memory 20).
If it is larger, that is, if A ≧ B, the output of the logic “1” is obtained from the comparator 19. At this time, the absolute value detector 21 calculates the absolute value difference between the address data A and the address data B, and if the difference is within a predetermined value, an output of logic "1" is obtained. When the output of the logic "1" is obtained from the comparator 19 and the absolute value detector 21, the output of the logic "1" is obtained from the AND circuit 22. In this case, the third address data memory 23 receives and stores the address data of the first address data memory 18. For the first time, the address data that can be actually used is obtained,
This is input to the microcomputer 24 and decoded.

Next, the case where the error checker 17 detects a data error will be described. In this case, no data is moved between the first address data memory 18 and the second address data memory 20.

Next, the case where the output of the logic "1" is not obtained from the AND circuit 22 will be described.

In this case, it is determined whether the comparison result in the comparator 19 is determined as A <B or the calculation result in the absolute value detector 21 is equal to or more than a predetermined value. In such a case, this system does not transfer the data in the first address data memory 18 to the third address data memory 23, but only repeats the data processing before this transfer processing. Therefore, the address data having no correlation with the adjacent address data is always excluded, and even if the error checker 17 makes a wrong decision and actually judges the wrong data to be the first address, The data stored in the data memory 18 is the third
Address data memory 23 is not transferred. In other words, this system is capable of further error checking by the data error checking function. As a result, it is prevented that the correct address data is always input to the third address data memory 23, that is, the microcomputer 24, and unexpected operation of the system occurs.

FIG. 2 is a flowchart showing the operation of the above system, in which steps S1 to S9 are repeated.

FIG. 3 shows a control data format of a compact disc on which audio information is recorded. Each symbol of this format will be explained.

SOSI ... A synchronization pattern that indicates the beginning of address data.

CTL: Control unit that distinguishes pre-emphasis and 2 or 4 channels.

ADR: Mode section that indicates whether it is address data or other data.

TNO: A track number section that identifies the track where digital data is stored.

X ... Index part that further identifies the track divided by TNO.

MIN: A portion (hereinafter, referred to as a relative address) indicating the elapsed time (minutes) after the reproduction of the digital data of the predetermined music number is started.

SEC ... Part of the relative address that indicates seconds.

FRAME: A part that indicates the unit time obtained by dividing the relative address second by 75.

ZERO: A part that is digital zero data (hereinafter referred to as an absolute address).

AEC: The part that indicates the second of the absolute address.

AFRAME ... The part that indicates the unit time that divides the second of the absolute address by 75.

CRCC: Error check code for all data except SOSI above.

FIG. 4 schematically shows the temporal changes of MIN, SEC, FRME, AMIN, ASEC and AFRAME. That is, AMI
N, ASEC, and AFRAME are addresses that change continuously from the beginning to the end of the disk, not the non-continuous addresses that are reset each time TNO changes, like MIN, SEC, and FRME. Can be used to examine the correlation.

In the present invention, the address data having the correlation between the values before and after the start to the end of the disc as described above is used.

FIG. 5 shows an example in which address data is actually detected by the system of the present invention. That is,
Consider the case where the absolute address currently being played is t1, the next reproduced absolute address is t1 + 1, and the next reproduced absolute address is judged as an error by the error checker 17 and becomes tx. However, it is assumed that tx <t1 and the absolute value difference is set to "1".

First, for t1 + 1, since the conditions of t1 + 1> t1 and t1 + 1−t1 = 1 are satisfied, the data t1 + 1 is used as normal data.

However, for tx, tx> t1 + 1 is satisfied, but the above-described difference condition is not satisfied, so the data of tx is determined as error data. Next, when the reproduced address data is t1 + 3, t1 + 4 ..., t1 + 3 <tx
Therefore, t1 + 3 is determined as an error, but in the next cycle, t1 + 4> t1 + 3, (t1 + 4)-(t1 +
3) = 1 and t1 + 4 is determined as a normal address. Therefore, the route indicated by the broken line in FIG. 5 is treated as a normal address.

As described above, according to the present invention, it is possible to significantly reduce the occurrence probability of error error detection of address data, and to obtain sufficient practical accuracy without using a high-level method for the original error checking code. Processing can be performed. Further, by realizing this function by software of a microcomputer, the original error detection capability can be reduced to a low level, which can also contribute to a reduction in the scale of hardware. Further, since the absolute value difference of the address data can be arbitrarily selected, there is an advantage that the accuracy of the reproduction address data can be freely set according to the system.

The present invention is not limited to the above embodiment,
Further, by increasing the number of stages of the address data memory, the error detection check step can be increased, and the error detection occurrence probability can be brought close to infinity.

When checking the correlation of address data,
Besides how to find out about all of AMIN, ASEC and AFRAME,
For example, it is possible to check only AFRAME and realize it with a simpler circuit configuration or software with almost no loss of inspection capability. This is not only AFRAM but A
The same applies to SEC, and the same effect can be expected by adopting their individual combinations.

EFFECTS OF THE INVENTION As described above, according to the present invention, address data determined as correct by an error check code are correlated with each other, and by monitoring the correlation, it is possible to determine a data error. It is possible to provide an address data processing method of a disk reproducing device capable of significantly reducing the probability.

[Brief description of drawings]

FIG. 1 is an explanatory diagram showing the structure of an embodiment of the present invention, FIG. 2 is an explanatory diagram shown in the explanation of the operation of the circuit shown in FIG. 1, and FIG. 3 is a diagram showing the format of control data of a compact disc. FIG. 4 is an explanatory diagram showing a change situation of address data,
FIG. 5 is an explanatory diagram shown for explaining an operation example of the circuit of FIG. 1, FIG. 6 is an explanatory diagram of address data, and FIG. 7 is an explanatory diagram showing an example of malfunction of a conventional disc reproducing apparatus. . 14 ... Data demodulator, 17 ... Error checker, 18, 20, 23
...... Address data memory, 19 …… Comparator, 21 …… Absolute value detector, 22 …… AND circuit, 24 …… Microcomputer.

Claims (1)

[Claims] 1. A pickup unit can be continuously or selectively moved with respect to a recording track of a disc on which digital information including address data is recorded, based on stored address data stored in an address processing unit. In the address data processing method of the disc reproducing apparatus, of the address data reproduced together with the digital information, the first address data and the second address data following the first address data are compared, and the magnitude relation between these data is a predetermined relation. And the second address data is determined as true data only when the difference between the values of these data is within a range of a predetermined value or equal, and the second address data is stored in the address processing unit by the storage address. If the determination is different from the above, the first address data is sent as the data. An address data processing method for a disc reproducing apparatus, characterized in that the address data is transmitted to a processing unit.