JPH0758597B2 - Peak voltage holding circuit - Google Patents

Description

The present invention relates to a peak voltage holding circuit, and more particularly to a peak voltage holding circuit using a capacitor.

[Conventional technology]

Conventionally, this type of peak voltage holding circuit applies an analog input voltage to a capacitor through an amplifier having a rectifying function, and rectifies the amplifier when the analog input voltage is lower than the voltage held by the capacitor. The circuit does not conduct due to the action and the capacitor continues to hold the previous voltage. Conversely, when the analog input voltage is higher than the voltage held by the capacitor, the rectifying action of the amplifier causes the circuit to conduct and the capacitor Is charged to the analog input voltage, the maximum value of the analog input voltage applied so far is held in the capacitor.

FIG. 5 is a circuit diagram of a conventional example of the peak voltage holding circuit described above. This peak voltage holding circuit comprises a voltage holding capacitor 11, amplifiers 13 and 14, rectifiers 15 and 16, an input terminal 10 for an analog input voltage Vx, and an output terminal 20 for a peak value voltage Vp. The amplifier 13 and the amplifier 14 each form a non-inverting amplifier circuit (voltage follower) having a gain of 1, and the output of the amplifier 14 is also connected to the inverting input terminal of the amplifier 13.

Next, the operation of this conventional example will be described. First, input terminal 10
When the analog input voltage Vx is applied to, the output voltage V ₂ of the amplifier 13 becomes equal to the analog input voltage Vx. At this time, when the value of the output voltage V ₂ of the amplifier 13 is higher than the voltage V ₁ held by the voltage holding capacitor 11, the rectifier 16 becomes conductive and the voltage holding capacitor 11 is further charged. However, since the charging is performed through the rectifier 16, the voltage V ₁ of the voltage holding capacitor 11 is charged only to a value smaller than the output voltage V ₂ of the amplifier 13 by the threshold voltage V _{T of the} rectifier, that is, V ₂ −V _T. By the way, since the output voltage V ₂ of the amplifier 13 is equal to the analog input voltage Vx and the output voltage Vp of the amplifier 14 is equal to the voltage V ₁ held by the voltage holding capacitor 11, the output voltage Vp of the amplifier 14 is It becomes Vx−V _T. On the other hand, since the output of the amplifier 14 is fed back to the inverting input terminal of the amplifier 13, the voltage applied to the inverting input terminal of the amplifier 13 is
Output voltage Vp, that is, Vx−V _T. Since the voltage applied to the non-inverting input terminal of the amplifier 13 is the analog input voltage Vx, the voltage applied to the inverting input terminal and the non-inverting input terminal of the amplifier 13 is unbalanced, and the difference between the applied voltages is V _T. Therefore, the output voltage of the amplifier 13 changes depending on the difference between the voltages applied to the inverting input terminal and the non-inverting input terminal. The change in the output voltage of the amplifier 13 is fed back to the inverting input terminal of the amplifier 13 through the amplifier 14, and when the voltage applied to the inverting input terminal of the amplifier 13 becomes equal to the analog input voltage Vx, the amplifier 13 enters a balanced state. The change in the output voltage at stops. Finally, the value of the output voltage V ₂ of the amplifier 13 becomes Vx + V _T , and the value of the holding voltage V ₁ of the voltage holding capacitor 11 becomes Vx, which is equal to the analog input voltage. Therefore, if the maximum value of the analog input voltage Vx is Vxp, the voltage holding capacitor 1
The holding voltage V ₁ of ₁ rises to Vxp, and at the same time, the output voltage Vp of the amplifier 14 also rises to Vxp. Amplifier 1 at this time
The output voltage V _{2 of} 3 is Vxp + V _T due to the feedback action from the amplifier 14 described above.

Next, when the analog input voltage Vx becomes lower than the maximum value Vxp, the output voltage V ₂ of the amplifier 13 becomes lower than Vxp + V _T , and the rectifier 16 becomes reverse biased and becomes non-conductive. Therefore, the change in the input voltage Vx is not transmitted to the voltage holding capacitor 11, and the voltage holding capacitor 11 continues to hold the maximum value Vxp of the analog input voltage Vx. The rectifier 15 is for clamping the output of the amplifier 13 so as not to swing to the negative side when the analog input voltage Vx becomes negative.

[Problems to be solved by the invention]

The conventional peak voltage holding circuit described above corrects the threshold voltage V _T of the rectifier 16 by feeding back the output of the amplifier 14 to the amplifier 13, so that the final balance after the analog input voltage Vx changes. By the time the state is reached, the output of the amplifier 13 changes, the voltage holding capacitor 11 is charged through the rectifier 16, the output of the amplifier 14 changes, and the amplifier 14
The feedback operation is repeated in which the output of is fed back to the input of the amplifier 13 and the output of the amplifier 13 is further changed. Therefore, when the frequency of the analog input voltage Vx becomes high and the change in the voltage becomes fast, the feedback operation needs to be performed at such a high speed. Therefore, it is necessary to use an amplifier capable of high-speed operation for the amplifier 13 and the amplifier 14. is there.

Fig. 6 shows the operational speed of the amplifier when the frequency of the analog input voltage Vx becomes high and the voltage changes rapidly, and the feedback operation cannot follow the change of the analog input voltage Vx. It is a figure which shows an operating waveform. The voltage V ₁ held by the voltage holding capacitor 11 and the output voltage Vp of the amplifier 14 must reach the peak value Vxp of the analog input voltage Vx because the analog input voltage Vx changes rapidly and the feedback operation cannot follow the change of the analog input. However, the error as shown in FIG. 6 occurs.

As described above, in the conventional peak voltage holding circuit, when the frequency of the analog input voltage becomes high and the change in the voltage becomes fast, it is necessary to use an amplifier capable of operating at high speed in order to prevent the occurrence of an error. Such an amplifier inevitably complicates the circuit and has a drawback that the chip area and power consumption increase when the peak voltage holding circuit is formed into a monolithic integrated circuit.

In addition, if the above-mentioned peak voltage holding circuit is to be formed in a silicon substrate using the MOS IC process technology, the rectifiers 15 and 16 are difficult to make with the normal MOS IC process technology, and the process technology becomes complicated. There is also.

[Means for solving problems]

The peak voltage holding circuit of the present invention includes an input terminal for inputting an analog signal, a capacitor for holding the voltage of the analog signal input to the input terminal, and a capacitor interposed in series between the input terminal and the capacitor. Switch means for
A comparator for comparing a voltage of the analog signal input to the input terminal with a voltage held in the capacitor; and an input terminal for inputting a control signal of a constant cycle, the comparator And the control signal to control the opening and closing of the switch means.

[Action]

A comparator is used to compare the magnitude of the analog input voltage and the voltage held by the capacitor, and only when the input analog voltage is higher than the voltage held by the voltage holding capacitor, the voltage between the input terminal and the voltage holding capacitor is By closing the switch means interposed in series to hold the analog input voltage in the voltage holding capacitor, there is no need for a rectifier such as a diode, and there is no need to repeat the feedback operation to compensate the threshold voltage of the rectifier. Therefore, high speed operation is possible. Further, since the diode is removed and the comparator and the switching means are added, the semiconductor integrated circuit can be easily formed because of the relatively simple structure.

〔Example〕

FIG. 1 is a circuit diagram of a first embodiment of a peak voltage holding circuit of the present invention.

The peak voltage holding circuit of this embodiment includes a voltage holding capacitor 1, an input terminal 10 for an analog input voltage Vx, and an input terminal 10.
2 which is interposed in series between the voltage holding capacitor 1 and the voltage holding capacitor 1, the equivalent series resistance 5 of the switch 2, the analog input voltage Vx and the voltage held by the voltage holding capacitor 1.
Comparator 4 for determining the magnitude of V ₁ and the input terminal 30 of control signal φ for controlling the opening / closing of switch 2, and controlling the opening / closing of switch 2 by receiving the control signal φ and the output of comparator 4. Logic gate 6, an output amplifier 3 for outputting the voltage V ₁ held by the voltage holding capacitor 1, and an output terminal
It consists of 20 and.

Here, the capacity of the voltage holding capacitor 1 is, for example, several PF, and the resistance value of the resistor 5 is, for example, about 1 KΩ, which is suitable for a semiconductor integrated circuit.

FIG. 2 is a waveform diagram showing changes in the voltage of each part of the peak voltage holding circuit of FIG. The changes in the analog input voltage Vx and the voltage V ₁ held by the voltage holding capacitor 1, the waveform of the control signal φ, the output waveform of the comparator 4, and the waveform of the output C of the logic gate that controls the opening and closing of the switch 2 are shown. There is.

The operation of this embodiment will be described below with reference to FIGS. 1 and 2. First, when the switch 2 is open and the analog input voltage Vx is applied to the input terminal 10, the comparator 4 compares the analog input voltage Vx and the voltage V ₁ held by the voltage holding capacitor 1 with each other. At this time, since the analog input voltage Vx is lower than the voltage V ₁ held by the voltage holding capacitor 1, the output of the comparator 4 becomes a high level, that is, the logic "1", and the logic gate 6 The output goes low and switch 2 remains open. Therefore, the change of the analog input voltage Vx does not have any influence on the voltage holding capacitor 1, and the voltage holding capacitor 1 continues to hold the voltage V ₁ held from before. Analog input voltage Vx
Becomes gradually higher and becomes higher than the voltage V ₁ held by the voltage holding capacitor 1, the output of the comparator 4 becomes low level, that is, the logic “0”, and when the control signal φ is “0”, the logic gate A control signal C is output from 6. Then, when the switch control signal C is at a high level, that is, the logic "1", the switch 2 is closed and the voltage holding capacitor 1 is charged via the switch 2. Since the switch 2 has the equivalent series resistance 5, the equivalent series resistance 5 and the voltage holding capacitor 1 form a time constant circuit, and the voltage V ₁ held by the voltage holding capacitor ₁ is the analog input voltage.
It follows the change in Vx with a delay of the time determined by the time constant circuit. If the value of the equivalent series resistance 5 of the switch 2 is made sufficiently small, the voltage holding capacitor 1 will be charged rapidly until it becomes equal to the analog input voltage Vx, and both ends of the equivalent series resistance 5 will correspond to the charge flow. A potential difference occurs. This potential difference becomes smaller as the analog input voltage Vx approaches the peak value Vxp and the difference between the analog input voltage Vx and the voltage V ₁ held by the voltage holding capacitor 1 becomes smaller, and the analog input voltage Vx becomes the peak value Vxp. After that, when the analog input voltage Vx becomes equal to the voltage V ₁ held by the voltage holding capacitor 1, the potential difference generated across the equivalent series resistor 5 becomes zero. By the way, the switch control signal C
If the potential difference does not become zero within one high level period of, that is, if the holding voltage V ₁ of the voltage holding capacitor ₁ does not reach the analog input voltage Vx, the output of the comparator 4 is in the low level state. Is maintained, and the switch control signal C is continuously supplied to the switch 2. However, when the analog input voltage Vx started to drop after passing the peak value Vxp and the voltage V ₁ held by the voltage holding capacitor 1 became equal to the analog input voltage Vx, it occurred at both ends of the equivalent series resistance 5. The potential difference becomes zero. Then, the output of the comparator 4 is inverted to a high level, that is, becomes a logic "1", the logic gate 6 is closed, and the switch control signal C is switched to the switch 2
Is not supplied to the switch 2, and the switch 2 is opened. Since the switch 2 is opened, the input terminal 10 for the analog input voltage Vx and the voltage holding capacitor 1 are separated from each other, and the voltage holding capacitor 1 holds a voltage substantially equal to the peak value Vxp of the analog input voltage. The voltage V ₁ held by the voltage holding capacitor 1 is output from the output terminal 20 via the gain 1 output amplifier 3 connected in the non-inverting circuit.

By the way, even if the analog input voltage Vx starts to drop after passing the peak value Vxp and the voltage V ₁ held by the voltage holding capacitor 1 becomes equal to the analog input voltage Vx, if the comparator 4 has an input offset, the output is Therefore, the switch 2 remains closed, and the voltage V ₁ held in the voltage holding capacitor 1 is dragged by the analog input voltage Vx that has become the peak value Vxp or less and falls, so that the peak hold cannot be performed. A phenomenon occurs. In order to avoid such a phenomenon, a period in which the switch control signal C is at a low level is provided, and during this low level period, the switch 2 is forcibly opened to prevent the change in the analog input voltage Vx from being transmitted to the voltage holding capacitor 1. By doing so, a difference is generated between the analog input voltage Vx and the voltage V ₁ held by the voltage holding capacitor 1 so that the output can be easily inverted even if the comparator 4 has an input offset. . Switch control signal C
During the low level period, the change of the analog input voltage Vx is not transmitted to the voltage holding capacitor 1, which causes an error. However, during the low level period of the switch control signal C, the analog input voltage Vx is changed.
If it is sufficiently short with respect to the maximum frequency component of, the error can be made small enough to be ignored.

FIG. 3 is a circuit diagram of the second embodiment of the present invention. In this embodiment, a semiconductor analog switch is used as the switch,
P-type MOS as a semiconductor element that constitutes an analog switch
The transistor 8 and the n-type MOS transistor 9 are connected in parallel and used. The output of the logic gate 6 is inverted by the inverter 7 and supplied to the gate of the p-type MOS transistor 8, and the logic gate 6 is supplied to the gate of the n-type MOS transistor 9.
The output of is supplied as it is. Since the semiconductor analog switch has an equivalent series resistance of several tens to several hundreds of ohms even in the conductive state, the circuit shown in FIG. 3 is equivalent to the circuit shown in FIG.

FIG. 4 is a circuit diagram of the third embodiment of the present invention. In this embodiment, two switches are provided as the circuit opening / closing means, and the output of the comparator 4 and the control signal φ are used to control the opening / closing of the other switches independently. The opening / closing is controlled by the output of the comparator 4. A switch and a second switch whose opening and closing are controlled by a control signal φ are provided. A p-type MOS transistor 8 and an n-type MOS transistor 9 are connected in parallel as a first switch, and the output of the comparator 4 is inverted by an inverter 7 and supplied to the gate of the p-type MOS transistor 8.
The output of the comparator 4 is directly supplied to the n-type MOS transistor 9. Also, a p-type MOS transistor 18 and an n-type MOS transistor 19 are connected in parallel as a second switch, and a control signal φ is inverted by an inverter 17 and supplied to the gate of the p-type MOS transistor 18 to supply an n-type MOS transistor. Transistor 1
The control signal φ is directly supplied to the gate of 9.

Needless to say, the same effect can be obtained even if the order of the first switch and the second switch is exchanged.

〔The invention's effect〕

As described above, the present invention connects a switch between the analog input terminal and the voltage holding capacitor, compares the analog input voltage and the voltage held by the voltage holding capacitor with a comparator, and determines By controlling the opening and closing of the switch based on the comparison result of the comparator, it is not necessary to feed back the output of the output amplifier to compensate the threshold voltage of the rectifier as in the conventional peak voltage holding circuit, and therefore at high speed. No need for an operating amplifier, and if the time constant of the time constant circuit consisting of the equivalent series resistance of the switch and the voltage holding capacitor is made small, the voltage holding capacitor holds even if the analog input voltage changes at high speed. Since the voltage can follow changes in the analog input voltage, it is possible to obtain a peak voltage holding circuit suitable for high-speed operation. Road easy to be configured as a simple monolithic integrated circuit relatively arrangement requires no, yet the effect capable of providing a peak voltage holding circuit capable of operating at high speed.

Further, the open / close of the switch is not directly controlled by the logical output of the comparator, but the open / close of the switch is controlled based on the two signals of the output signal of the comparator and the control signal having a constant period, so that the capacitor is held. Even if the voltage being applied is lower than the input voltage and thus the logic output of the comparator remains low, the control signal forces the switch to open, allowing a change in the analog input signal to the capacitor. This prevents the signal from being transmitted and causes a difference between the analog input voltage and the holding voltage of the capacitor, so that even if the comparator has an input offset, the output can be easily inverted by the comparator near the input signal. By doing,
The accuracy of the peak voltage has been dramatically improved.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a first embodiment of a peak voltage holding circuit of the present invention, FIG. 2 is a diagram showing changes in voltage of each part of the peak voltage holding circuit of FIG. 1, and FIG. Circuit diagram of the second embodiment of the peak voltage holding circuit, FIG. 4 is a circuit diagram of the third embodiment of the peak voltage holding circuit of the present invention, and FIG. 5 is a circuit diagram showing a conventional example of the peak voltage holding circuit. , FIG. 6 is a diagram showing changes in the voltage of each part of the conventional peak voltage holding circuit of FIG. 1 ... Voltage holding capacitor, 2 ... Switch, 3 ... Amplifier, 4 ... Comparator, 5 ... Equivalent series resistance of switch 2, 6 ... NOR gate, 7 ... Inverter, 8 ... PMOS transistor, 9 …… NMOS transistor, 10 …… Analog input terminal, 20 …… Hold voltage output terminal, 30 …… Control signal input terminal, 15,16 …… Rectifier, 18,19 …… MOS transistor, Vx …… Analog input voltage, φ: control signal, V _1: holding voltage, C: output of NOR gate 6, Vp: output voltage.

Claims (3)

[Claims] 1. An input terminal for inputting an analog signal, a capacitor for holding a voltage of the analog signal input to the input terminal, and switch means interposed in series between the input terminal and the capacitor. A comparator for comparing the voltage of the analog signal input to the input terminal with the voltage held in the capacitor, and an input terminal for inputting a control signal of a constant cycle, the comparator The peak voltage holding circuit is characterized in that the switch means is controlled to be opened / closed by the output of the control signal and the control signal to periodically interrupt the conduction between the input terminal and the capacitor. 2. The method according to claim 1, further comprising a logical product means for outputting the output of the comparator and the control signal, and controlling the opening / closing of the switch means by the output of the logical product means. Peak voltage holding circuit. 3. The peak voltage according to claim 1, wherein said switch means comprises two switches connected in series, each of which is controlled to open / close by an output of said comparator and said control signal. Holding circuit.