JPH0752990B2 - Subscriber circuit control information transmission system - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a subscriber circuit of a digital exchange, and in particular,
The present invention relates to a control information transmission method suitable for simplifying a control circuit.

[Conventional technology]

The conventional subscriber circuit is formed of 8-bit burst serial for each of the voice signal and the control information as described in "LSI for subscriber circuit of digital subscriber line switch" in NTT Research Practical Report Vol. 31 No. 11 The number of subscribers that can be accommodated on the same highway has been halved because it was transmitting and receiving at (8KHz
In case of 2,048MHz clock with sample 8 bits, it is originally 32
Channel accommodation is 16 channels. ) Moreover, JP-A-55-920
As shown in No. 68 "Voice / Data Combined Communication Method", a method of sending data in the absence of voice is also considered. A protection time is provided in order to confirm and guarantee, and this protection time requires a certain long idle state, which is insufficient to solve the above problem.

[Problems to be solved by the invention]

The above-mentioned prior art does not consider reduction of the number of bits when transmitting and receiving a voice signal and control information, and has a problem that the number of subscribers that can be accommodated in the same highway is halved.

An object of the present invention is to reduce the number of subscribers and
It is an object of the present invention to provide an economical subscriber circuit control information transmission method that enables control information to be transmitted and received on the same highway while maintaining the quality of a voice signal with simple control.

[Means for solving problems]

The above-mentioned object is that in the interface with the subscriber circuit of the digital exchange, the contents of the 2nd, 3rd and 4th bits of each code of the voice signal coded by the μ-law twice consecutively are all "1". That is, that is, a circuit for detecting whether or not the level of the voice signal is in a silent state, and a voice signal or a control signal to the subscriber circuit of the digital exchange or monitoring information from the subscriber circuit is selected and transmitted / received. If a circuit is provided and the audio signal is determined to be silent,
This is achieved by selecting and transmitting and receiving a control signal to the subscriber circuit of the digital exchange or monitoring information from the subscriber circuit in place of the voice signal during the transmission and reception of the voice signal.

[Action]

It detects whether or not the voice signal on the highway is in a silent state in a short period of two consecutive μ-law encoding periods, and if it is in a silent state, instead of the voice signal during that period, control information or monitoring is performed. Since it is configured to send and receive information, if there is a silent state such as interruption of conversation that occurs during normal voice transmission and reception, control information and monitoring information will be transmitted and received during that period, so it will be In order to transmit data, it is possible to realize a transmission method that enables control and monitoring of a subscriber circuit while maintaining voice quality without reducing or delaying the number of bits of a voice signal.

〔Example〕

 An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit configuration diagram for realizing a subscriber circuit control information transmission system according to an embodiment of the present invention. In FIG. 1, 8-bit shift registers 1 and 2 arranged in columns are adapted to input a PCM signal (voice signal) according to μ-law, and the output of the shift register 2 is input to a selector 6. ing. On the other hand, an identification pattern and control information are input to the 8-bit shift registers 7 and 8 arranged in columns, and the control information with the identification pattern at the head is transferred from the shift register 7 to the selector 6. Is entered. The selector 6 sends the information from the left registers 7 and 8 to the highway when the output signal of the AND gate 5 which will be described later is "1", and outputs the information (audio signal) from the left registers 2 and 1 to the highway when "0". Send to.

The control circuit of the selector 6 includes a 6-input AND gate 3 and 2
It consists of a frame width control output creation circuit 4 and a 2-input AND gate 5, and 3 of the 6 input lines of the AND gate 3
The books are connected to the second, third and fourth bits of the shift register 2, and the remaining three are connected to the second, third and fourth bits of the shift register 1. This is a 2-frame shift register 1, 2 in which the PCM audio signal conforming to μ-law is 8 bits each.
When the sampled values of these two continuous audio signals are less than or equal to the minimum segment, respectively, when they are stored in
This is to check that the fourth bit becomes "1", that is, the encoded audio signal level is in the silent state. When the output of the AND gate 3 becomes "1", the 2-frame width control output creating circuit 4 outputs a pulse which becomes "1" by the width of 2 frames, and uses this pulse as one input of the AND gate 5. Then, "1" is input to the other input of the AND gate 5 in the control information output mode.

With such a configuration, when the audio level is high, the output of the 6-input AND gate 3 is "0", so the output of the creating circuit 4 is also "0". Therefore, when the audio level is continuously high, the selector 6 is fixed to the audio side and the audio signal continues to be sent to the highway. When the audio level becomes low and the signal level for two consecutive frames falls below the minimum segment, the output of the AND circuit 3 becomes "1", and a pulse is output from the preparation circuit. At this time, if the control information output is present and the mode is set to "1", the output of the AND gate 5 becomes "1" and the selector 6 is switched, so that the control information with the identification pattern is transmitted. It is output to the highway. Even when the audio level is low, when the control information output is not necessary, the control information output mode becomes "0", so the output of the AND gate 5 is fixed to "0" and the audio signal is output to the highway. It

FIG. 2 shows a circuit configuration for extracting the control information transmitted on the highway and inserted in the audio signal. In order to extract the control information, the identification pattern attached to the control information may be identified. In the case of the present embodiment, the identification pattern is defined as a negative zero value in μ-law. "011
11111 "is used. This is because there is no restriction on the number of patterns. In FIG. 2, the signal transmitted through the highway is temporarily stored in the 8-bit shift register 11 and The output of the shift register 11 is input to the 2-input OR gate 16 and the 8-bit shift register 15. Each bit of the shift register 11 is input to the 8-input AND gate 12. However, the inverter 17 is provided at the first bit. The output of the AND gate 12 is input as a switch-on signal of the 2-frame width control output generation circuit 13 and the clock generation circuit 14 for latching after 2 frames, and the output of the circuit 13 is input to the other input of the OR gate 16. The output clock of the clock generation circuit 14 is applied to the shift register 15.

In such a circuit configuration, when the identification pattern "01111111" is input to the shift register 11 from the high phase, the AND gate 12 outputs "1". In response to this output, circuit 13
Outputs to the OR gate 16 a signal having a pulse width of "1" for two frames, that is, the identification pattern and the control information. As a result,
All the outputs of the OR gate 16 are forcibly set to "1" regardless of the identification pattern and the signal level of the control information. this is,
That is, the signal pattern of “11111111” is defined as a positive zero value in μ-law. Further, when the clock generation circuit 14 outputs the clock to the shift register 15 in response to the “1” output of the AND gate 12, the shift register 15 latches the control information after the identification pattern output from the shift register 11. Then, the control information latched by the shift register 15 is distributed as the control information of the subscriber circuit. When the signal input from the highway is other than the identification pattern, it is an audio signal and the output of the AND gate 12 remains "0". Therefore, it is directly output from the OR gate 16.

The above is the description of the control information to the subscriber circuit.
It goes without saying that this can also be applied to the monitoring information from the subscriber circuit.

Also, by changing the judgment level of the presence or absence of voice signal,
It is also obvious that the insertion degree of control information can be changed.

〔The invention's effect〕

According to the present invention, the control signal can be transmitted and received on the same highway by utilizing the period of the silence level of the voice signal generated on the interface of the subscriber circuit for a short period with a simple configuration, so that the quality of the voice signal is maintained. The control signal can be transmitted and received as it is, and the number of accommodated subscribers on the same highway can be doubled.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram of a transmitting side for realizing a subscriber circuit control information transmission system according to an embodiment of the present invention, and FIG. 2 is a circuit configuration diagram of a receiving side. 1,2,7,8,11,15 …… 8-bit shift register, 3,5,12…
… And gate, 4,13 …… 2 frame width control output creation circuit, 6 …… selector, 14 …… 2 frame later latch clock generation circuit, 16 …… OR gate, 17 …… inverter.

Claims (1)

[Claims] 1. In the subscriber circuit interface of the digital exchange, the subscriber circuit of the digital exchange transmits and receives a voice signal digitally encoded by the μ-law and a control signal for controlling and monitoring the subscriber circuit. A first shift register that receives the encoded audio signal as an input; a second shift register that is connected in series to the first shift register and that receives the output of the first shift register; Stored in each of the shift register and the second shift register of
Second and third voice signals digitally encoded according to the law
And an AND circuit for taking the logical product of the contents of the fourth bit, and the AND
A pulse generation circuit that generates a pulse having the same number of bits as the audio signal accumulated in the first shift register and the second shift register corresponding to the output of the circuit, and a third shift register that stores the control signal. A fourth shift register connected in series to the third shift register and storing an identifier indicating that the signal transmitted / received by the interface is the control signal, and corresponding to the output of the pulse generation circuit, A voice signal digitally encoded by the μ-law stored in each of the first shift register and the second shift register or the third shift register.
A selector for selecting a control signal and an identifier stored in each of the first shift register and the fourth shift register, and digitalized according to the μ-law stored in each of the first shift register and the second shift register. During a voice level period in which the second, third and fourth bits of the encoded voice signal are all "1", the selector selects and controls the outputs of the third shift register and the fourth shift register. A subscriber circuit control information transmission method characterized by transmitting and receiving signals.